1 /* 2 * Include file private to the SOC Interconnect support files. 3 * 4 * Copyright (C) 2020, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * 21 * <<Broadcom-WL-IPTag/Dual:>> 22 */ 23 24 #ifndef _siutils_priv_h_ 25 #define _siutils_priv_h_ 26 27 #if defined(BCMDBG_ERR) && defined(ERR_USE_LOG_EVENT) 28 #define SI_ERROR(args) EVENT_LOG_COMPACT_CAST_PAREN_ARGS(EVENT_LOG_TAG_SI_ERROR, args) 29 #elif defined(BCMDBG_ERR) || defined(SI_ERROR_ENFORCE) 30 #define SI_ERROR(args) printf args 31 #else 32 #define SI_ERROR(args) 33 #endif /* BCMDBG_ERR */ 34 35 #if defined(ENABLE_CORECAPTURE) 36 37 #if !defined(BCMDBG) 38 #define SI_PRINT(args) osl_wificc_logDebug args 39 #else 40 #define SI_PRINT(args) printf args 41 #endif /* !BCMDBG */ 42 43 #else 44 45 #define SI_PRINT(args) printf args 46 47 #endif /* ENABLE_CORECAPTURE */ 48 49 #ifdef BCMDBG 50 #define SI_MSG(args) printf args 51 #else 52 #define SI_MSG(args) 53 #endif /* BCMDBG */ 54 55 #ifdef BCMDBG_SI 56 #define SI_VMSG(args) printf args 57 #else 58 #define SI_VMSG(args) 59 #endif 60 61 #define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID)) 62 63 typedef void (*si_intrsoff_t)(void *intr_arg, bcm_int_bitmask_t *mask); 64 typedef void (*si_intrsrestore_t)(void *intr_arg, bcm_int_bitmask_t *mask); 65 typedef bool (*si_intrsenabled_t)(void *intr_arg); 66 67 #define SI_GPIO_MAX 16 68 69 typedef struct gci_gpio_item { 70 void *arg; 71 uint8 gci_gpio; 72 uint8 status; 73 gci_gpio_handler_t handler; 74 struct gci_gpio_item *next; 75 } gci_gpio_item_t; 76 77 typedef struct wci2_cbs { 78 void *context; 79 wci2_handler_t handler; 80 } wci2_cbs_t; 81 82 typedef struct wci2_rxfifo_info { 83 char *rx_buf; 84 int rx_idx; 85 wci2_cbs_t *cbs; 86 } wci2_rxfifo_info_t; 87 88 #define AI_SLAVE_WRAPPER 0 89 #define AI_MASTER_WRAPPER 1 90 91 typedef struct axi_wrapper { 92 uint32 mfg; 93 uint32 cid; 94 uint32 rev; 95 uint32 wrapper_type; 96 uint32 wrapper_addr; 97 uint32 wrapper_size; 98 uint32 node_type; 99 } axi_wrapper_t; 100 101 #ifdef SOCI_NCI_BUS 102 #define SI_MAX_AXI_WRAPPERS 65u 103 #else 104 #define SI_MAX_AXI_WRAPPERS 32u 105 #endif /* SOCI_NCI_BUS */ 106 #define AI_REG_READ_TIMEOUT 300u /* in msec */ 107 108 /* for some combo chips, BT side accesses chipcommon->0x190, as a 16 byte addr */ 109 /* register at 0x19C doesn't exist, so error is logged at the slave wrapper */ 110 /* Since this can't be fixed in the boot rom, WAR it */ 111 #define BT_CC_SPROM_BADREG_LO 0x18000190 112 #define BT_CC_SPROM_BADREG_SIZE 4 113 #define BT_CC_SPROM_BADREG_HI 0 114 115 #define BCM4389_BT_AXI_ID 2 116 #define BCM4388_BT_AXI_ID 2 117 #define BCM4369_BT_AXI_ID 4 118 #define BCM4378_BT_AXI_ID 2 119 #define BCM43602_BT_AXI_ID 1 120 #define BCM4378_ARM_PREFETCH_AXI_ID 9 121 122 #define BCM4378_BT_ADDR_HI 0 123 #define BCM4378_BT_ADDR_LO 0x19000000 /* BT address space */ 124 #define BCM4378_BT_SIZE 0x01000000 /* BT address space size */ 125 #define BCM4378_UNUSED_AXI_ID 0xffffffff 126 #define BCM4378_CC_AXI_ID 0 127 #define BCM4378_PCIE_AXI_ID 1 128 129 #define BCM4387_BT_ADDR_HI 0 130 #define BCM4387_BT_ADDR_LO 0x19000000 /* BT address space */ 131 #define BCM4387_BT_SIZE 0x01000000 /* BT address space size */ 132 #define BCM4387_UNUSED_AXI_ID 0xffffffff 133 #define BCM4387_CC_AXI_ID 0 134 #define BCM4387_PCIE_AXI_ID 1 135 136 #define BCM_AXI_ID_MASK 0xFu 137 #define BCM_AXI_ACCESS_TYPE_MASK 0xF0u 138 139 #define BCM43xx_CR4_AXI_ID 3 140 #define BCM43xx_AXI_ACCESS_TYPE_PREFETCH (1 << 4) 141 142 typedef struct si_cores_info { 143 volatile void *regs[SI_MAXCORES]; /* other regs va */ 144 145 uint coreid[SI_MAXCORES]; /**< id of each core */ 146 uint32 coresba[SI_MAXCORES]; /**< backplane address of each core */ 147 void *regs2[SI_MAXCORES]; /**< va of each core second register set (usbh20) */ 148 uint32 coresba2[SI_MAXCORES]; /**< address of each core second register set (usbh20) */ 149 uint32 coresba_size[SI_MAXCORES]; /**< backplane address space size */ 150 uint32 coresba2_size[SI_MAXCORES]; /**< second address space size */ 151 152 void *wrappers[SI_MAXCORES]; /**< other cores wrapper va */ 153 uint32 wrapba[SI_MAXCORES]; /**< address of controlling wrapper */ 154 155 void *wrappers2[SI_MAXCORES]; /**< other cores wrapper va */ 156 uint32 wrapba2[SI_MAXCORES]; /**< address of controlling wrapper */ 157 158 void *wrappers3[SI_MAXCORES]; /**< other cores wrapper va */ 159 uint32 wrapba3[SI_MAXCORES]; /**< address of controlling wrapper */ 160 161 uint32 cia[SI_MAXCORES]; /**< erom cia entry for each core */ 162 uint32 cib[SI_MAXCORES]; /**< erom cia entry for each core */ 163 164 uint32 csp2ba[SI_MAXCORES]; /**< Second slave port base addr 0 */ 165 uint32 csp2ba_size[SI_MAXCORES]; /**< Second slave port addr space size */ 166 } si_cores_info_t; 167 168 #define RES_PEND_STATS_COUNT 8 169 170 typedef struct res_state_info 171 { 172 uint32 low; 173 uint32 low_time; 174 uint32 high; 175 uint32 high_time; 176 } si_res_state_info_t; 177 178 /** misc si info needed by some of the routines */ 179 typedef struct si_info { 180 struct si_pub pub; /**< back plane public state (must be first field) */ 181 182 void *osh; /**< osl os handle */ 183 void *sdh; /**< bcmsdh handle */ 184 185 uint dev_coreid; /**< the core provides driver functions */ 186 void *intr_arg; /**< interrupt callback function arg */ 187 si_intrsoff_t intrsoff_fn; /**< turns chip interrupts off */ 188 si_intrsrestore_t intrsrestore_fn; /**< restore chip interrupts */ 189 si_intrsenabled_t intrsenabled_fn; /**< check if interrupts are enabled */ 190 191 void *pch; /**< PCI/E core handle */ 192 193 bool memseg; /**< flag to toggle MEM_SEG register */ 194 195 char *vars; 196 uint varsz; 197 198 volatile void *curmap; /* current regs va */ 199 200 uint curidx; /**< current core index */ 201 uint numcores; /**< # discovered cores */ 202 203 void *curwrap; /**< current wrapper va */ 204 205 uint32 oob_router; /**< oob router registers for axi */ 206 uint32 oob_router1; /**< oob router registers for axi */ 207 208 si_cores_info_t *cores_info; 209 #if !defined(BCMDONGLEHOST) 210 /* Store NVRAM data so that it is available after reclaim. */ 211 uint32 nvram_min_mask; 212 bool min_mask_valid; 213 uint32 nvram_max_mask; 214 bool max_mask_valid; 215 #endif /* !BCMDONGLEHOST */ 216 gci_gpio_item_t *gci_gpio_head; /**< gci gpio interrupts head */ 217 uint chipnew; /**< new chip number */ 218 uint second_bar0win; /**< Backplane region */ 219 uint num_br; /**< # discovered bridges */ 220 uint32 br_wrapba[SI_MAXBR]; /**< address of bridge controlling wrapper */ 221 uint32 xtalfreq; 222 uint32 openloop_dco_code; /**< OPEN loop calibration dco code */ 223 uint8 spurmode; 224 bool device_removed; 225 uint axi_num_wrappers; 226 axi_wrapper_t *axi_wrapper; 227 uint8 device_wake_opt; /* device_wake GPIO number */ 228 uint8 lhl_ps_mode; 229 uint8 hib_ext_wakeup_enab; 230 uint32 armpllclkfreq; /**< arm clock rate from nvram */ 231 uint32 ccidiv; /**< arm clock : cci clock ratio 232 * (determines sysmem frequency) 233 */ 234 wci2_rxfifo_info_t *wci2_info; /* wci2_rxfifo interrupt info */ 235 uint8 slice; /* this instance of the si accesses 236 * the first(0)/second(1)/... 237 * d11 core 238 */ 239 si_res_state_info_t res_state[RES_PEND_STATS_COUNT]; 240 uint32 res_pend_count; 241 bool rfldo3p3_war; /**< singing cap war enable from nvram */ 242 void *nci_info; 243 } si_info_t; 244 245 #define SI_INFO(sih) ((si_info_t *)(uintptr)sih) 246 247 #define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \ 248 ISALIGNED((x), SI_CORE_SIZE)) 249 #define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE)) 250 #define BADCOREADDR 0 251 #define GOODIDX(idx, maxcores) (((uint)idx) < maxcores) 252 #define NOREV (int16)-1 /**< Invalid rev */ 253 254 #define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 255 ((si)->pub.buscoretype == PCI_CORE_ID)) 256 257 #define PCIE_GEN1(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 258 ((si)->pub.buscoretype == PCIE_CORE_ID)) 259 260 #define PCIE_GEN2(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 261 ((si)->pub.buscoretype == PCIE2_CORE_ID)) 262 263 #define PCIE(si) (PCIE_GEN1(si) || PCIE_GEN2(si)) 264 265 /** Newer chips can access PCI/PCIE and CC core without requiring to change PCI BAR0 WIN */ 266 #define SI_FAST(si) (PCIE(si) || (PCI(si) && ((si)->pub.buscorerev >= 13))) 267 268 #define CCREGS_FAST(si) \ 269 (((si)->curmap == NULL) ? NULL : \ 270 ((volatile char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET)) 271 #define PCIEREGS(si) (((volatile char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET)) 272 273 /* 274 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/ 275 * after core switching to avoid invalid register accesss inside ISR. 276 * Adding SOCI_NCI_BUS to avoid abandons in the branches that use this MACRO. 277 */ 278 #ifdef SOCI_NCI_BUS 279 #define INTR_OFF(si, intr_val) \ 280 if ((si)->intrsoff_fn && (si_coreid(&(si)->pub) == (si)->dev_coreid)) { \ 281 (*(si)->intrsoff_fn)((si)->intr_arg, intr_val); } 282 #define INTR_RESTORE(si, intr_val) \ 283 if ((si)->intrsrestore_fn && (si_coreid(&(si)->pub) == (si)->dev_coreid)) { \ 284 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); } 285 #else 286 #define INTR_OFF(si, intr_val) \ 287 if ((si)->intrsoff_fn && (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \ 288 (*(si)->intrsoff_fn)((si)->intr_arg, intr_val); } 289 #define INTR_RESTORE(si, intr_val) \ 290 if ((si)->intrsrestore_fn && (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \ 291 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); } 292 #endif /* SOCI_NCI_BUS */ 293 294 /* dynamic clock control defines */ 295 #define LPOMINFREQ 25000 /**< low power oscillator min */ 296 #define LPOMAXFREQ 43000 /**< low power oscillator max */ 297 #define XTALMINFREQ 19800000 /**< 20 MHz - 1% */ 298 #define XTALMAXFREQ 20200000 /**< 20 MHz + 1% */ 299 #define PCIMINFREQ 25000000 /**< 25 MHz */ 300 #define PCIMAXFREQ 34000000 /**< 33 MHz + fudge */ 301 302 #define ILP_DIV_5MHZ 0 /**< ILP = 5 MHz */ 303 #define ILP_DIV_1MHZ 4 /**< ILP = 1 MHz */ 304 305 /* GPIO Based LED powersave defines */ 306 #define DEFAULT_GPIO_ONTIME 10 /**< Default: 10% on */ 307 #define DEFAULT_GPIO_OFFTIME 90 /**< Default: 10% on */ 308 309 #ifndef DEFAULT_GPIOTIMERVAL 310 #define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME) 311 #endif 312 313 /* Silicon Backplane externs */ 314 extern void sb_scan(si_t *sih, volatile void *regs, uint devid); 315 extern uint sb_coreid(const si_t *sih); 316 extern uint sb_intflag(si_t *sih); 317 extern uint sb_flag(const si_t *sih); 318 extern void sb_setint(const si_t *sih, int siflag); 319 extern uint sb_corevendor(const si_t *sih); 320 extern uint sb_corerev(const si_t *sih); 321 extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 322 extern volatile uint32 *sb_corereg_addr(const si_t *sih, uint coreidx, uint regoff); 323 extern bool sb_iscoreup(const si_t *sih); 324 extern volatile void *sb_setcoreidx(si_t *sih, uint coreidx); 325 extern uint32 sb_core_cflags(const si_t *sih, uint32 mask, uint32 val); 326 extern void sb_core_cflags_wo(const si_t *sih, uint32 mask, uint32 val); 327 extern uint32 sb_core_sflags(const si_t *sih, uint32 mask, uint32 val); 328 extern void sb_commit(si_t *sih); 329 extern uint32 sb_base(uint32 admatch); 330 extern uint32 sb_size(uint32 admatch); 331 extern void sb_core_reset(const si_t *sih, uint32 bits, uint32 resetbits); 332 extern void sb_core_disable(const si_t *sih, uint32 bits); 333 extern uint32 sb_addrspace(const si_t *sih, uint asidx); 334 extern uint32 sb_addrspacesize(const si_t *sih, uint asidx); 335 extern int sb_numaddrspaces(const si_t *sih); 336 337 extern bool sb_taclear(si_t *sih, bool details); 338 339 #ifdef BCMDBG 340 extern void sb_view(si_t *sih, bool verbose); 341 extern void sb_viewall(si_t *sih, bool verbose); 342 #endif 343 #if defined(BCMDBG) || defined(BCMDBG_DUMP) 344 extern void sb_dump(si_t *sih, struct bcmstrbuf *b); 345 #endif 346 #if defined(BCMDBG) || defined(BCMDBG_DUMP)|| defined(BCMDBG_PHYDUMP) 347 extern void sb_dumpregs(si_t *sih, struct bcmstrbuf *b); 348 #endif /* BCMDBG || BCMDBG_DUMP|| BCMDBG_PHYDUMP */ 349 350 /* AMBA Interconnect exported externs */ 351 extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype, 352 void *sdh, char **vars, uint *varsz); 353 extern si_t *ai_kattach(osl_t *osh); 354 extern void ai_scan(si_t *sih, void *regs, uint devid); 355 356 extern uint ai_flag(si_t *sih); 357 extern uint ai_flag_alt(const si_t *sih); 358 extern void ai_setint(const si_t *sih, int siflag); 359 extern uint ai_corevendor(const si_t *sih); 360 extern uint ai_corerev(const si_t *sih); 361 extern uint ai_corerev_minor(const si_t *sih); 362 extern volatile uint32 *ai_corereg_addr(si_t *sih, uint coreidx, uint regoff); 363 extern bool ai_iscoreup(const si_t *sih); 364 extern volatile void *ai_setcoreidx(si_t *sih, uint coreidx); 365 extern volatile void *ai_setcoreidx_2ndwrap(si_t *sih, uint coreidx); 366 extern volatile void *ai_setcoreidx_3rdwrap(si_t *sih, uint coreidx); 367 extern uint32 ai_core_cflags(const si_t *sih, uint32 mask, uint32 val); 368 extern void ai_core_cflags_wo(const si_t *sih, uint32 mask, uint32 val); 369 extern uint32 ai_core_sflags(const si_t *sih, uint32 mask, uint32 val); 370 extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 371 extern uint ai_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 372 extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 373 extern void ai_d11rsdb_core_reset(si_t *sih, uint32 bits, 374 uint32 resetbits, void *p, volatile void *s); 375 extern void ai_core_disable(const si_t *sih, uint32 bits); 376 extern void ai_d11rsdb_core_disable(const si_info_t *sii, uint32 bits, 377 aidmp_t *pmacai, aidmp_t *smacai); 378 extern int ai_numaddrspaces(const si_t *sih); 379 extern uint32 ai_addrspace(const si_t *sih, uint spidx, uint baidx); 380 extern uint32 ai_addrspacesize(const si_t *sih, uint spidx, uint baidx); 381 extern void ai_coreaddrspaceX(const si_t *sih, uint asidx, uint32 *addr, uint32 *size); 382 extern uint ai_wrap_reg(const si_t *sih, uint32 offset, uint32 mask, uint32 val); 383 extern void ai_update_backplane_timeouts(const si_t *sih, bool enable, uint32 timeout, uint32 cid); 384 extern uint32 ai_clear_backplane_to(si_t *sih); 385 void ai_force_clocks(const si_t *sih, uint clock_state); 386 extern uint ai_num_slaveports(const si_t *sih, uint coreidx); 387 388 #ifdef AXI_TIMEOUTS_NIC 389 uint32 ai_clear_backplane_to_fast(si_t *sih, void * addr); 390 #endif /* AXI_TIMEOUTS_NIC */ 391 392 #ifdef BOOKER_NIC400_INF 393 extern void ai_core_reset_ext(const si_t *sih, uint32 bits, uint32 resetbits); 394 #endif /* BOOKER_NIC400_INF */ 395 396 #if defined(AXI_TIMEOUTS) || defined(AXI_TIMEOUTS_NIC) 397 extern uint32 ai_clear_backplane_to_per_core(si_t *sih, uint coreid, uint coreunit, void * wrap); 398 #endif /* AXI_TIMEOUTS || AXI_TIMEOUTS_NIC */ 399 400 #ifdef BCMDBG 401 extern void ai_view(const si_t *sih, bool verbose); 402 extern void ai_viewall(si_t *sih, bool verbose); 403 #endif 404 #if defined(BCMDBG) || defined(BCMDBG_DUMP)|| defined(BCMDBG_PHYDUMP) 405 extern void ai_dumpregs(const si_t *sih, struct bcmstrbuf *b); 406 #endif /* BCMDBG || BCMDBG_DUMP|| BCMDBG_PHYDUMP */ 407 408 extern uint32 ai_wrapper_dump_buf_size(const si_t *sih); 409 extern uint32 ai_wrapper_dump_binary(const si_t *sih, uchar *p); 410 extern bool ai_check_enable_backplane_log(const si_t *sih); 411 extern uint32 ai_wrapper_dump_last_timeout(const si_t *sih, uint32 *error, uint32 *core, 412 uint32 *ba, uchar *p); 413 extern uint32 ai_findcoreidx_by_axiid(const si_t *sih, uint32 axiid); 414 #if defined(AXI_TIMEOUTS_NIC) || defined(AXI_TIMEOUTS) 415 extern void ai_wrapper_get_last_error(const si_t *sih, uint32 *error_status, uint32 *core, 416 uint32 *lo, uint32 *hi, uint32 *id); 417 extern uint32 ai_get_axi_timeout_reg(void); 418 #endif /* (AXI_TIMEOUTS_NIC) || (AXI_TIMEOUTS) */ 419 420 #ifdef UART_TRAP_DBG 421 void ai_dump_APB_Bridge_registers(const si_t *sih); 422 #endif /* UART_TRAP_DBG */ 423 void ai_force_clocks(const si_t *sih, uint clock_state); 424 425 #define ub_scan(a, b, c) do {} while (0) 426 #define ub_flag(a) (0) 427 #define ub_setint(a, b) do {} while (0) 428 #define ub_coreidx(a) (0) 429 #define ub_corevendor(a) (0) 430 #define ub_corerev(a) (0) 431 #define ub_iscoreup(a) (0) 432 #define ub_setcoreidx(a, b) (0) 433 #define ub_core_cflags(a, b, c) (0) 434 #define ub_core_cflags_wo(a, b, c) do {} while (0) 435 #define ub_core_sflags(a, b, c) (0) 436 #define ub_corereg(a, b, c, d, e) (0) 437 #define ub_core_reset(a, b, c) do {} while (0) 438 #define ub_core_disable(a, b) do {} while (0) 439 #define ub_numaddrspaces(a) (0) 440 #define ub_addrspace(a, b) (0) 441 #define ub_addrspacesize(a, b) (0) 442 #define ub_view(a, b) do {} while (0) 443 #define ub_dumpregs(a, b) do {} while (0) 444 445 #ifndef SOCI_NCI_BUS 446 #define nci_uninit(a) do {} while (0) 447 #define nci_scan(a) (0) 448 #define nci_dump_erom(a) do {} while (0) 449 #define nci_init(a, b, c) (NULL) 450 #define nci_setcore(a, b, c) (NULL) 451 #define nci_setcoreidx(a, b) (NULL) 452 #define nci_findcoreidx(a, b, c) (0) 453 #define nci_corereg_addr(a, b, c) (NULL) 454 #define nci_corereg_writeonly(a, b, c, d, e) (0) 455 #define nci_corereg(a, b, c, d, e) (0) 456 #define nci_corerev_minor(a) (0) 457 #define nci_corerev(a) (0) 458 #define nci_corevendor(a) (0) 459 #define nci_get_wrap_reg(a, b, c, d) (0) 460 #define nci_core_reset(a, b, c) do {} while (0) 461 #define nci_core_disable(a, b) do {} while (0) 462 #define nci_iscoreup(a) (FALSE) 463 #define nci_coreid(a, b) (0) 464 #define nci_numcoreunits(a, b) (0) 465 #define nci_addr_space(a, b, c) (0) 466 #define nci_addr_space_size(a, b, c) (0) 467 #define nci_iscoreup(a) (FALSE) 468 #define nci_intflag(a) (0) 469 #define nci_flag(a) (0) 470 #define nci_flag_alt(a) (0) 471 #define nci_setint(a, b) do {} while (0) 472 #define nci_oobr_baseaddr(a, b) (0) 473 #define nci_coreunit(a) (0) 474 #define nci_corelist(a, b) (0) 475 #define nci_numaddrspaces(a) (0) 476 #define nci_addrspace(a, b, c) (0) 477 #define nci_addrspacesize(a, b, c) (0) 478 #define nci_coreaddrspaceX(a, b, c, d) do {} while (0) 479 #define nci_core_cflags(a, b, c) (0) 480 #define nci_core_cflags_wo(a, b, c) do {} while (0) 481 #define nci_core_sflags(a, b, c) (0) 482 #define nci_wrapperreg(a, b, c, d) (0) 483 #define nci_invalidate_second_bar0win(a) do {} while (0) 484 #define nci_backplane_access(a, b, c, d, e) (0) 485 #define nci_backplane_access_64(a, b, c, d, e) (0) 486 #define nci_num_slaveports(a, b) (0) 487 #if defined(BCMDBG) || defined(BCMDBG_DUMP) || defined(BCMDBG_PHYDUMP) 488 #define nci_dumpregs(a, b) do {} while (0) 489 #endif /* BCMDBG || BCMDBG_DUMP || BCMDBG_PHYDUMP */ 490 #ifdef BCMDBG 491 #define nci_view(a, b) do {} while (0) 492 #define nci_viewall(a, b) do {} while (0) 493 #endif /* BCMDBG */ 494 #define nci_get_nth_wrapper(a, b) (0) 495 #define nci_get_axi_addr(a, b) (0) 496 #define nci_wrapper_dump_binary_one(a, b, c) (NULL) 497 #define nci_wrapper_dump_binary(a, b) (0) 498 #define nci_wrapper_dump_last_timeout(a, b, c, d, e) (0) 499 #define nci_check_enable_backplane_log(a) (FALSE) 500 #define nci_get_core_baaddr(a, b, c) (0) 501 #define nci_clear_backplane_to(a) (0) 502 #define nci_clear_backplane_to_per_core(a, b, c, d) (0) 503 #define nci_ignore_errlog(a, b, c, d, e, f) (FALSE) 504 #define nci_wrapper_get_last_error(a, b, c, d, e, f) do {} while (0) 505 #define nci_get_axi_timeout_reg() (0) 506 #define nci_findcoreidx_by_axiid(a, b) (0) 507 #define nci_wrapper_dump_binary_one(a, b, c) (NULL) 508 #define nci_wrapper_dump_binary(a, b) (0) 509 #define nci_wrapper_dump_last_timeout(a, b, c, d, e) (0) 510 #define nci_check_enable_backplane_log(a) (FALSE) 511 #define nci_wrapper_dump_buf_size(a) (0) 512 #endif /* SOCI_NCI_BUS */ 513 #endif /* _siutils_priv_h_ */ 514