1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2014 Broadcom Corporation. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __SYSMAP_H 8*4882a593Smuzhiyun #define __SYSMAP_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define IHOST_PROC_CLK_PLLARMA 0X19000C00 11*4882a593Smuzhiyun #define IHOST_PROC_CLK_PLLARMB 0X19000C04 12*4882a593Smuzhiyun #define IHOST_PROC_CLK_PLLARMA__PLLARM_PDIV_R 24 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define IHOST_PROC_CLK_WR_ACCESS 0X19000000 15*4882a593Smuzhiyun #define IHOST_PROC_CLK_POLICY_FREQ 0X19000008 16*4882a593Smuzhiyun #define IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE 31 17*4882a593Smuzhiyun #define IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R 24 18*4882a593Smuzhiyun #define IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R 16 19*4882a593Smuzhiyun #define IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R 8 20*4882a593Smuzhiyun #define IHOST_PROC_CLK_POLICY_CTL 0X1900000C 21*4882a593Smuzhiyun #define IHOST_PROC_CLK_POLICY_CTL__GO 0 22*4882a593Smuzhiyun #define IHOST_PROC_CLK_POLICY_CTL__GO_AC 1 23*4882a593Smuzhiyun #define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R 0 24*4882a593Smuzhiyun #define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH 20 25*4882a593Smuzhiyun #define IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK 28 26*4882a593Smuzhiyun #define IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R 0 27*4882a593Smuzhiyun #define IHOST_PROC_CLK_PLLARMA__PLLARM_NDIV_INT_R 8 28*4882a593Smuzhiyun #define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB 1 29*4882a593Smuzhiyun #define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB 0 30*4882a593Smuzhiyun #define IHOST_PROC_CLK_CORE0_CLKGATE 0X19000200 31*4882a593Smuzhiyun #define IHOST_PROC_CLK_CORE1_CLKGATE 0X19000204 32*4882a593Smuzhiyun #define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE 0X19000210 33*4882a593Smuzhiyun #define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE 0X19000300 34*4882a593Smuzhiyun #define IHOST_PROC_CLK_APB0_CLKGATE 0X19000400 35*4882a593Smuzhiyun #define IPROC_CLKCT_HDELAY_SW_EN 0x00000303 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define IPROC_REG_WRITE_ACCESS 0x00a5a501 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define IPROC_PERIPH_BASE 0x19020000 40*4882a593Smuzhiyun #define IPROC_PERIPH_INT_CTRL_REG_BASE (IPROC_PERIPH_BASE + 0x100) 41*4882a593Smuzhiyun #define IPROC_PERIPH_GLB_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x200) 42*4882a593Smuzhiyun #define IPROC_PERIPH_PVT_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x600) 43*4882a593Smuzhiyun #define IPROC_PERIPH_INT_DISTR_REG_BASE (IPROC_PERIPH_BASE + 0x1000) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define PLL_AXI_CLK 0x1DCD6500 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #endif /* __SYSMAP_H */ 48