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/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-imx/
H A Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
H A Dmx2x.h16 #define MX2x_AIPI_BASE_ADDR 0x10000000
18 #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
19 #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
20 #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
21 #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
22 #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
23 #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
24 #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
25 #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
26 #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h12 #define ROMCP_ARB_BASE_ADDR 0x00000000
13 #define ROMCP_ARB_END_ADDR 0x000FFFFF
16 #define GPU_2D_ARB_BASE_ADDR 0x02200000
17 #define GPU_2D_ARB_END_ADDR 0x02203FFF
18 #define OPENVG_ARB_BASE_ADDR 0x02204000
19 #define OPENVG_ARB_END_ADDR 0x02207FFF
21 #define CAAM_ARB_BASE_ADDR 0x00100000
22 #define CAAM_ARB_END_ADDR 0x00107FFF
23 #define GPU_ARB_BASE_ADDR 0x01800000
24 #define GPU_ARB_END_ADDR 0x01803FFF
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dma/
H A Dmpc512x-dma.txt24 reg = <0x14000 0x1800>;
25 interrupts = <65 0x8>;
/OK3568_Linux_fs/kernel/arch/arm/mach-mmp/
H A Dregs-timers.h11 #define TIMERS1_VIRT_BASE (APB_VIRT_BASE + 0x14000)
12 #define TIMERS2_VIRT_BASE (APB_VIRT_BASE + 0x16000)
14 #define TMR_CCR (0x0000)
15 #define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2))
16 #define TMR_CR(n) (0x0028 + ((n) << 2))
17 #define TMR_SR(n) (0x0034 + ((n) << 2))
18 #define TMR_IER(n) (0x0040 + ((n) << 2))
19 #define TMR_PLVR(n) (0x004c + ((n) << 2))
20 #define TMR_PLCR(n) (0x0058 + ((n) << 2))
21 #define TMR_WMER (0x0064)
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interconnect/
H A Dqcom,msm8916.yaml54 reg = <0x00400000 0x62000>;
63 reg = <0x00500000 0x11000>;
72 reg = <0x00580000 0x14000>;
H A Dinterconnect.txt30 reg = <0x580000 0x14000>;
83 cpu@0 {
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/marvell/
H A Darmada-37xx.txt34 reg = <0x14000 0x60>;
49 reg = <0x11500 0x40>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/ufs/
H A Dti,j721e-ufs.yaml49 "^ufs@[0-9a-f]+$":
69 reg = <0x0 0x4e80000 0x0 0x100>;
75 ranges = <0x0 0x0 0x0 0x4e80000 0x0 0x14000>;
81 reg = <0x0 0x4000 0x0 0x10000>;
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3528-linux.dtsi9 …bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw roo…
14 rockchip,serial-id = <0>;
15 rockchip,wake-irq = <0>;
21 pinctrl-0 = <&uart0m0_xfer>;
39 reg = <0x0 0x0 0x0 0x0>;
44 reg = <0x0 0x0 0x0 0x0>;
49 /* 0x110000 to 0x1f0000 is for ramoops */
50 reg = <0x0 0x110000 0x0 0xe0000>;
51 boot-log-size = <0x8000>; /* do not change */
52 boot-log-count = <0x1>; /* do not change */
[all …]
H A Drk3528-android.dtsi9 …rlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 driver_async_probe=dwmmc_rockchip,rockchip-drm d…
14 rockchip,serial-id = <0>;
15 rockchip,wake-irq = <0>;
21 pinctrl-0 = <&uart0m0_xfer>;
40 size = <0x0 0x00800000>;
46 reg = <0x0 0x0 0x0 0x0>;
51 reg = <0x0 0x0 0x0 0x0>;
56 /* 0x110000 to 0x1f0000 is for ramoops */
57 reg = <0x0 0x110000 0x0 0xe0000>;
58 boot-log-size = <0x8000>; /* do not change */
[all …]
H A Drk3588-android.dtsi9 bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0";
14 reg = <0x0 0xfd10c000 0x0 0x1000>,
15 <0x0 0xfd10d000 0x0 0x1000>,
16 <0x0 0xfd10e000 0x0 0x1000>,
17 <0x0 0xfd10f000 0x0 0x1000>,
18 <0x0 0xfd12c000 0x0 0x1000>,
19 <0x0 0xfd12d000 0x0 0x1000>,
20 <0x0 0xfd12e000 0x0 0x1000>,
21 <0x0 0xfd12f000 0x0 0x1000>;
26 reg = <0x0 0xfd104000 0x0 0x1000>,
[all …]
/OK3568_Linux_fs/kernel/sound/soc/intel/atom/sst/
H A Dsst_acpi.c38 #define SST_BYT_IRAM_PHY_START 0xff2c0000
39 #define SST_BYT_IRAM_PHY_END 0xff2d4000
40 #define SST_BYT_DRAM_PHY_START 0xff300000
41 #define SST_BYT_DRAM_PHY_END 0xff320000
42 #define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */
43 #define SST_BYT_IMR_VIRT_END 0xc01fffff
44 #define SST_BYT_SHIM_PHY_ADDR 0xff340000
45 #define SST_BYT_MBOX_PHY_ADDR 0xff344000
46 #define SST_BYT_DMA0_PHY_ADDR 0xff298000
47 #define SST_BYT_DMA1_PHY_ADDR 0xff29c000
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/netlogic/xlr/
H A Diomap.h38 #define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
39 #define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000
40 #define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000
41 #define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000
42 #define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000
43 #define NETLOGIC_IO_PIC_OFFSET 0x08000
44 #define NETLOGIC_IO_UART_0_OFFSET 0x14000
45 #define NETLOGIC_IO_UART_1_OFFSET 0x15100
47 #define NETLOGIC_IO_SIZE 0x1000
49 #define NETLOGIC_IO_BRIDGE_OFFSET 0x00000
[all …]
/OK3568_Linux_fs/kernel/drivers/remoteproc/
H A Dmtk_common.h15 #define MT8183_SW_RSTN 0x0
16 #define MT8183_SW_RSTN_BIT BIT(0)
17 #define MT8183_SCP_TO_HOST 0x1C
18 #define MT8183_SCP_IPC_INT_BIT BIT(0)
20 #define MT8183_HOST_TO_SCP 0x28
21 #define MT8183_HOST_IPC_INT_BIT BIT(0)
22 #define MT8183_WDT_CFG 0x84
23 #define MT8183_SCP_CLK_SW_SEL 0x4000
24 #define MT8183_SCP_CLK_DIV_SEL 0x4024
25 #define MT8183_SCP_SRAM_PDN 0x402C
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-omap4/
H A Domap.h27 #define OMAP44XX_L4_CORE_BASE 0x4A000000
28 #define OMAP44XX_L4_WKUP_BASE 0x4A300000
29 #define OMAP44XX_L4_PER_BASE 0x48000000
31 #define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
32 #define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000
37 #define CONTROL_ID_CODE 0x4A002204
39 #define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F
40 #define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F
41 #define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F
42 #define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dqoriq-bman1-portals.dtsi40 bman-portal@0 {
42 reg = <0x0 0x4000>, <0x100000 0x1000>;
43 interrupts = <105 2 0 0>;
47 reg = <0x4000 0x4000>, <0x101000 0x1000>;
48 interrupts = <107 2 0 0>;
52 reg = <0x8000 0x4000>, <0x102000 0x1000>;
53 interrupts = <109 2 0 0>;
57 reg = <0xc000 0x4000>, <0x103000 0x1000>;
58 interrupts = <111 2 0 0>;
62 reg = <0x10000 0x4000>, <0x104000 0x1000>;
[all …]
H A Dqoriq-qman1-portals.dtsi40 qportal0: qman-portal@0 {
42 reg = <0x0 0x4000>, <0x100000 0x1000>;
43 interrupts = <104 2 0 0>;
44 cell-index = <0x0>;
48 reg = <0x4000 0x4000>, <0x101000 0x1000>;
49 interrupts = <106 2 0 0>;
54 reg = <0x8000 0x4000>, <0x102000 0x1000>;
55 interrupts = <108 2 0 0>;
60 reg = <0xc000 0x4000>, <0x103000 0x1000>;
61 interrupts = <110 2 0 0>;
[all …]
H A Dinterlaken-lac-portals.dtsi34 #address-cells = <0x1>;
35 #size-cells = <0x1>;
38 lportal0: lac-portal@0 {
39 compatible = "fsl,interlaken-lac-portal-v1.0";
40 reg = <0x0 0x1000>;
44 compatible = "fsl,interlaken-lac-portal-v1.0";
45 reg = <0x1000 0x1000>;
49 compatible = "fsl,interlaken-lac-portal-v1.0";
50 reg = <0x2000 0x1000>;
54 compatible = "fsl,interlaken-lac-portal-v1.0";
[all …]
/OK3568_Linux_fs/kernel/drivers/reset/
H A Dreset-qcom-aoss.c30 [AOSS_CC_MSS_RESTART] = {0x10000},
31 [AOSS_CC_CAMSS_RESTART] = {0x11000},
32 [AOSS_CC_VENUS_RESTART] = {0x12000},
33 [AOSS_CC_GPU_RESTART] = {0x13000},
34 [AOSS_CC_DISPSS_RESTART] = {0x14000},
35 [AOSS_CC_WCSS_RESTART] = {0x20000},
36 [AOSS_CC_LPASS_RESTART] = {0x30000},
59 return 0; in qcom_aoss_control_assert()
68 writel(0, data->base + map->reg); in qcom_aoss_control_deassert()
71 return 0; in qcom_aoss_control_deassert()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-omap5/
H A Dcpu.h24 u32 tidr; /* 0x00 r */
25 u8 res1[0xc];
26 u32 tiocp_cfg; /* 0x10 rw */
27 u8 res2[0x10];
28 u32 tisr_raw; /* 0x24 r */
29 u32 tisr; /* 0x28 rw */
30 u32 tier; /* 0x2c rw */
31 u32 ticr; /* 0x30 rw */
32 u32 twer; /* 0x34 rw */
33 u32 tclr; /* 0x38 rw */
[all …]
/OK3568_Linux_fs/kernel/sound/soc/amd/
H A Dacp.h8 #define ACP_PAGE_SIZE_4K_ENABLE 0x02
11 #define ACP_CAPTURE_PTE_OFFSET 0
14 #define ACP_ST_PLAYBACK_PTE_OFFSET 0x04
15 #define ACP_ST_CAPTURE_PTE_OFFSET 0x00
16 #define ACP_ST_BT_PLAYBACK_PTE_OFFSET 0x08
17 #define ACP_ST_BT_CAPTURE_PTE_OFFSET 0x0c
19 #define ACP_GARLIC_CNTL_DEFAULT 0x00000FB4
20 #define ACP_ONION_CNTL_DEFAULT 0x00000FB4
22 #define ACP_PHYSICAL_BASE 0x14000
32 #define ACP_SRAM_BANK_1_ADDRESS 0x4002000
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/
H A Dpstore.c11 * reg = <0x0 0x110000 0x0 0xe0000>;
12 * boot-log-size = <0x8000>;
13 * boot-log-count = <0x1>
14 * console-size = <0x80000>;
15 * pmsg-size = <0x30000>;
16 * ftrace-size = <0x00000>;
17 * record-size = <0x14000>;
26 #define PERSISTENT_RAM_SIG (0x43474244)
27 #define LOG_TYPE_MASK (0x00000fff)
33 u8 data[0];
[all …]
/OK3568_Linux_fs/kernel/drivers/pinctrl/tegra/
H A Dpinctrl-tegra194.c89 .mux_bit = 0, \
101 .parked_bitmask = 0
104 DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
106 DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
127 PINGROUP(pex_l5_clkreq_n_pgg0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0,
129 PINGROUP(pex_l5_rst_n_pgg1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0,

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