1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * sst_acpi.c - SST (LPE) driver init file for ACPI enumeration.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2013, Intel Corporation.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Authors: Ramesh Babu K V <Ramesh.Babu@intel.com>
8*4882a593Smuzhiyun * Authors: Omair Mohammed Abdullah <omair.m.abdullah@intel.com>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/fs.h>
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/firmware.h>
18*4882a593Smuzhiyun #include <linux/pm_runtime.h>
19*4882a593Smuzhiyun #include <linux/pm_qos.h>
20*4882a593Smuzhiyun #include <linux/dmi.h>
21*4882a593Smuzhiyun #include <linux/acpi.h>
22*4882a593Smuzhiyun #include <asm/platform_sst_audio.h>
23*4882a593Smuzhiyun #include <sound/core.h>
24*4882a593Smuzhiyun #include <sound/soc.h>
25*4882a593Smuzhiyun #include <sound/compress_driver.h>
26*4882a593Smuzhiyun #include <acpi/acbuffer.h>
27*4882a593Smuzhiyun #include <acpi/platform/acenv.h>
28*4882a593Smuzhiyun #include <acpi/platform/aclinux.h>
29*4882a593Smuzhiyun #include <acpi/actypes.h>
30*4882a593Smuzhiyun #include <acpi/acpi_bus.h>
31*4882a593Smuzhiyun #include <sound/soc-acpi.h>
32*4882a593Smuzhiyun #include <sound/soc-acpi-intel-match.h>
33*4882a593Smuzhiyun #include "../sst-mfld-platform.h"
34*4882a593Smuzhiyun #include "../../common/soc-intel-quirks.h"
35*4882a593Smuzhiyun #include "sst.h"
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* LPE viewpoint addresses */
38*4882a593Smuzhiyun #define SST_BYT_IRAM_PHY_START 0xff2c0000
39*4882a593Smuzhiyun #define SST_BYT_IRAM_PHY_END 0xff2d4000
40*4882a593Smuzhiyun #define SST_BYT_DRAM_PHY_START 0xff300000
41*4882a593Smuzhiyun #define SST_BYT_DRAM_PHY_END 0xff320000
42*4882a593Smuzhiyun #define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */
43*4882a593Smuzhiyun #define SST_BYT_IMR_VIRT_END 0xc01fffff
44*4882a593Smuzhiyun #define SST_BYT_SHIM_PHY_ADDR 0xff340000
45*4882a593Smuzhiyun #define SST_BYT_MBOX_PHY_ADDR 0xff344000
46*4882a593Smuzhiyun #define SST_BYT_DMA0_PHY_ADDR 0xff298000
47*4882a593Smuzhiyun #define SST_BYT_DMA1_PHY_ADDR 0xff29c000
48*4882a593Smuzhiyun #define SST_BYT_SSP0_PHY_ADDR 0xff2a0000
49*4882a593Smuzhiyun #define SST_BYT_SSP2_PHY_ADDR 0xff2a2000
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #define BYT_FW_MOD_TABLE_OFFSET 0x80000
52*4882a593Smuzhiyun #define BYT_FW_MOD_TABLE_SIZE 0x100
53*4882a593Smuzhiyun #define BYT_FW_MOD_OFFSET (BYT_FW_MOD_TABLE_OFFSET + BYT_FW_MOD_TABLE_SIZE)
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static const struct sst_info byt_fwparse_info = {
56*4882a593Smuzhiyun .use_elf = false,
57*4882a593Smuzhiyun .max_streams = 25,
58*4882a593Smuzhiyun .iram_start = SST_BYT_IRAM_PHY_START,
59*4882a593Smuzhiyun .iram_end = SST_BYT_IRAM_PHY_END,
60*4882a593Smuzhiyun .iram_use = true,
61*4882a593Smuzhiyun .dram_start = SST_BYT_DRAM_PHY_START,
62*4882a593Smuzhiyun .dram_end = SST_BYT_DRAM_PHY_END,
63*4882a593Smuzhiyun .dram_use = true,
64*4882a593Smuzhiyun .imr_start = SST_BYT_IMR_VIRT_START,
65*4882a593Smuzhiyun .imr_end = SST_BYT_IMR_VIRT_END,
66*4882a593Smuzhiyun .imr_use = true,
67*4882a593Smuzhiyun .mailbox_start = SST_BYT_MBOX_PHY_ADDR,
68*4882a593Smuzhiyun .num_probes = 0,
69*4882a593Smuzhiyun .lpe_viewpt_rqd = true,
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun static const struct sst_ipc_info byt_ipc_info = {
73*4882a593Smuzhiyun .ipc_offset = 0,
74*4882a593Smuzhiyun .mbox_recv_off = 0x400,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun static const struct sst_lib_dnld_info byt_lib_dnld_info = {
78*4882a593Smuzhiyun .mod_base = SST_BYT_IMR_VIRT_START,
79*4882a593Smuzhiyun .mod_end = SST_BYT_IMR_VIRT_END,
80*4882a593Smuzhiyun .mod_table_offset = BYT_FW_MOD_TABLE_OFFSET,
81*4882a593Smuzhiyun .mod_table_size = BYT_FW_MOD_TABLE_SIZE,
82*4882a593Smuzhiyun .mod_ddr_dnld = false,
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun static const struct sst_res_info byt_rvp_res_info = {
86*4882a593Smuzhiyun .shim_offset = 0x140000,
87*4882a593Smuzhiyun .shim_size = 0x000100,
88*4882a593Smuzhiyun .shim_phy_addr = SST_BYT_SHIM_PHY_ADDR,
89*4882a593Smuzhiyun .ssp0_offset = 0xa0000,
90*4882a593Smuzhiyun .ssp0_size = 0x1000,
91*4882a593Smuzhiyun .dma0_offset = 0x98000,
92*4882a593Smuzhiyun .dma0_size = 0x4000,
93*4882a593Smuzhiyun .dma1_offset = 0x9c000,
94*4882a593Smuzhiyun .dma1_size = 0x4000,
95*4882a593Smuzhiyun .iram_offset = 0x0c0000,
96*4882a593Smuzhiyun .iram_size = 0x14000,
97*4882a593Smuzhiyun .dram_offset = 0x100000,
98*4882a593Smuzhiyun .dram_size = 0x28000,
99*4882a593Smuzhiyun .mbox_offset = 0x144000,
100*4882a593Smuzhiyun .mbox_size = 0x1000,
101*4882a593Smuzhiyun .acpi_lpe_res_index = 0,
102*4882a593Smuzhiyun .acpi_ddr_index = 2,
103*4882a593Smuzhiyun .acpi_ipc_irq_index = 5,
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* BYTCR has different BIOS from BYT */
107*4882a593Smuzhiyun static const struct sst_res_info bytcr_res_info = {
108*4882a593Smuzhiyun .shim_offset = 0x140000,
109*4882a593Smuzhiyun .shim_size = 0x000100,
110*4882a593Smuzhiyun .shim_phy_addr = SST_BYT_SHIM_PHY_ADDR,
111*4882a593Smuzhiyun .ssp0_offset = 0xa0000,
112*4882a593Smuzhiyun .ssp0_size = 0x1000,
113*4882a593Smuzhiyun .dma0_offset = 0x98000,
114*4882a593Smuzhiyun .dma0_size = 0x4000,
115*4882a593Smuzhiyun .dma1_offset = 0x9c000,
116*4882a593Smuzhiyun .dma1_size = 0x4000,
117*4882a593Smuzhiyun .iram_offset = 0x0c0000,
118*4882a593Smuzhiyun .iram_size = 0x14000,
119*4882a593Smuzhiyun .dram_offset = 0x100000,
120*4882a593Smuzhiyun .dram_size = 0x28000,
121*4882a593Smuzhiyun .mbox_offset = 0x144000,
122*4882a593Smuzhiyun .mbox_size = 0x1000,
123*4882a593Smuzhiyun .acpi_lpe_res_index = 0,
124*4882a593Smuzhiyun .acpi_ddr_index = 2,
125*4882a593Smuzhiyun .acpi_ipc_irq_index = 0
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun static struct sst_platform_info byt_rvp_platform_data = {
129*4882a593Smuzhiyun .probe_data = &byt_fwparse_info,
130*4882a593Smuzhiyun .ipc_info = &byt_ipc_info,
131*4882a593Smuzhiyun .lib_info = &byt_lib_dnld_info,
132*4882a593Smuzhiyun .res_info = &byt_rvp_res_info,
133*4882a593Smuzhiyun .platform = "sst-mfld-platform",
134*4882a593Smuzhiyun .streams_lost_on_suspend = true,
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /* Cherryview (Cherrytrail and Braswell) uses same mrfld dpcm fw as Baytrail,
138*4882a593Smuzhiyun * so pdata is same as Baytrail, minus the streams_lost_on_suspend quirk.
139*4882a593Smuzhiyun */
140*4882a593Smuzhiyun static struct sst_platform_info chv_platform_data = {
141*4882a593Smuzhiyun .probe_data = &byt_fwparse_info,
142*4882a593Smuzhiyun .ipc_info = &byt_ipc_info,
143*4882a593Smuzhiyun .lib_info = &byt_lib_dnld_info,
144*4882a593Smuzhiyun .res_info = &byt_rvp_res_info,
145*4882a593Smuzhiyun .platform = "sst-mfld-platform",
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun
sst_platform_get_resources(struct intel_sst_drv * ctx)148*4882a593Smuzhiyun static int sst_platform_get_resources(struct intel_sst_drv *ctx)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun struct resource *rsrc;
151*4882a593Smuzhiyun struct platform_device *pdev = to_platform_device(ctx->dev);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /* All ACPI resource request here */
154*4882a593Smuzhiyun /* Get Shim addr */
155*4882a593Smuzhiyun rsrc = platform_get_resource(pdev, IORESOURCE_MEM,
156*4882a593Smuzhiyun ctx->pdata->res_info->acpi_lpe_res_index);
157*4882a593Smuzhiyun if (!rsrc) {
158*4882a593Smuzhiyun dev_err(ctx->dev, "Invalid SHIM base from IFWI\n");
159*4882a593Smuzhiyun return -EIO;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun dev_info(ctx->dev, "LPE base: %#x size:%#x", (unsigned int) rsrc->start,
162*4882a593Smuzhiyun (unsigned int)resource_size(rsrc));
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun ctx->iram_base = rsrc->start + ctx->pdata->res_info->iram_offset;
165*4882a593Smuzhiyun ctx->iram_end = ctx->iram_base + ctx->pdata->res_info->iram_size - 1;
166*4882a593Smuzhiyun dev_info(ctx->dev, "IRAM base: %#x", ctx->iram_base);
167*4882a593Smuzhiyun ctx->iram = devm_ioremap(ctx->dev, ctx->iram_base,
168*4882a593Smuzhiyun ctx->pdata->res_info->iram_size);
169*4882a593Smuzhiyun if (!ctx->iram) {
170*4882a593Smuzhiyun dev_err(ctx->dev, "unable to map IRAM\n");
171*4882a593Smuzhiyun return -EIO;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun ctx->dram_base = rsrc->start + ctx->pdata->res_info->dram_offset;
175*4882a593Smuzhiyun ctx->dram_end = ctx->dram_base + ctx->pdata->res_info->dram_size - 1;
176*4882a593Smuzhiyun dev_info(ctx->dev, "DRAM base: %#x", ctx->dram_base);
177*4882a593Smuzhiyun ctx->dram = devm_ioremap(ctx->dev, ctx->dram_base,
178*4882a593Smuzhiyun ctx->pdata->res_info->dram_size);
179*4882a593Smuzhiyun if (!ctx->dram) {
180*4882a593Smuzhiyun dev_err(ctx->dev, "unable to map DRAM\n");
181*4882a593Smuzhiyun return -EIO;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun ctx->shim_phy_add = rsrc->start + ctx->pdata->res_info->shim_offset;
185*4882a593Smuzhiyun dev_info(ctx->dev, "SHIM base: %#x", ctx->shim_phy_add);
186*4882a593Smuzhiyun ctx->shim = devm_ioremap(ctx->dev, ctx->shim_phy_add,
187*4882a593Smuzhiyun ctx->pdata->res_info->shim_size);
188*4882a593Smuzhiyun if (!ctx->shim) {
189*4882a593Smuzhiyun dev_err(ctx->dev, "unable to map SHIM\n");
190*4882a593Smuzhiyun return -EIO;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun /* reassign physical address to LPE viewpoint address */
194*4882a593Smuzhiyun ctx->shim_phy_add = ctx->pdata->res_info->shim_phy_addr;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun /* Get mailbox addr */
197*4882a593Smuzhiyun ctx->mailbox_add = rsrc->start + ctx->pdata->res_info->mbox_offset;
198*4882a593Smuzhiyun dev_info(ctx->dev, "Mailbox base: %#x", ctx->mailbox_add);
199*4882a593Smuzhiyun ctx->mailbox = devm_ioremap(ctx->dev, ctx->mailbox_add,
200*4882a593Smuzhiyun ctx->pdata->res_info->mbox_size);
201*4882a593Smuzhiyun if (!ctx->mailbox) {
202*4882a593Smuzhiyun dev_err(ctx->dev, "unable to map mailbox\n");
203*4882a593Smuzhiyun return -EIO;
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun /* reassign physical address to LPE viewpoint address */
207*4882a593Smuzhiyun ctx->mailbox_add = ctx->info.mailbox_start;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun rsrc = platform_get_resource(pdev, IORESOURCE_MEM,
210*4882a593Smuzhiyun ctx->pdata->res_info->acpi_ddr_index);
211*4882a593Smuzhiyun if (!rsrc) {
212*4882a593Smuzhiyun dev_err(ctx->dev, "Invalid DDR base from IFWI\n");
213*4882a593Smuzhiyun return -EIO;
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun ctx->ddr_base = rsrc->start;
216*4882a593Smuzhiyun ctx->ddr_end = rsrc->end;
217*4882a593Smuzhiyun dev_info(ctx->dev, "DDR base: %#x", ctx->ddr_base);
218*4882a593Smuzhiyun ctx->ddr = devm_ioremap(ctx->dev, ctx->ddr_base,
219*4882a593Smuzhiyun resource_size(rsrc));
220*4882a593Smuzhiyun if (!ctx->ddr) {
221*4882a593Smuzhiyun dev_err(ctx->dev, "unable to map DDR\n");
222*4882a593Smuzhiyun return -EIO;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun /* Find the IRQ */
226*4882a593Smuzhiyun ctx->irq_num = platform_get_irq(pdev,
227*4882a593Smuzhiyun ctx->pdata->res_info->acpi_ipc_irq_index);
228*4882a593Smuzhiyun if (ctx->irq_num <= 0)
229*4882a593Smuzhiyun return ctx->irq_num < 0 ? ctx->irq_num : -EIO;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun return 0;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
sst_acpi_probe(struct platform_device * pdev)234*4882a593Smuzhiyun static int sst_acpi_probe(struct platform_device *pdev)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun struct device *dev = &pdev->dev;
237*4882a593Smuzhiyun int ret = 0;
238*4882a593Smuzhiyun struct intel_sst_drv *ctx;
239*4882a593Smuzhiyun const struct acpi_device_id *id;
240*4882a593Smuzhiyun struct snd_soc_acpi_mach *mach;
241*4882a593Smuzhiyun struct platform_device *mdev;
242*4882a593Smuzhiyun struct platform_device *plat_dev;
243*4882a593Smuzhiyun struct sst_platform_info *pdata;
244*4882a593Smuzhiyun unsigned int dev_id;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun id = acpi_match_device(dev->driver->acpi_match_table, dev);
247*4882a593Smuzhiyun if (!id)
248*4882a593Smuzhiyun return -ENODEV;
249*4882a593Smuzhiyun dev_dbg(dev, "for %s\n", id->id);
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun mach = (struct snd_soc_acpi_mach *)id->driver_data;
252*4882a593Smuzhiyun mach = snd_soc_acpi_find_machine(mach);
253*4882a593Smuzhiyun if (mach == NULL) {
254*4882a593Smuzhiyun dev_err(dev, "No matching machine driver found\n");
255*4882a593Smuzhiyun return -ENODEV;
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun if (soc_intel_is_byt())
259*4882a593Smuzhiyun mach->pdata = &byt_rvp_platform_data;
260*4882a593Smuzhiyun else
261*4882a593Smuzhiyun mach->pdata = &chv_platform_data;
262*4882a593Smuzhiyun pdata = mach->pdata;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun ret = kstrtouint(id->id, 16, &dev_id);
265*4882a593Smuzhiyun if (ret < 0) {
266*4882a593Smuzhiyun dev_err(dev, "Unique device id conversion error: %d\n", ret);
267*4882a593Smuzhiyun return ret;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun dev_dbg(dev, "ACPI device id: %x\n", dev_id);
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun ret = sst_alloc_drv_context(&ctx, dev, dev_id);
273*4882a593Smuzhiyun if (ret < 0)
274*4882a593Smuzhiyun return ret;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun if (soc_intel_is_byt_cr(pdev)) {
277*4882a593Smuzhiyun /* override resource info */
278*4882a593Smuzhiyun byt_rvp_platform_data.res_info = &bytcr_res_info;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun /* update machine parameters */
282*4882a593Smuzhiyun mach->mach_params.acpi_ipc_irq_index =
283*4882a593Smuzhiyun pdata->res_info->acpi_ipc_irq_index;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun plat_dev = platform_device_register_data(dev, pdata->platform, -1,
286*4882a593Smuzhiyun NULL, 0);
287*4882a593Smuzhiyun if (IS_ERR(plat_dev)) {
288*4882a593Smuzhiyun dev_err(dev, "Failed to create machine device: %s\n",
289*4882a593Smuzhiyun pdata->platform);
290*4882a593Smuzhiyun return PTR_ERR(plat_dev);
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun /*
294*4882a593Smuzhiyun * Create platform device for sst machine driver,
295*4882a593Smuzhiyun * pass machine info as pdata
296*4882a593Smuzhiyun */
297*4882a593Smuzhiyun mdev = platform_device_register_data(dev, mach->drv_name, -1,
298*4882a593Smuzhiyun (const void *)mach, sizeof(*mach));
299*4882a593Smuzhiyun if (IS_ERR(mdev)) {
300*4882a593Smuzhiyun dev_err(dev, "Failed to create machine device: %s\n",
301*4882a593Smuzhiyun mach->drv_name);
302*4882a593Smuzhiyun return PTR_ERR(mdev);
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun /* Fill sst platform data */
306*4882a593Smuzhiyun ctx->pdata = pdata;
307*4882a593Smuzhiyun strcpy(ctx->firmware_name, mach->fw_filename);
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun ret = sst_platform_get_resources(ctx);
310*4882a593Smuzhiyun if (ret)
311*4882a593Smuzhiyun return ret;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun ret = sst_context_init(ctx);
314*4882a593Smuzhiyun if (ret < 0)
315*4882a593Smuzhiyun return ret;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun sst_configure_runtime_pm(ctx);
318*4882a593Smuzhiyun platform_set_drvdata(pdev, ctx);
319*4882a593Smuzhiyun return ret;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun /**
323*4882a593Smuzhiyun * intel_sst_remove - remove function
324*4882a593Smuzhiyun *
325*4882a593Smuzhiyun * @pdev: platform device structure
326*4882a593Smuzhiyun *
327*4882a593Smuzhiyun * This function is called by OS when a device is unloaded
328*4882a593Smuzhiyun * This frees the interrupt etc
329*4882a593Smuzhiyun */
sst_acpi_remove(struct platform_device * pdev)330*4882a593Smuzhiyun static int sst_acpi_remove(struct platform_device *pdev)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun struct intel_sst_drv *ctx;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun ctx = platform_get_drvdata(pdev);
335*4882a593Smuzhiyun sst_context_cleanup(ctx);
336*4882a593Smuzhiyun platform_set_drvdata(pdev, NULL);
337*4882a593Smuzhiyun return 0;
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun static const struct acpi_device_id sst_acpi_ids[] = {
341*4882a593Smuzhiyun { "80860F28", (unsigned long)&snd_soc_acpi_intel_baytrail_machines},
342*4882a593Smuzhiyun { "808622A8", (unsigned long)&snd_soc_acpi_intel_cherrytrail_machines},
343*4882a593Smuzhiyun { },
344*4882a593Smuzhiyun };
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, sst_acpi_ids);
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun static struct platform_driver sst_acpi_driver = {
349*4882a593Smuzhiyun .driver = {
350*4882a593Smuzhiyun .name = "intel_sst_acpi",
351*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(sst_acpi_ids),
352*4882a593Smuzhiyun .pm = &intel_sst_pm,
353*4882a593Smuzhiyun },
354*4882a593Smuzhiyun .probe = sst_acpi_probe,
355*4882a593Smuzhiyun .remove = sst_acpi_remove,
356*4882a593Smuzhiyun };
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun module_platform_driver(sst_acpi_driver);
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun MODULE_DESCRIPTION("Intel (R) SST(R) Audio Engine ACPI Driver");
361*4882a593Smuzhiyun MODULE_AUTHOR("Ramesh Babu K V");
362*4882a593Smuzhiyun MODULE_AUTHOR("Omair Mohammed Abdullah");
363*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
364*4882a593Smuzhiyun MODULE_ALIAS("sst");
365