1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 4*4882a593Smuzhiyun * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This contains hardware definitions that are common between i.MX21 and 7*4882a593Smuzhiyun * i.MX27. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __MACH_MX2x_H__ 11*4882a593Smuzhiyun #define __MACH_MX2x_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* The following addresses are common between i.MX21 and i.MX27 */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Register offsets */ 16*4882a593Smuzhiyun #define MX2x_AIPI_BASE_ADDR 0x10000000 17*4882a593Smuzhiyun #define MX2x_AIPI_SIZE SZ_1M 18*4882a593Smuzhiyun #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) 19*4882a593Smuzhiyun #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) 20*4882a593Smuzhiyun #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000) 21*4882a593Smuzhiyun #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000) 22*4882a593Smuzhiyun #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000) 23*4882a593Smuzhiyun #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000) 24*4882a593Smuzhiyun #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000) 25*4882a593Smuzhiyun #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000) 26*4882a593Smuzhiyun #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000) 27*4882a593Smuzhiyun #define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000) 28*4882a593Smuzhiyun #define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000) 29*4882a593Smuzhiyun #define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000) 30*4882a593Smuzhiyun #define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000) 31*4882a593Smuzhiyun #define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000) 32*4882a593Smuzhiyun #define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000) 33*4882a593Smuzhiyun #define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000) 34*4882a593Smuzhiyun #define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000) 35*4882a593Smuzhiyun #define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000) 36*4882a593Smuzhiyun #define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000) 37*4882a593Smuzhiyun #define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000) 38*4882a593Smuzhiyun #define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000) 39*4882a593Smuzhiyun #define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000) 40*4882a593Smuzhiyun #define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000) 41*4882a593Smuzhiyun #define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000) 42*4882a593Smuzhiyun #define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000) 43*4882a593Smuzhiyun #define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000) 44*4882a593Smuzhiyun #define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000) 45*4882a593Smuzhiyun #define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400) 46*4882a593Smuzhiyun #define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000) 47*4882a593Smuzhiyun #define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800) 48*4882a593Smuzhiyun #define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000) 49*4882a593Smuzhiyun #define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define MX2x_AVIC_BASE_ADDR 0x10040000 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define MX2x_SAHB1_BASE_ADDR 0x80000000 54*4882a593Smuzhiyun #define MX2x_SAHB1_SIZE SZ_1M 55*4882a593Smuzhiyun #define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* fixed interrupt numbers */ 58*4882a593Smuzhiyun #include <asm/irq.h> 59*4882a593Smuzhiyun #define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6) 60*4882a593Smuzhiyun #define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8) 61*4882a593Smuzhiyun #define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10) 62*4882a593Smuzhiyun #define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11) 63*4882a593Smuzhiyun #define MX2x_INT_I2C (NR_IRQS_LEGACY + 12) 64*4882a593Smuzhiyun #define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13) 65*4882a593Smuzhiyun #define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14) 66*4882a593Smuzhiyun #define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15) 67*4882a593Smuzhiyun #define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16) 68*4882a593Smuzhiyun #define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17) 69*4882a593Smuzhiyun #define MX2x_INT_UART3 (NR_IRQS_LEGACY + 18) 70*4882a593Smuzhiyun #define MX2x_INT_UART2 (NR_IRQS_LEGACY + 19) 71*4882a593Smuzhiyun #define MX2x_INT_UART1 (NR_IRQS_LEGACY + 20) 72*4882a593Smuzhiyun #define MX2x_INT_KPP (NR_IRQS_LEGACY + 21) 73*4882a593Smuzhiyun #define MX2x_INT_RTC (NR_IRQS_LEGACY + 22) 74*4882a593Smuzhiyun #define MX2x_INT_PWM (NR_IRQS_LEGACY + 23) 75*4882a593Smuzhiyun #define MX2x_INT_GPT3 (NR_IRQS_LEGACY + 24) 76*4882a593Smuzhiyun #define MX2x_INT_GPT2 (NR_IRQS_LEGACY + 25) 77*4882a593Smuzhiyun #define MX2x_INT_GPT1 (NR_IRQS_LEGACY + 26) 78*4882a593Smuzhiyun #define MX2x_INT_WDOG (NR_IRQS_LEGACY + 27) 79*4882a593Smuzhiyun #define MX2x_INT_PCMCIA (NR_IRQS_LEGACY + 28) 80*4882a593Smuzhiyun #define MX2x_INT_NANDFC (NR_IRQS_LEGACY + 29) 81*4882a593Smuzhiyun #define MX2x_INT_CSI (NR_IRQS_LEGACY + 31) 82*4882a593Smuzhiyun #define MX2x_INT_DMACH0 (NR_IRQS_LEGACY + 32) 83*4882a593Smuzhiyun #define MX2x_INT_DMACH1 (NR_IRQS_LEGACY + 33) 84*4882a593Smuzhiyun #define MX2x_INT_DMACH2 (NR_IRQS_LEGACY + 34) 85*4882a593Smuzhiyun #define MX2x_INT_DMACH3 (NR_IRQS_LEGACY + 35) 86*4882a593Smuzhiyun #define MX2x_INT_DMACH4 (NR_IRQS_LEGACY + 36) 87*4882a593Smuzhiyun #define MX2x_INT_DMACH5 (NR_IRQS_LEGACY + 37) 88*4882a593Smuzhiyun #define MX2x_INT_DMACH6 (NR_IRQS_LEGACY + 38) 89*4882a593Smuzhiyun #define MX2x_INT_DMACH7 (NR_IRQS_LEGACY + 39) 90*4882a593Smuzhiyun #define MX2x_INT_DMACH8 (NR_IRQS_LEGACY + 40) 91*4882a593Smuzhiyun #define MX2x_INT_DMACH9 (NR_IRQS_LEGACY + 41) 92*4882a593Smuzhiyun #define MX2x_INT_DMACH10 (NR_IRQS_LEGACY + 42) 93*4882a593Smuzhiyun #define MX2x_INT_DMACH11 (NR_IRQS_LEGACY + 43) 94*4882a593Smuzhiyun #define MX2x_INT_DMACH12 (NR_IRQS_LEGACY + 44) 95*4882a593Smuzhiyun #define MX2x_INT_DMACH13 (NR_IRQS_LEGACY + 45) 96*4882a593Smuzhiyun #define MX2x_INT_DMACH14 (NR_IRQS_LEGACY + 46) 97*4882a593Smuzhiyun #define MX2x_INT_DMACH15 (NR_IRQS_LEGACY + 47) 98*4882a593Smuzhiyun #define MX2x_INT_EMMAPRP (NR_IRQS_LEGACY + 51) 99*4882a593Smuzhiyun #define MX2x_INT_EMMAPP (NR_IRQS_LEGACY + 52) 100*4882a593Smuzhiyun #define MX2x_INT_SLCDC (NR_IRQS_LEGACY + 60) 101*4882a593Smuzhiyun #define MX2x_INT_LCDC (NR_IRQS_LEGACY + 61) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* fixed DMA request numbers */ 104*4882a593Smuzhiyun #define MX2x_DMA_REQ_CSPI3_RX 1 105*4882a593Smuzhiyun #define MX2x_DMA_REQ_CSPI3_TX 2 106*4882a593Smuzhiyun #define MX2x_DMA_REQ_EXT 3 107*4882a593Smuzhiyun #define MX2x_DMA_REQ_SDHC2 6 108*4882a593Smuzhiyun #define MX2x_DMA_REQ_SDHC1 7 109*4882a593Smuzhiyun #define MX2x_DMA_REQ_SSI2_RX0 8 110*4882a593Smuzhiyun #define MX2x_DMA_REQ_SSI2_TX0 9 111*4882a593Smuzhiyun #define MX2x_DMA_REQ_SSI2_RX1 10 112*4882a593Smuzhiyun #define MX2x_DMA_REQ_SSI2_TX1 11 113*4882a593Smuzhiyun #define MX2x_DMA_REQ_SSI1_RX0 12 114*4882a593Smuzhiyun #define MX2x_DMA_REQ_SSI1_TX0 13 115*4882a593Smuzhiyun #define MX2x_DMA_REQ_SSI1_RX1 14 116*4882a593Smuzhiyun #define MX2x_DMA_REQ_SSI1_TX1 15 117*4882a593Smuzhiyun #define MX2x_DMA_REQ_CSPI2_RX 16 118*4882a593Smuzhiyun #define MX2x_DMA_REQ_CSPI2_TX 17 119*4882a593Smuzhiyun #define MX2x_DMA_REQ_CSPI1_RX 18 120*4882a593Smuzhiyun #define MX2x_DMA_REQ_CSPI1_TX 19 121*4882a593Smuzhiyun #define MX2x_DMA_REQ_UART4_RX 20 122*4882a593Smuzhiyun #define MX2x_DMA_REQ_UART4_TX 21 123*4882a593Smuzhiyun #define MX2x_DMA_REQ_UART3_RX 22 124*4882a593Smuzhiyun #define MX2x_DMA_REQ_UART3_TX 23 125*4882a593Smuzhiyun #define MX2x_DMA_REQ_UART2_RX 24 126*4882a593Smuzhiyun #define MX2x_DMA_REQ_UART2_TX 25 127*4882a593Smuzhiyun #define MX2x_DMA_REQ_UART1_RX 26 128*4882a593Smuzhiyun #define MX2x_DMA_REQ_UART1_TX 27 129*4882a593Smuzhiyun #define MX2x_DMA_REQ_CSI_STAT 30 130*4882a593Smuzhiyun #define MX2x_DMA_REQ_CSI_RX 31 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #endif /* ifndef __MACH_MX2x_H__ */ 133