1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010 3*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Authors: 6*4882a593Smuzhiyun * Aneesh V <aneesh@ti.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Derived from OMAP3 work by 9*4882a593Smuzhiyun * Richard Woodruff <r-woodruff2@ti.com> 10*4882a593Smuzhiyun * Syed Mohammed Khasim <x0khasim@ti.com> 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef _OMAP4_H_ 16*4882a593Smuzhiyun #define _OMAP4_H_ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 19*4882a593Smuzhiyun #include <asm/types.h> 20*4882a593Smuzhiyun #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #include <linux/sizes.h> 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * L4 Peripherals - L4 Wakeup and L4 Core now 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun #define OMAP44XX_L4_CORE_BASE 0x4A000000 28*4882a593Smuzhiyun #define OMAP44XX_L4_WKUP_BASE 0x4A300000 29*4882a593Smuzhiyun #define OMAP44XX_L4_PER_BASE 0x48000000 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 32*4882a593Smuzhiyun #define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 33*4882a593Smuzhiyun #define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START 34*4882a593Smuzhiyun #define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* CONTROL_ID_CODE */ 37*4882a593Smuzhiyun #define CONTROL_ID_CODE 0x4A002204 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F 40*4882a593Smuzhiyun #define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F 41*4882a593Smuzhiyun #define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F 42*4882a593Smuzhiyun #define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F 43*4882a593Smuzhiyun #define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F 44*4882a593Smuzhiyun #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F 45*4882a593Smuzhiyun #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F 46*4882a593Smuzhiyun #define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* UART */ 49*4882a593Smuzhiyun #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) 50*4882a593Smuzhiyun #define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) 51*4882a593Smuzhiyun #define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* General Purpose Timers */ 54*4882a593Smuzhiyun #define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000) 55*4882a593Smuzhiyun #define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000) 56*4882a593Smuzhiyun #define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Watchdog Timer2 - MPU watchdog */ 59*4882a593Smuzhiyun #define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * Hardware Register Details 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Watchdog Timer */ 66*4882a593Smuzhiyun #define WD_UNLOCK1 0xAAAA 67*4882a593Smuzhiyun #define WD_UNLOCK2 0x5555 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* GP Timer */ 70*4882a593Smuzhiyun #define TCLR_ST (0x1 << 0) 71*4882a593Smuzhiyun #define TCLR_AR (0x1 << 1) 72*4882a593Smuzhiyun #define TCLR_PRE (0x1 << 5) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* Control Module */ 75*4882a593Smuzhiyun #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) 76*4882a593Smuzhiyun #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f 77*4882a593Smuzhiyun #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 78*4882a593Smuzhiyun #define CONTROL_EFUSE_2_OVERRIDE 0x99084000 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* LPDDR2 IO regs */ 81*4882a593Smuzhiyun #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C 82*4882a593Smuzhiyun #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E 83*4882a593Smuzhiyun #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C 84*4882a593Smuzhiyun #define LPDDR2IO_GR10_WD_MASK (3 << 17) 85*4882a593Smuzhiyun #define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* CONTROL_EFUSE_2 */ 88*4882a593Smuzhiyun #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define MMC1_PWRDNZ (1 << 26) 91*4882a593Smuzhiyun #define MMC1_PBIASLITE_PWRDNZ (1 << 22) 92*4882a593Smuzhiyun #define MMC1_PBIASLITE_VMODE (1 << 21) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun struct s32ktimer { 97*4882a593Smuzhiyun unsigned char res[0x10]; 98*4882a593Smuzhiyun unsigned int s32k_cr; /* 0x10 */ 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define DEVICE_TYPE_SHIFT (0x8) 102*4882a593Smuzhiyun #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* 107*4882a593Smuzhiyun * Non-secure SRAM Addresses 108*4882a593Smuzhiyun * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE 109*4882a593Smuzhiyun * at 0x40304000(EMU base) so that our code works for both EMU and GP 110*4882a593Smuzhiyun */ 111*4882a593Smuzhiyun #define NON_SECURE_SRAM_START 0x40304000 112*4882a593Smuzhiyun #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ 113*4882a593Smuzhiyun #define NON_SECURE_SRAM_IMG_END 0x4030C000 114*4882a593Smuzhiyun #define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) 115*4882a593Smuzhiyun /* base address for indirect vectors (internal boot mode) */ 116*4882a593Smuzhiyun #define SRAM_ROM_VECT_BASE 0x4030D000 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* ABB settings */ 119*4882a593Smuzhiyun #define OMAP_ABB_SETTLING_TIME 50 120*4882a593Smuzhiyun #define OMAP_ABB_CLOCK_CYCLES 16 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* ABB tranxdone mask */ 123*4882a593Smuzhiyun #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define OMAP44XX_SAR_RAM_BASE 0x4a326000 126*4882a593Smuzhiyun #define OMAP_REBOOT_REASON_OFFSET 0xA0C 127*4882a593Smuzhiyun #define OMAP_REBOOT_REASON_SIZE 0x0F 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* Boot parameters */ 130*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 131*4882a593Smuzhiyun struct omap_boot_parameters { 132*4882a593Smuzhiyun unsigned int boot_message; 133*4882a593Smuzhiyun unsigned int boot_device_descriptor; 134*4882a593Smuzhiyun unsigned char boot_device; 135*4882a593Smuzhiyun unsigned char reset_reason; 136*4882a593Smuzhiyun unsigned char ch_flags; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun int omap_reboot_mode(char *mode, unsigned int length); 140*4882a593Smuzhiyun int omap_reboot_mode_clear(void); 141*4882a593Smuzhiyun int omap_reboot_mode_store(char *mode); 142*4882a593Smuzhiyun #endif 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #endif 145