1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __MACH_MX3x_H__ 8*4882a593Smuzhiyun #define __MACH_MX3x_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * MX31 memory map: 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * Virt Phys Size What 14*4882a593Smuzhiyun * --------------------------------------------------------------------------- 15*4882a593Smuzhiyun * FC000000 43F00000 1M AIPS 1 16*4882a593Smuzhiyun * FC100000 50000000 1M SPBA 17*4882a593Smuzhiyun * FC200000 53F00000 1M AIPS 2 18*4882a593Smuzhiyun * FC500000 60000000 128M ROMPATCH 19*4882a593Smuzhiyun * FC400000 68000000 128M AVIC 20*4882a593Smuzhiyun * 70000000 256M IPU (MAX M2) 21*4882a593Smuzhiyun * 80000000 256M CSD0 SDRAM/DDR 22*4882a593Smuzhiyun * 90000000 256M CSD1 SDRAM/DDR 23*4882a593Smuzhiyun * A0000000 128M CS0 Flash 24*4882a593Smuzhiyun * A8000000 128M CS1 Flash 25*4882a593Smuzhiyun * B0000000 32M CS2 26*4882a593Smuzhiyun * B2000000 32M CS3 27*4882a593Smuzhiyun * F4000000 B4000000 32M CS4 28*4882a593Smuzhiyun * B6000000 32M CS5 29*4882a593Smuzhiyun * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers 30*4882a593Smuzhiyun * C0000000 64M PCMCIA/CF 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * L2CC 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #define MX3x_L2CC_BASE_ADDR 0x30000000 37*4882a593Smuzhiyun #define MX3x_L2CC_SIZE SZ_1M 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * AIPS 1 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun #define MX3x_AIPS1_BASE_ADDR 0x43f00000 43*4882a593Smuzhiyun #define MX3x_AIPS1_SIZE SZ_1M 44*4882a593Smuzhiyun #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) 45*4882a593Smuzhiyun #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) 46*4882a593Smuzhiyun #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000) 47*4882a593Smuzhiyun #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000) 48*4882a593Smuzhiyun #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000) 49*4882a593Smuzhiyun #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000) 50*4882a593Smuzhiyun #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000) 51*4882a593Smuzhiyun #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000) 52*4882a593Smuzhiyun #define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000) 53*4882a593Smuzhiyun #define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000) 54*4882a593Smuzhiyun #define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000) 55*4882a593Smuzhiyun #define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000) 56*4882a593Smuzhiyun #define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000) 57*4882a593Smuzhiyun #define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000) 58*4882a593Smuzhiyun #define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000) 59*4882a593Smuzhiyun #define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000) 60*4882a593Smuzhiyun #define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000) 61*4882a593Smuzhiyun #define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* 64*4882a593Smuzhiyun * SPBA global module enabled #0 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun #define MX3x_SPBA0_BASE_ADDR 0x50000000 67*4882a593Smuzhiyun #define MX3x_SPBA0_SIZE SZ_1M 68*4882a593Smuzhiyun #define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) 69*4882a593Smuzhiyun #define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) 70*4882a593Smuzhiyun #define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000) 71*4882a593Smuzhiyun #define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000) 72*4882a593Smuzhiyun #define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000) 73*4882a593Smuzhiyun #define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* 76*4882a593Smuzhiyun * AIPS 2 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun #define MX3x_AIPS2_BASE_ADDR 0x53f00000 79*4882a593Smuzhiyun #define MX3x_AIPS2_SIZE SZ_1M 80*4882a593Smuzhiyun #define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) 81*4882a593Smuzhiyun #define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) 82*4882a593Smuzhiyun #define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000) 83*4882a593Smuzhiyun #define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000) 84*4882a593Smuzhiyun #define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000) 85*4882a593Smuzhiyun #define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000) 86*4882a593Smuzhiyun #define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000) 87*4882a593Smuzhiyun #define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000) 88*4882a593Smuzhiyun #define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000) 89*4882a593Smuzhiyun #define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000) 90*4882a593Smuzhiyun #define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000) 91*4882a593Smuzhiyun #define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000) 92*4882a593Smuzhiyun #define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000) 93*4882a593Smuzhiyun #define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000) 94*4882a593Smuzhiyun #define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000) 95*4882a593Smuzhiyun #define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* 98*4882a593Smuzhiyun * ROMP and AVIC 99*4882a593Smuzhiyun */ 100*4882a593Smuzhiyun #define MX3x_ROMP_BASE_ADDR 0x60000000 101*4882a593Smuzhiyun #define MX3x_ROMP_SIZE SZ_1M 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define MX3x_AVIC_BASE_ADDR 0x68000000 104*4882a593Smuzhiyun #define MX3x_AVIC_SIZE SZ_1M 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* 107*4882a593Smuzhiyun * Memory regions and CS 108*4882a593Smuzhiyun */ 109*4882a593Smuzhiyun #define MX3x_IPU_MEM_BASE_ADDR 0x70000000 110*4882a593Smuzhiyun #define MX3x_CSD0_BASE_ADDR 0x80000000 111*4882a593Smuzhiyun #define MX3x_CSD1_BASE_ADDR 0x90000000 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define MX3x_CS0_BASE_ADDR 0xa0000000 114*4882a593Smuzhiyun #define MX3x_CS1_BASE_ADDR 0xa8000000 115*4882a593Smuzhiyun #define MX3x_CS2_BASE_ADDR 0xb0000000 116*4882a593Smuzhiyun #define MX3x_CS3_BASE_ADDR 0xb2000000 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define MX3x_CS4_BASE_ADDR 0xb4000000 119*4882a593Smuzhiyun #define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000 120*4882a593Smuzhiyun #define MX3x_CS4_SIZE SZ_32M 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define MX3x_CS5_BASE_ADDR 0xb6000000 123*4882a593Smuzhiyun #define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000 124*4882a593Smuzhiyun #define MX3x_CS5_SIZE SZ_32M 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* 127*4882a593Smuzhiyun * NAND, SDRAM, WEIM, M3IF, EMI controllers 128*4882a593Smuzhiyun */ 129*4882a593Smuzhiyun #define MX3x_X_MEMC_BASE_ADDR 0xb8000000 130*4882a593Smuzhiyun #define MX3x_X_MEMC_SIZE SZ_64K 131*4882a593Smuzhiyun #define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) 132*4882a593Smuzhiyun #define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) 133*4882a593Smuzhiyun #define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000) 134*4882a593Smuzhiyun #define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000) 135*4882a593Smuzhiyun #define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* 140*4882a593Smuzhiyun * Interrupt numbers 141*4882a593Smuzhiyun */ 142*4882a593Smuzhiyun #include <asm/irq.h> 143*4882a593Smuzhiyun #define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3) 144*4882a593Smuzhiyun #define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4) 145*4882a593Smuzhiyun #define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6) 146*4882a593Smuzhiyun #define MX3x_INT_I2C (NR_IRQS_LEGACY + 10) 147*4882a593Smuzhiyun #define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13) 148*4882a593Smuzhiyun #define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14) 149*4882a593Smuzhiyun #define MX3x_INT_ATA (NR_IRQS_LEGACY + 15) 150*4882a593Smuzhiyun #define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18) 151*4882a593Smuzhiyun #define MX3x_INT_IIM (NR_IRQS_LEGACY + 19) 152*4882a593Smuzhiyun #define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22) 153*4882a593Smuzhiyun #define MX3x_INT_EVTMON (NR_IRQS_LEGACY + 23) 154*4882a593Smuzhiyun #define MX3x_INT_KPP (NR_IRQS_LEGACY + 24) 155*4882a593Smuzhiyun #define MX3x_INT_RTC (NR_IRQS_LEGACY + 25) 156*4882a593Smuzhiyun #define MX3x_INT_PWM (NR_IRQS_LEGACY + 26) 157*4882a593Smuzhiyun #define MX3x_INT_EPIT2 (NR_IRQS_LEGACY + 27) 158*4882a593Smuzhiyun #define MX3x_INT_EPIT1 (NR_IRQS_LEGACY + 28) 159*4882a593Smuzhiyun #define MX3x_INT_GPT (NR_IRQS_LEGACY + 29) 160*4882a593Smuzhiyun #define MX3x_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) 161*4882a593Smuzhiyun #define MX3x_INT_UART2 (NR_IRQS_LEGACY + 32) 162*4882a593Smuzhiyun #define MX3x_INT_NANDFC (NR_IRQS_LEGACY + 33) 163*4882a593Smuzhiyun #define MX3x_INT_SDMA (NR_IRQS_LEGACY + 34) 164*4882a593Smuzhiyun #define MX3x_INT_MSHC1 (NR_IRQS_LEGACY + 39) 165*4882a593Smuzhiyun #define MX3x_INT_IPU_ERR (NR_IRQS_LEGACY + 41) 166*4882a593Smuzhiyun #define MX3x_INT_IPU_SYN (NR_IRQS_LEGACY + 42) 167*4882a593Smuzhiyun #define MX3x_INT_UART1 (NR_IRQS_LEGACY + 45) 168*4882a593Smuzhiyun #define MX3x_INT_ECT (NR_IRQS_LEGACY + 48) 169*4882a593Smuzhiyun #define MX3x_INT_SCC_SCM (NR_IRQS_LEGACY + 49) 170*4882a593Smuzhiyun #define MX3x_INT_SCC_SMN (NR_IRQS_LEGACY + 50) 171*4882a593Smuzhiyun #define MX3x_INT_GPIO2 (NR_IRQS_LEGACY + 51) 172*4882a593Smuzhiyun #define MX3x_INT_GPIO1 (NR_IRQS_LEGACY + 52) 173*4882a593Smuzhiyun #define MX3x_INT_WDOG (NR_IRQS_LEGACY + 55) 174*4882a593Smuzhiyun #define MX3x_INT_GPIO3 (NR_IRQS_LEGACY + 56) 175*4882a593Smuzhiyun #define MX3x_INT_EXT_POWER (NR_IRQS_LEGACY + 58) 176*4882a593Smuzhiyun #define MX3x_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) 177*4882a593Smuzhiyun #define MX3x_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) 178*4882a593Smuzhiyun #define MX3x_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) 179*4882a593Smuzhiyun #define MX3x_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) 180*4882a593Smuzhiyun #define MX3x_INT_EXT_TV (NR_IRQS_LEGACY + 63) 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun #define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #endif /* ifndef __MACH_MX3x_H__ */ 185