1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: TI J721e UFS Host Controller Glue Driver 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Vignesh Raghavendra <vigneshr@ti.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun compatible: 14*4882a593Smuzhiyun items: 15*4882a593Smuzhiyun - const: ti,j721e-ufs 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun reg: 18*4882a593Smuzhiyun maxItems: 1 19*4882a593Smuzhiyun description: address of TI UFS glue registers 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun clocks: 22*4882a593Smuzhiyun maxItems: 1 23*4882a593Smuzhiyun description: phandle to the M-PHY clock 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun power-domains: 26*4882a593Smuzhiyun maxItems: 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun assigned-clocks: 29*4882a593Smuzhiyun maxItems: 1 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun assigned-clock-parents: 32*4882a593Smuzhiyun maxItems: 1 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun "#address-cells": 35*4882a593Smuzhiyun const: 2 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun "#size-cells": 38*4882a593Smuzhiyun const: 2 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun ranges: true 41*4882a593Smuzhiyun 42*4882a593Smuzhiyunrequired: 43*4882a593Smuzhiyun - compatible 44*4882a593Smuzhiyun - reg 45*4882a593Smuzhiyun - clocks 46*4882a593Smuzhiyun - power-domains 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunpatternProperties: 49*4882a593Smuzhiyun "^ufs@[0-9a-f]+$": 50*4882a593Smuzhiyun type: object 51*4882a593Smuzhiyun description: | 52*4882a593Smuzhiyun Cadence UFS controller node must be the child node. Refer 53*4882a593Smuzhiyun Documentation/devicetree/bindings/ufs/cdns,ufshc.txt for binding 54*4882a593Smuzhiyun documentation of child node 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunadditionalProperties: false 57*4882a593Smuzhiyun 58*4882a593Smuzhiyunexamples: 59*4882a593Smuzhiyun - | 60*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/irq.h> 61*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun bus { 64*4882a593Smuzhiyun #address-cells = <2>; 65*4882a593Smuzhiyun #size-cells = <2>; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun ufs-wrapper@4e80000 { 68*4882a593Smuzhiyun compatible = "ti,j721e-ufs"; 69*4882a593Smuzhiyun reg = <0x0 0x4e80000 0x0 0x100>; 70*4882a593Smuzhiyun power-domains = <&k3_pds 277>; 71*4882a593Smuzhiyun clocks = <&k3_clks 277 1>; 72*4882a593Smuzhiyun assigned-clocks = <&k3_clks 277 1>; 73*4882a593Smuzhiyun assigned-clock-parents = <&k3_clks 277 4>; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun ranges = <0x0 0x0 0x0 0x4e80000 0x0 0x14000>; 76*4882a593Smuzhiyun #address-cells = <2>; 77*4882a593Smuzhiyun #size-cells = <2>; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun ufs@4000 { 80*4882a593Smuzhiyun compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 81*4882a593Smuzhiyun reg = <0x0 0x4000 0x0 0x10000>; 82*4882a593Smuzhiyun interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 83*4882a593Smuzhiyun freq-table-hz = <19200000 19200000>; 84*4882a593Smuzhiyun power-domains = <&k3_pds 277>; 85*4882a593Smuzhiyun clocks = <&k3_clks 277 1>; 86*4882a593Smuzhiyun assigned-clocks = <&k3_clks 277 1>; 87*4882a593Smuzhiyun assigned-clock-parents = <&k3_clks 277 4>; 88*4882a593Smuzhiyun clock-names = "core_clk"; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun }; 92