1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Timers Module 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __ASM_MACH_REGS_TIMERS_H 7*4882a593Smuzhiyun #define __ASM_MACH_REGS_TIMERS_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "addr-map.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define TIMERS1_VIRT_BASE (APB_VIRT_BASE + 0x14000) 12*4882a593Smuzhiyun #define TIMERS2_VIRT_BASE (APB_VIRT_BASE + 0x16000) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define TMR_CCR (0x0000) 15*4882a593Smuzhiyun #define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2)) 16*4882a593Smuzhiyun #define TMR_CR(n) (0x0028 + ((n) << 2)) 17*4882a593Smuzhiyun #define TMR_SR(n) (0x0034 + ((n) << 2)) 18*4882a593Smuzhiyun #define TMR_IER(n) (0x0040 + ((n) << 2)) 19*4882a593Smuzhiyun #define TMR_PLVR(n) (0x004c + ((n) << 2)) 20*4882a593Smuzhiyun #define TMR_PLCR(n) (0x0058 + ((n) << 2)) 21*4882a593Smuzhiyun #define TMR_WMER (0x0064) 22*4882a593Smuzhiyun #define TMR_WMR (0x0068) 23*4882a593Smuzhiyun #define TMR_WVR (0x006c) 24*4882a593Smuzhiyun #define TMR_WSR (0x0070) 25*4882a593Smuzhiyun #define TMR_ICR(n) (0x0074 + ((n) << 2)) 26*4882a593Smuzhiyun #define TMR_WICR (0x0080) 27*4882a593Smuzhiyun #define TMR_CER (0x0084) 28*4882a593Smuzhiyun #define TMR_CMR (0x0088) 29*4882a593Smuzhiyun #define TMR_ILR(n) (0x008c + ((n) << 2)) 30*4882a593Smuzhiyun #define TMR_WCR (0x0098) 31*4882a593Smuzhiyun #define TMR_WFAR (0x009c) 32*4882a593Smuzhiyun #define TMR_WSAR (0x00A0) 33*4882a593Smuzhiyun #define TMR_CVWR(n) (0x00A4 + ((n) << 2)) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define TMR_CCR_CS_0(x) (((x) & 0x3) << 0) 36*4882a593Smuzhiyun #define TMR_CCR_CS_1(x) (((x) & 0x7) << 2) 37*4882a593Smuzhiyun #define TMR_CCR_CS_2(x) (((x) & 0x3) << 5) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #endif /* __ASM_MACH_REGS_TIMERS_H */ 40