1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2006-2010 3*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Aneesh V <aneesh@ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _CPU_H 11*4882a593Smuzhiyun #define _CPU_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 14*4882a593Smuzhiyun #include <asm/types.h> 15*4882a593Smuzhiyun #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <asm/arch/hardware.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifndef __KERNEL_STRICT_NAMES 20*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 21*4882a593Smuzhiyun #include <asm/ti-common/omap_wdt.h> 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct gptimer { 24*4882a593Smuzhiyun u32 tidr; /* 0x00 r */ 25*4882a593Smuzhiyun u8 res1[0xc]; 26*4882a593Smuzhiyun u32 tiocp_cfg; /* 0x10 rw */ 27*4882a593Smuzhiyun u8 res2[0x10]; 28*4882a593Smuzhiyun u32 tisr_raw; /* 0x24 r */ 29*4882a593Smuzhiyun u32 tisr; /* 0x28 rw */ 30*4882a593Smuzhiyun u32 tier; /* 0x2c rw */ 31*4882a593Smuzhiyun u32 ticr; /* 0x30 rw */ 32*4882a593Smuzhiyun u32 twer; /* 0x34 rw */ 33*4882a593Smuzhiyun u32 tclr; /* 0x38 rw */ 34*4882a593Smuzhiyun u32 tcrr; /* 0x3c rw */ 35*4882a593Smuzhiyun u32 tldr; /* 0x40 rw */ 36*4882a593Smuzhiyun u32 ttgr; /* 0x44 rw */ 37*4882a593Smuzhiyun u32 twpc; /* 0x48 r */ 38*4882a593Smuzhiyun u32 tmar; /* 0x4c rw */ 39*4882a593Smuzhiyun u32 tcar1; /* 0x50 r */ 40*4882a593Smuzhiyun u32 tcicr; /* 0x54 rw */ 41*4882a593Smuzhiyun u32 tcar2; /* 0x58 r */ 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 44*4882a593Smuzhiyun #endif /* __KERNEL_STRICT_NAMES */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* enable sys_clk NO-prescale /1 */ 47*4882a593Smuzhiyun #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define WDT_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) 50*4882a593Smuzhiyun /* Watchdog */ 51*4882a593Smuzhiyun #ifndef __KERNEL_STRICT_NAMES 52*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 53*4882a593Smuzhiyun struct watchdog { 54*4882a593Smuzhiyun u8 res1[0x34]; 55*4882a593Smuzhiyun u32 wwps; /* 0x34 r */ 56*4882a593Smuzhiyun u8 res2[0x10]; 57*4882a593Smuzhiyun u32 wspr; /* 0x48 rw */ 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 60*4882a593Smuzhiyun #endif /* __KERNEL_STRICT_NAMES */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define WD_UNLOCK1 0xAAAA 63*4882a593Smuzhiyun #define WD_UNLOCK2 0x5555 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define TCLR_ST (0x1 << 0) 66*4882a593Smuzhiyun #define TCLR_AR (0x1 << 1) 67*4882a593Smuzhiyun #define TCLR_PRE (0x1 << 5) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* I2C base */ 70*4882a593Smuzhiyun #define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000) 71*4882a593Smuzhiyun #define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000) 72*4882a593Smuzhiyun #define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000) 73*4882a593Smuzhiyun #define I2C_BASE4 (OMAP54XX_L4_PER_BASE + 0x7A000) 74*4882a593Smuzhiyun #define I2C_BASE5 (OMAP54XX_L4_PER_BASE + 0x7C000) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* MUSB base */ 77*4882a593Smuzhiyun #define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* OMAP4 GPIO registers */ 80*4882a593Smuzhiyun #define OMAP_GPIO_REVISION 0x0000 81*4882a593Smuzhiyun #define OMAP_GPIO_SYSCONFIG 0x0010 82*4882a593Smuzhiyun #define OMAP_GPIO_SYSSTATUS 0x0114 83*4882a593Smuzhiyun #define OMAP_GPIO_IRQSTATUS1 0x0118 84*4882a593Smuzhiyun #define OMAP_GPIO_IRQSTATUS2 0x0128 85*4882a593Smuzhiyun #define OMAP_GPIO_IRQENABLE2 0x012c 86*4882a593Smuzhiyun #define OMAP_GPIO_IRQENABLE1 0x011c 87*4882a593Smuzhiyun #define OMAP_GPIO_WAKE_EN 0x0120 88*4882a593Smuzhiyun #define OMAP_GPIO_CTRL 0x0130 89*4882a593Smuzhiyun #define OMAP_GPIO_OE 0x0134 90*4882a593Smuzhiyun #define OMAP_GPIO_DATAIN 0x0138 91*4882a593Smuzhiyun #define OMAP_GPIO_DATAOUT 0x013c 92*4882a593Smuzhiyun #define OMAP_GPIO_LEVELDETECT0 0x0140 93*4882a593Smuzhiyun #define OMAP_GPIO_LEVELDETECT1 0x0144 94*4882a593Smuzhiyun #define OMAP_GPIO_RISINGDETECT 0x0148 95*4882a593Smuzhiyun #define OMAP_GPIO_FALLINGDETECT 0x014c 96*4882a593Smuzhiyun #define OMAP_GPIO_DEBOUNCE_EN 0x0150 97*4882a593Smuzhiyun #define OMAP_GPIO_DEBOUNCE_VAL 0x0154 98*4882a593Smuzhiyun #define OMAP_GPIO_CLEARIRQENABLE1 0x0160 99*4882a593Smuzhiyun #define OMAP_GPIO_SETIRQENABLE1 0x0164 100*4882a593Smuzhiyun #define OMAP_GPIO_CLEARWKUENA 0x0180 101*4882a593Smuzhiyun #define OMAP_GPIO_SETWKUENA 0x0184 102*4882a593Smuzhiyun #define OMAP_GPIO_CLEARDATAOUT 0x0190 103*4882a593Smuzhiyun #define OMAP_GPIO_SETDATAOUT 0x0194 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* 106*4882a593Smuzhiyun * PRCM 107*4882a593Smuzhiyun */ 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* PRM */ 110*4882a593Smuzhiyun #define PRM_BASE 0x4AE06000 111*4882a593Smuzhiyun #define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define PRM_RSTCTRL PRM_DEVICE_BASE 114*4882a593Smuzhiyun #define PRM_RSTCTRL_RESET 0x01 115*4882a593Smuzhiyun #define PRM_RSTST (PRM_DEVICE_BASE + 0x4) 116*4882a593Smuzhiyun #define PRM_RSTST_WARM_RESET_MASK 0x7FEA 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* DRA7XX CPSW Config space */ 119*4882a593Smuzhiyun #define CPSW_BASE 0x48484000 120*4882a593Smuzhiyun #define CPSW_MDIO_BASE 0x48485000 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* gmii_sel register defines */ 123*4882a593Smuzhiyun #define GMII1_SEL_MII 0x0 124*4882a593Smuzhiyun #define GMII1_SEL_RMII 0x1 125*4882a593Smuzhiyun #define GMII1_SEL_RGMII 0x2 126*4882a593Smuzhiyun #define GMII2_SEL_MII (GMII1_SEL_MII << 4) 127*4882a593Smuzhiyun #define GMII2_SEL_RMII (GMII1_SEL_RMII << 4) 128*4882a593Smuzhiyun #define GMII2_SEL_RGMII (GMII1_SEL_RGMII << 4) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII) 131*4882a593Smuzhiyun #define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII) 132*4882a593Smuzhiyun #define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII) 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #endif /* _CPU_H */ 135