1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun chosen: chosen { 9*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; 10*4882a593Smuzhiyun }; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun fiq-debugger { 13*4882a593Smuzhiyun compatible = "rockchip,fiq-debugger"; 14*4882a593Smuzhiyun rockchip,serial-id = <0>; 15*4882a593Smuzhiyun rockchip,wake-irq = <0>; 16*4882a593Smuzhiyun /* If enable uart uses irq instead of fiq */ 17*4882a593Smuzhiyun rockchip,irq-mode-enable = <1>; 18*4882a593Smuzhiyun rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 19*4882a593Smuzhiyun interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 20*4882a593Smuzhiyun pinctrl-names = "default"; 21*4882a593Smuzhiyun pinctrl-0 = <&uart0m0_xfer>; 22*4882a593Smuzhiyun status = "okay"; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun firmware { 26*4882a593Smuzhiyun optee { 27*4882a593Smuzhiyun compatible = "linaro,optee-tz"; 28*4882a593Smuzhiyun method = "smc"; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun reserved_memory: reserved-memory { 33*4882a593Smuzhiyun #address-cells = <2>; 34*4882a593Smuzhiyun #size-cells = <2>; 35*4882a593Smuzhiyun ranges; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun drm_logo: drm-logo@00000000 { 38*4882a593Smuzhiyun compatible = "rockchip,drm-logo"; 39*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0x0>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun drm_cubic_lut: drm-cubic-lut@00000000 { 43*4882a593Smuzhiyun compatible = "rockchip,drm-cubic-lut"; 44*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0x0>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun ramoops: ramoops@110000 { 48*4882a593Smuzhiyun compatible = "ramoops"; 49*4882a593Smuzhiyun /* 0x110000 to 0x1f0000 is for ramoops */ 50*4882a593Smuzhiyun reg = <0x0 0x110000 0x0 0xe0000>; 51*4882a593Smuzhiyun boot-log-size = <0x8000>; /* do not change */ 52*4882a593Smuzhiyun boot-log-count = <0x1>; /* do not change */ 53*4882a593Smuzhiyun console-size = <0x80000>; 54*4882a593Smuzhiyun pmsg-size = <0x30000>; 55*4882a593Smuzhiyun ftrace-size = <0x00000>; 56*4882a593Smuzhiyun record-size = <0x14000>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun}; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun&display_subsystem { 62*4882a593Smuzhiyun memory-region = <&drm_logo>, <&drm_cubic_lut>; 63*4882a593Smuzhiyun memory-region-names = "drm-logo", "drm-cubic-lut"; 64*4882a593Smuzhiyun /* devfreq = <&dmc>; */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun route { 67*4882a593Smuzhiyun route_hdmi: route-hdmi { 68*4882a593Smuzhiyun status = "okay"; 69*4882a593Smuzhiyun logo,uboot = "logo.bmp"; 70*4882a593Smuzhiyun logo,kernel = "logo_kernel.bmp"; 71*4882a593Smuzhiyun logo,mode = "center"; 72*4882a593Smuzhiyun charge_logo,mode = "center"; 73*4882a593Smuzhiyun connect = <&vp0_out_hdmi>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun route_tve: route-tve { 76*4882a593Smuzhiyun status = "okay"; 77*4882a593Smuzhiyun logo,uboot = "logo.bmp"; 78*4882a593Smuzhiyun logo,kernel = "logo_kernel.bmp"; 79*4882a593Smuzhiyun logo,mode = "center"; 80*4882a593Smuzhiyun charge_logo,mode = "center"; 81*4882a593Smuzhiyun connect = <&vp1_out_tve>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun}; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun&rng { 87*4882a593Smuzhiyun status = "okay"; 88*4882a593Smuzhiyun}; 89
