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/OK3568_Linux_fs/kernel/drivers/net/ethernet/qlogic/qed/
H A Dqed_init_ops.c25 0,
26 0,
27 0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */
28 0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */
29 0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */
30 0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */
31 0x1d02, /* win 6: addr=0x1d02000, size=4096 bytes */
32 0x1d80, /* win 7: addr=0x1d80000, size=4096 bytes */
33 0x1d81, /* win 8: addr=0x1d81000, size=4096 bytes */
34 0x1d82, /* win 9: addr=0x1d82000, size=4096 bytes */
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-orion5x/
H A Dts209-setup.c29 #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000
38 * [2] 0x00000000-0x00200000 : "Kernel"
39 * [3] 0x00200000-0x00600000 : "RootFS1"
40 * [4] 0x00600000-0x00700000 : "RootFS2"
41 * [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
42 * [5] 0x00760000-0x00780000 : "U-Boot Config"
43 * [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
48 .size = 0x00080000,
49 .offset = 0x00780000,
53 .size = 0x00200000,
[all …]
H A Dts409-setup.c40 * - RTC S35390A (@0x30) on I2C bus
49 #define QNAP_TS409_NOR_BOOT_BASE 0xff800000
58 * [2] 0x00000000-0x00200000 : "Kernel"
59 * [3] 0x00200000-0x00600000 : "RootFS1"
60 * [4] 0x00600000-0x00700000 : "RootFS2"
61 * [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
62 * [5] 0x00760000-0x00780000 : "U-Boot Config"
63 * [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
68 .size = 0x00080000,
69 .offset = 0x00780000,
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/nvmem/
H A Dqcom,qfprom.yaml64 reg = <0 0x00784000 0 0x8ff>,
65 <0 0x00780000 0 0x7a0>,
66 <0 0x00782000 0 0x100>,
67 <0 0x00786000 0 0x1fff>;
76 reg = <0x25b 0x1>;
89 reg = <0 0x00784000 0 0x8ff>;
94 reg = <0x1eb 0x1>;
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dmucmc52.dts78 phy0: ethernet-phy@0 {
80 reg = <0>;
91 reg = <0x2c>;
95 reg = <0x51>;
101 interrupt-map-mask = <0xf800 0 0 7>;
103 /* IDSEL 0x10 */
104 0x8000 0 0 1 &mpc5200_pic 0 3 3
105 0x8000 0 0 2 &mpc5200_pic 0 3 3
106 0x8000 0 0 3 &mpc5200_pic 0 2 3
107 0x8000 0 0 4 &mpc5200_pic 0 1 3
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dam335x-igep0033.dtsi15 cpu@0 {
22 reg = <0x80000000 0x10000000>; /* 256 MB */
27 pinctrl-0 = <&leds_pins>;
103 ethphy0: ethernet-phy@0 {
104 reg = <0>;
130 pinctrl-0 = <&nandflash_pins>;
132 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
134 nand@0,0 {
136 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
138 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
[all …]
H A Dsam9x60.dtsi36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
47 reg = <0x20000000 0x10000000>;
53 #clock-cells = <0>;
58 #clock-cells = <0>;
64 reg = <0x00300000 0x100000>;
67 ranges = <0 0x00300000 0x100000>;
78 #size-cells = <0>;
80 reg = <0x00500000 0x100000
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/nohash/
H A Dmmu-book3e.h9 #define BOOK3E_PAGESZ_1K 0
44 #define MAS0_TLBSEL_MASK 0x30000000
49 #define MAS0_ESEL_MASK 0x0FFF0000
52 #define MAS0_NV(x) ((x) & 0x00000FFF)
53 #define MAS0_HES 0x00004000
54 #define MAS0_WQ_ALLWAYS 0x00000000
55 #define MAS0_WQ_COND 0x00001000
56 #define MAS0_WQ_CLR_RSRV 0x00002000
58 #define MAS1_VALID 0x80000000
59 #define MAS1_IPROT 0x40000000
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram.h23 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
30 u32 dram_timing4; /* 0x10 */
35 u32 dram_addrw; /* 0x2c */
36 u32 dram_if_width; /* 0x30 */
40 u32 sbe_count; /* 0x40 */
44 u32 drop_addr; /* 0x50 */
48 u32 ctrl_width; /* 0x60 */
52 u32 rfifo_cmap; /* 0x70 */
56 u32 fpgaport_rst; /* 0x80 */
60 u32 prot_rule_addr; /* 0x90 */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dradeon_combios.c138 uint16_t offset = 0, check_offset; in combios_get_table_offset()
141 return 0; in combios_get_table_offset()
146 check_offset = 0xc; in combios_get_table_offset()
149 check_offset = 0x14; in combios_get_table_offset()
152 check_offset = 0x2a; in combios_get_table_offset()
155 check_offset = 0x2c; in combios_get_table_offset()
158 check_offset = 0x2e; in combios_get_table_offset()
161 check_offset = 0x30; in combios_get_table_offset()
164 check_offset = 0x32; in combios_get_table_offset()
167 check_offset = 0x34; in combios_get_table_offset()
[all …]
/OK3568_Linux_fs/kernel/drivers/rapidio/devices/
H A Dtsi721.h13 DBG_NONE = 0,
14 DBG_INIT = BIT(0), /* driver init */
26 DBG_ALL = ~0,
36 } while (0)
53 #define DEFAULT_HOPCOUNT 0xff
54 #define DEFAULT_DESTID 0xff
57 #define PCI_DEVICE_ID_TSI721 0x80ab
59 #define BAR_0 0
67 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
68 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
[all …]
/OK3568_Linux_fs/kernel/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/qcom/
H A Dsdm630.dtsi22 #clock-cells = <0>;
29 #clock-cells = <0>;
37 #size-cells = <0>;
42 reg = <0x0 0x100>;
61 reg = <0x0 0x101>;
76 reg = <0x0 0x102>;
91 reg = <0x0 0x103>;
103 CPU4: cpu@0 {
106 reg = <0x0 0x0>;
125 reg = <0x0 0x1>;
[all …]
H A Dmsm8998.dtsi14 qcom,msm-id = <292 0x0>;
24 reg = <0 0 0 0>;
33 reg = <0x0 0x85800000 0x0 0x600000>;
38 reg = <0x0 0x85e00000 0x0 0x100000>;
43 reg = <0x0 0x86000000 0x0 0x200000>;
48 reg = <0x0 0x86200000 0x0 0x2d00000>;
54 reg = <0x0 0x88f00000 0x0 0x200000>;
62 reg = <0x0 0x8ab00000 0x0 0x700000>;
67 reg = <0x0 0x8b200000 0x0 0x1a00000>;
72 reg = <0x0 0x8cc00000 0x0 0x7000000>;
[all …]
H A Dsc7180.dtsi60 #clock-cells = <0>;
66 #clock-cells = <0>;
76 reg = <0x0 0x80000000 0x0 0x600000>;
81 reg = <0x0 0x80600000 0x0 0x200000>;
86 reg = <0x0 0x80800000 0x0 0x20000>;
91 reg = <0x0 0x80820000 0x0 0x20000>;
97 reg = <0x0 0x808ff000 0x0 0x1000>;
102 reg = <0x0 0x80900000 0x0 0x200000>;
107 reg = <0x0 0x80b00000 0x0 0x3900000>;
113 reg = <0x0 0x84400000 0x0 0x200000>;
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath9k/
H A Dar9003_phy.h23 #define AR_CHAN_BASE 0x9800
25 #define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0)
26 #define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4)
27 #define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8)
28 #define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc)
29 #define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10)
30 #define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14)
31 #define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18)
32 #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c)
33 #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc)
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/fsl/
H A Dctrl_regs.c30 * 0 = Rtt disabled
35 * 0 = Rtt disabled
48 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
62 rtt = 0; in fsl_ddr_get_rtt()
66 rtt = 0; in fsl_ddr_get_rtt()
152 unsigned int cs_n_en = 0; /* Chip Select enable */ in set_csn_config()
153 unsigned int intlv_en = 0; /* Memory controller interleave enable */ in set_csn_config()
154 unsigned int intlv_ctl = 0; /* Interleaving control */ in set_csn_config()
155 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ in set_csn_config()
156 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */ in set_csn_config()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/sun/
H A Dniu.h10 #define PIO 0x000000UL
11 #define FZC_PIO 0x080000UL
12 #define FZC_MAC 0x180000UL
13 #define FZC_IPP 0x280000UL
14 #define FFLP 0x300000UL
15 #define FZC_FFLP 0x380000UL
16 #define PIO_VADDR 0x400000UL
17 #define ZCP 0x500000UL
18 #define FZC_ZCP 0x580000UL
19 #define DMC 0x600000UL
[all …]
/OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/
H A Dimmap_85xx.h29 #define CCSRAR_C 0x80000000 /* Commit */
38 u8 res3[0xbd4];
45 u8 res35[0x204];
58 u32 lawbar0; /* Local Access Window 0 Base Addr */
60 u32 lawar0; /* Local Access Window 0 Attrs */
118 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
119 #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
178 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
179 u8 res2[4048]; /* fill up to 0x1000 */
192 u32 potar0; /* PCIX Outbound Transaction Addr 0 */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/intel/iwlegacy/
H A Dcommands.h72 #define IL_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
73 #define IL_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
74 #define IL_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
75 #define IL_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
83 N_ALIVE = 0x1,
84 N_ERROR = 0x2,
87 C_RXON = 0x10,
88 C_RXON_ASSOC = 0x11,
89 C_QOS_PARAM = 0x13,
90 C_RXON_TIMING = 0x14,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/intel/iwlwifi/dvm/
H A Dcommands.h72 REPLY_ALIVE = 0x1,
73 REPLY_ERROR = 0x2,
74 REPLY_ECHO = 0x3, /* test command */
77 REPLY_RXON = 0x10,
78 REPLY_RXON_ASSOC = 0x11,
79 REPLY_QOS_PARAM = 0x13,
80 REPLY_RXON_TIMING = 0x14,
83 REPLY_ADD_STA = 0x18,
84 REPLY_REMOVE_STA = 0x19,
85 REPLY_REMOVE_ALL_STA = 0x1a, /* not used */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/ssv6xxx/include/
H A Dssv6200_aux.h17 #define MCU_ENABLE_MSK 0x00000001
18 #define MCU_ENABLE_I_MSK 0xfffffffe
19 #define MCU_ENABLE_SFT 0
20 #define MCU_ENABLE_HI 0
22 #define MAC_SW_RST_MSK 0x00000002
23 #define MAC_SW_RST_I_MSK 0xfffffffd
27 #define MCU_SW_RST_MSK 0x00000004
28 #define MCU_SW_RST_I_MSK 0xfffffffb
32 #define SDIO_SW_RST_MSK 0x00000008
33 #define SDIO_SW_RST_I_MSK 0xfffffff7
[all …]
H A Dssv6200_reg.h17 #define SYS_REG_BASE 0xc0000000
18 #define WBOOT_REG_BASE 0xc0000100
19 #define TU0_US_REG_BASE 0xc0000200
20 #define TU1_US_REG_BASE 0xc0000210
21 #define TU2_US_REG_BASE 0xc0000220
22 #define TU3_US_REG_BASE 0xc0000230
23 #define TM0_MS_REG_BASE 0xc0000240
24 #define TM1_MS_REG_BASE 0xc0000250
25 #define TM2_MS_REG_BASE 0xc0000260
26 #define TM3_MS_REG_BASE 0xc0000270
[all …]