1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Manroland mucmc52 board Device Tree Source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009 DENX Software Engineering GmbH 6*4882a593Smuzhiyun * Heiko Schocher <hs@denx.de> 7*4882a593Smuzhiyun * Copyright 2006-2007 Secret Lab Technologies Ltd. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/include/ "mpc5200b.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/* Timer pins that need to be in GPIO mode */ 13*4882a593Smuzhiyun&gpt0 { gpio-controller; }; 14*4882a593Smuzhiyun&gpt1 { gpio-controller; }; 15*4882a593Smuzhiyun&gpt2 { gpio-controller; }; 16*4882a593Smuzhiyun&gpt3 { gpio-controller; }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun/* Disabled timers */ 19*4882a593Smuzhiyun&gpt4 { status = "disabled"; }; 20*4882a593Smuzhiyun&gpt5 { status = "disabled"; }; 21*4882a593Smuzhiyun&gpt6 { status = "disabled"; }; 22*4882a593Smuzhiyun&gpt7 { status = "disabled"; }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun/ { 25*4882a593Smuzhiyun model = "manroland,mucmc52"; 26*4882a593Smuzhiyun compatible = "manroland,mucmc52"; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun soc5200@f0000000 { 29*4882a593Smuzhiyun rtc@800 { 30*4882a593Smuzhiyun status = "disabled"; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun can@900 { 34*4882a593Smuzhiyun status = "disabled"; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun can@980 { 38*4882a593Smuzhiyun status = "disabled"; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun spi@f00 { 42*4882a593Smuzhiyun status = "disabled"; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun usb@1000 { 46*4882a593Smuzhiyun status = "disabled"; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun psc@2000 { // PSC1 50*4882a593Smuzhiyun compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun psc@2200 { // PSC2 54*4882a593Smuzhiyun compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun psc@2400 { // PSC3 58*4882a593Smuzhiyun status = "disabled"; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun psc@2600 { // PSC4 62*4882a593Smuzhiyun status = "disabled"; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun psc@2800 { // PSC5 66*4882a593Smuzhiyun status = "disabled"; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun psc@2c00 { // PSC6 70*4882a593Smuzhiyun compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun ethernet@3000 { 74*4882a593Smuzhiyun phy-handle = <&phy0>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun mdio@3000 { 78*4882a593Smuzhiyun phy0: ethernet-phy@0 { 79*4882a593Smuzhiyun compatible = "intel,lxt971"; 80*4882a593Smuzhiyun reg = <0>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun i2c@3d00 { 85*4882a593Smuzhiyun status = "disabled"; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun i2c@3d40 { 89*4882a593Smuzhiyun hwmon@2c { 90*4882a593Smuzhiyun compatible = "ad,adm9240"; 91*4882a593Smuzhiyun reg = <0x2c>; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun rtc@51 { 94*4882a593Smuzhiyun compatible = "nxp,pcf8563"; 95*4882a593Smuzhiyun reg = <0x51>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun pci@f0000d00 { 101*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0 0 7>; 102*4882a593Smuzhiyun interrupt-map = < 103*4882a593Smuzhiyun /* IDSEL 0x10 */ 104*4882a593Smuzhiyun 0x8000 0 0 1 &mpc5200_pic 0 3 3 105*4882a593Smuzhiyun 0x8000 0 0 2 &mpc5200_pic 0 3 3 106*4882a593Smuzhiyun 0x8000 0 0 3 &mpc5200_pic 0 2 3 107*4882a593Smuzhiyun 0x8000 0 0 4 &mpc5200_pic 0 1 3 108*4882a593Smuzhiyun >; 109*4882a593Smuzhiyun ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000 110*4882a593Smuzhiyun 0x02000000 0 0x90000000 0x90000000 0 0x10000000 111*4882a593Smuzhiyun 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun localbus { 115*4882a593Smuzhiyun ranges = <0 0 0xff800000 0x00800000 116*4882a593Smuzhiyun 1 0 0x80000000 0x00800000 117*4882a593Smuzhiyun 3 0 0x80000000 0x00800000>; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun flash@0,0 { 120*4882a593Smuzhiyun compatible = "cfi-flash"; 121*4882a593Smuzhiyun reg = <0 0 0x00800000>; 122*4882a593Smuzhiyun bank-width = <4>; 123*4882a593Smuzhiyun device-width = <2>; 124*4882a593Smuzhiyun #size-cells = <1>; 125*4882a593Smuzhiyun #address-cells = <1>; 126*4882a593Smuzhiyun partition@0 { 127*4882a593Smuzhiyun label = "DTS"; 128*4882a593Smuzhiyun reg = <0x0 0x00100000>; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun partition@100000 { 131*4882a593Smuzhiyun label = "Kernel"; 132*4882a593Smuzhiyun reg = <0x100000 0x00200000>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun partition@300000 { 135*4882a593Smuzhiyun label = "RootFS"; 136*4882a593Smuzhiyun reg = <0x00300000 0x00200000>; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun partition@500000 { 139*4882a593Smuzhiyun label = "user"; 140*4882a593Smuzhiyun reg = <0x00500000 0x00200000>; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun partition@700000 { 143*4882a593Smuzhiyun label = "U-Boot"; 144*4882a593Smuzhiyun reg = <0x00700000 0x00040000>; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun partition@740000 { 147*4882a593Smuzhiyun label = "Env"; 148*4882a593Smuzhiyun reg = <0x00740000 0x00020000>; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun partition@760000 { 151*4882a593Smuzhiyun label = "red. Env"; 152*4882a593Smuzhiyun reg = <0x00760000 0x00020000>; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun partition@780000 { 155*4882a593Smuzhiyun label = "reserve"; 156*4882a593Smuzhiyun reg = <0x00780000 0x00080000>; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun simple100: gpio-controller-100@3,600100 { 161*4882a593Smuzhiyun compatible = "manroland,mucmc52-aux-gpio"; 162*4882a593Smuzhiyun reg = <3 0x00600100 0x1>; 163*4882a593Smuzhiyun gpio-controller; 164*4882a593Smuzhiyun #gpio-cells = <2>; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun simple104: gpio-controller-104@3,600104 { 167*4882a593Smuzhiyun compatible = "manroland,mucmc52-aux-gpio"; 168*4882a593Smuzhiyun reg = <3 0x00600104 0x1>; 169*4882a593Smuzhiyun gpio-controller; 170*4882a593Smuzhiyun #gpio-cells = <2>; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun simple200: gpio-controller-200@3,600200 { 173*4882a593Smuzhiyun compatible = "manroland,mucmc52-aux-gpio"; 174*4882a593Smuzhiyun reg = <3 0x00600200 0x1>; 175*4882a593Smuzhiyun gpio-controller; 176*4882a593Smuzhiyun #gpio-cells = <2>; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun simple201: gpio-controller-201@3,600201 { 179*4882a593Smuzhiyun compatible = "manroland,mucmc52-aux-gpio"; 180*4882a593Smuzhiyun reg = <3 0x00600201 0x1>; 181*4882a593Smuzhiyun gpio-controller; 182*4882a593Smuzhiyun #gpio-cells = <2>; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun simple202: gpio-controller-202@3,600202 { 185*4882a593Smuzhiyun compatible = "manroland,mucmc52-aux-gpio"; 186*4882a593Smuzhiyun reg = <3 0x00600202 0x1>; 187*4882a593Smuzhiyun gpio-controller; 188*4882a593Smuzhiyun #gpio-cells = <2>; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun simple203: gpio-controller-203@3,600203 { 191*4882a593Smuzhiyun compatible = "manroland,mucmc52-aux-gpio"; 192*4882a593Smuzhiyun reg = <3 0x00600203 0x1>; 193*4882a593Smuzhiyun gpio-controller; 194*4882a593Smuzhiyun #gpio-cells = <2>; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun simple204: gpio-controller-204@3,600204 { 197*4882a593Smuzhiyun compatible = "manroland,mucmc52-aux-gpio"; 198*4882a593Smuzhiyun reg = <3 0x00600204 0x1>; 199*4882a593Smuzhiyun gpio-controller; 200*4882a593Smuzhiyun #gpio-cells = <2>; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun simple206: gpio-controller-206@3,600206 { 203*4882a593Smuzhiyun compatible = "manroland,mucmc52-aux-gpio"; 204*4882a593Smuzhiyun reg = <3 0x00600206 0x1>; 205*4882a593Smuzhiyun gpio-controller; 206*4882a593Smuzhiyun #gpio-cells = <2>; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun simple207: gpio-controller-207@3,600207 { 209*4882a593Smuzhiyun compatible = "manroland,mucmc52-aux-gpio"; 210*4882a593Smuzhiyun reg = <3 0x00600207 0x1>; 211*4882a593Smuzhiyun gpio-controller; 212*4882a593Smuzhiyun #gpio-cells = <2>; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun simple20f: gpio-controller-20f@3,60020f { 215*4882a593Smuzhiyun compatible = "manroland,mucmc52-aux-gpio"; 216*4882a593Smuzhiyun reg = <3 0x0060020f 0x1>; 217*4882a593Smuzhiyun gpio-controller; 218*4882a593Smuzhiyun #gpio-cells = <2>; 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun}; 223