1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * QNAP TS-109/TS-209 Board Setup
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Maintainer: Byron Bradley <byron.bbradley@gmail.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/gpio.h>
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun #include <linux/pci.h>
12*4882a593Smuzhiyun #include <linux/irq.h>
13*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
14*4882a593Smuzhiyun #include <linux/mtd/rawnand.h>
15*4882a593Smuzhiyun #include <linux/mv643xx_eth.h>
16*4882a593Smuzhiyun #include <linux/gpio_keys.h>
17*4882a593Smuzhiyun #include <linux/input.h>
18*4882a593Smuzhiyun #include <linux/i2c.h>
19*4882a593Smuzhiyun #include <linux/serial_reg.h>
20*4882a593Smuzhiyun #include <linux/ata_platform.h>
21*4882a593Smuzhiyun #include <asm/mach-types.h>
22*4882a593Smuzhiyun #include <asm/mach/arch.h>
23*4882a593Smuzhiyun #include <asm/mach/pci.h>
24*4882a593Smuzhiyun #include "common.h"
25*4882a593Smuzhiyun #include "mpp.h"
26*4882a593Smuzhiyun #include "orion5x.h"
27*4882a593Smuzhiyun #include "tsx09-common.h"
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000
30*4882a593Smuzhiyun #define QNAP_TS209_NOR_BOOT_SIZE SZ_8M
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /****************************************************************************
33*4882a593Smuzhiyun * 8MiB NOR flash. The struct mtd_partition is not in the same order as the
34*4882a593Smuzhiyun * partitions on the device because we want to keep compatibility with
35*4882a593Smuzhiyun * existing QNAP firmware.
36*4882a593Smuzhiyun *
37*4882a593Smuzhiyun * Layout as used by QNAP:
38*4882a593Smuzhiyun * [2] 0x00000000-0x00200000 : "Kernel"
39*4882a593Smuzhiyun * [3] 0x00200000-0x00600000 : "RootFS1"
40*4882a593Smuzhiyun * [4] 0x00600000-0x00700000 : "RootFS2"
41*4882a593Smuzhiyun * [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
42*4882a593Smuzhiyun * [5] 0x00760000-0x00780000 : "U-Boot Config"
43*4882a593Smuzhiyun * [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
44*4882a593Smuzhiyun ***************************************************************************/
45*4882a593Smuzhiyun static struct mtd_partition qnap_ts209_partitions[] = {
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun .name = "U-Boot",
48*4882a593Smuzhiyun .size = 0x00080000,
49*4882a593Smuzhiyun .offset = 0x00780000,
50*4882a593Smuzhiyun .mask_flags = MTD_WRITEABLE,
51*4882a593Smuzhiyun }, {
52*4882a593Smuzhiyun .name = "Kernel",
53*4882a593Smuzhiyun .size = 0x00200000,
54*4882a593Smuzhiyun .offset = 0,
55*4882a593Smuzhiyun }, {
56*4882a593Smuzhiyun .name = "RootFS1",
57*4882a593Smuzhiyun .size = 0x00400000,
58*4882a593Smuzhiyun .offset = 0x00200000,
59*4882a593Smuzhiyun }, {
60*4882a593Smuzhiyun .name = "RootFS2",
61*4882a593Smuzhiyun .size = 0x00100000,
62*4882a593Smuzhiyun .offset = 0x00600000,
63*4882a593Smuzhiyun }, {
64*4882a593Smuzhiyun .name = "U-Boot Config",
65*4882a593Smuzhiyun .size = 0x00020000,
66*4882a593Smuzhiyun .offset = 0x00760000,
67*4882a593Smuzhiyun }, {
68*4882a593Smuzhiyun .name = "NAS Config",
69*4882a593Smuzhiyun .size = 0x00060000,
70*4882a593Smuzhiyun .offset = 0x00700000,
71*4882a593Smuzhiyun .mask_flags = MTD_WRITEABLE,
72*4882a593Smuzhiyun },
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun static struct physmap_flash_data qnap_ts209_nor_flash_data = {
76*4882a593Smuzhiyun .width = 1,
77*4882a593Smuzhiyun .parts = qnap_ts209_partitions,
78*4882a593Smuzhiyun .nr_parts = ARRAY_SIZE(qnap_ts209_partitions)
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static struct resource qnap_ts209_nor_flash_resource = {
82*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
83*4882a593Smuzhiyun .start = QNAP_TS209_NOR_BOOT_BASE,
84*4882a593Smuzhiyun .end = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1,
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun static struct platform_device qnap_ts209_nor_flash = {
88*4882a593Smuzhiyun .name = "physmap-flash",
89*4882a593Smuzhiyun .id = 0,
90*4882a593Smuzhiyun .dev = {
91*4882a593Smuzhiyun .platform_data = &qnap_ts209_nor_flash_data,
92*4882a593Smuzhiyun },
93*4882a593Smuzhiyun .resource = &qnap_ts209_nor_flash_resource,
94*4882a593Smuzhiyun .num_resources = 1,
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /*****************************************************************************
98*4882a593Smuzhiyun * PCI
99*4882a593Smuzhiyun ****************************************************************************/
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #define QNAP_TS209_PCI_SLOT0_OFFS 7
102*4882a593Smuzhiyun #define QNAP_TS209_PCI_SLOT0_IRQ_PIN 6
103*4882a593Smuzhiyun #define QNAP_TS209_PCI_SLOT1_IRQ_PIN 7
104*4882a593Smuzhiyun
qnap_ts209_pci_preinit(void)105*4882a593Smuzhiyun static void __init qnap_ts209_pci_preinit(void)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun int pin;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /*
110*4882a593Smuzhiyun * Configure PCI GPIO IRQ pins
111*4882a593Smuzhiyun */
112*4882a593Smuzhiyun pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN;
113*4882a593Smuzhiyun if (gpio_request(pin, "PCI Int1") == 0) {
114*4882a593Smuzhiyun if (gpio_direction_input(pin) == 0) {
115*4882a593Smuzhiyun irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
116*4882a593Smuzhiyun } else {
117*4882a593Smuzhiyun printk(KERN_ERR "qnap_ts209_pci_preinit failed to "
118*4882a593Smuzhiyun "set_irq_type pin %d\n", pin);
119*4882a593Smuzhiyun gpio_free(pin);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun } else {
122*4882a593Smuzhiyun printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request "
123*4882a593Smuzhiyun "%d\n", pin);
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN;
127*4882a593Smuzhiyun if (gpio_request(pin, "PCI Int2") == 0) {
128*4882a593Smuzhiyun if (gpio_direction_input(pin) == 0) {
129*4882a593Smuzhiyun irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
130*4882a593Smuzhiyun } else {
131*4882a593Smuzhiyun printk(KERN_ERR "qnap_ts209_pci_preinit failed "
132*4882a593Smuzhiyun "to set_irq_type pin %d\n", pin);
133*4882a593Smuzhiyun gpio_free(pin);
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun } else {
136*4882a593Smuzhiyun printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request "
137*4882a593Smuzhiyun "%d\n", pin);
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
qnap_ts209_pci_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)141*4882a593Smuzhiyun static int __init qnap_ts209_pci_map_irq(const struct pci_dev *dev, u8 slot,
142*4882a593Smuzhiyun u8 pin)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun int irq;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun /*
147*4882a593Smuzhiyun * Check for devices with hard-wired IRQs.
148*4882a593Smuzhiyun */
149*4882a593Smuzhiyun irq = orion5x_pci_map_irq(dev, slot, pin);
150*4882a593Smuzhiyun if (irq != -1)
151*4882a593Smuzhiyun return irq;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /*
154*4882a593Smuzhiyun * PCI IRQs are connected via GPIOs.
155*4882a593Smuzhiyun */
156*4882a593Smuzhiyun switch (slot - QNAP_TS209_PCI_SLOT0_OFFS) {
157*4882a593Smuzhiyun case 0:
158*4882a593Smuzhiyun return gpio_to_irq(QNAP_TS209_PCI_SLOT0_IRQ_PIN);
159*4882a593Smuzhiyun case 1:
160*4882a593Smuzhiyun return gpio_to_irq(QNAP_TS209_PCI_SLOT1_IRQ_PIN);
161*4882a593Smuzhiyun default:
162*4882a593Smuzhiyun return -1;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun static struct hw_pci qnap_ts209_pci __initdata = {
167*4882a593Smuzhiyun .nr_controllers = 2,
168*4882a593Smuzhiyun .preinit = qnap_ts209_pci_preinit,
169*4882a593Smuzhiyun .setup = orion5x_pci_sys_setup,
170*4882a593Smuzhiyun .scan = orion5x_pci_sys_scan_bus,
171*4882a593Smuzhiyun .map_irq = qnap_ts209_pci_map_irq,
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun
qnap_ts209_pci_init(void)174*4882a593Smuzhiyun static int __init qnap_ts209_pci_init(void)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun if (machine_is_ts209())
177*4882a593Smuzhiyun pci_common_init(&qnap_ts209_pci);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun return 0;
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun subsys_initcall(qnap_ts209_pci_init);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun /*****************************************************************************
185*4882a593Smuzhiyun * RTC S35390A on I2C bus
186*4882a593Smuzhiyun ****************************************************************************/
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun #define TS209_RTC_GPIO 3
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = {
191*4882a593Smuzhiyun I2C_BOARD_INFO("s35390a", 0x30),
192*4882a593Smuzhiyun .irq = 0,
193*4882a593Smuzhiyun };
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun /****************************************************************************
196*4882a593Smuzhiyun * GPIO Attached Keys
197*4882a593Smuzhiyun * Power button is attached to the PIC microcontroller
198*4882a593Smuzhiyun ****************************************************************************/
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun #define QNAP_TS209_GPIO_KEY_MEDIA 1
201*4882a593Smuzhiyun #define QNAP_TS209_GPIO_KEY_RESET 2
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun static struct gpio_keys_button qnap_ts209_buttons[] = {
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun .code = KEY_COPY,
206*4882a593Smuzhiyun .gpio = QNAP_TS209_GPIO_KEY_MEDIA,
207*4882a593Smuzhiyun .desc = "USB Copy Button",
208*4882a593Smuzhiyun .active_low = 1,
209*4882a593Smuzhiyun }, {
210*4882a593Smuzhiyun .code = KEY_RESTART,
211*4882a593Smuzhiyun .gpio = QNAP_TS209_GPIO_KEY_RESET,
212*4882a593Smuzhiyun .desc = "Reset Button",
213*4882a593Smuzhiyun .active_low = 1,
214*4882a593Smuzhiyun },
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun static struct gpio_keys_platform_data qnap_ts209_button_data = {
218*4882a593Smuzhiyun .buttons = qnap_ts209_buttons,
219*4882a593Smuzhiyun .nbuttons = ARRAY_SIZE(qnap_ts209_buttons),
220*4882a593Smuzhiyun };
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun static struct platform_device qnap_ts209_button_device = {
223*4882a593Smuzhiyun .name = "gpio-keys",
224*4882a593Smuzhiyun .id = -1,
225*4882a593Smuzhiyun .num_resources = 0,
226*4882a593Smuzhiyun .dev = {
227*4882a593Smuzhiyun .platform_data = &qnap_ts209_button_data,
228*4882a593Smuzhiyun },
229*4882a593Smuzhiyun };
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun /*****************************************************************************
232*4882a593Smuzhiyun * SATA
233*4882a593Smuzhiyun ****************************************************************************/
234*4882a593Smuzhiyun static struct mv_sata_platform_data qnap_ts209_sata_data = {
235*4882a593Smuzhiyun .n_ports = 2,
236*4882a593Smuzhiyun };
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun /*****************************************************************************
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun * General Setup
241*4882a593Smuzhiyun ****************************************************************************/
242*4882a593Smuzhiyun static unsigned int ts209_mpp_modes[] __initdata = {
243*4882a593Smuzhiyun MPP0_UNUSED,
244*4882a593Smuzhiyun MPP1_GPIO, /* USB copy button */
245*4882a593Smuzhiyun MPP2_GPIO, /* Load defaults button */
246*4882a593Smuzhiyun MPP3_GPIO, /* GPIO RTC */
247*4882a593Smuzhiyun MPP4_UNUSED,
248*4882a593Smuzhiyun MPP5_UNUSED,
249*4882a593Smuzhiyun MPP6_GPIO, /* PCI Int A */
250*4882a593Smuzhiyun MPP7_GPIO, /* PCI Int B */
251*4882a593Smuzhiyun MPP8_UNUSED,
252*4882a593Smuzhiyun MPP9_UNUSED,
253*4882a593Smuzhiyun MPP10_UNUSED,
254*4882a593Smuzhiyun MPP11_UNUSED,
255*4882a593Smuzhiyun MPP12_SATA_LED, /* SATA 0 presence */
256*4882a593Smuzhiyun MPP13_SATA_LED, /* SATA 1 presence */
257*4882a593Smuzhiyun MPP14_SATA_LED, /* SATA 0 active */
258*4882a593Smuzhiyun MPP15_SATA_LED, /* SATA 1 active */
259*4882a593Smuzhiyun MPP16_UART, /* UART1 RXD */
260*4882a593Smuzhiyun MPP17_UART, /* UART1 TXD */
261*4882a593Smuzhiyun MPP18_GPIO, /* SW_RST */
262*4882a593Smuzhiyun MPP19_UNUSED,
263*4882a593Smuzhiyun 0,
264*4882a593Smuzhiyun };
265*4882a593Smuzhiyun
qnap_ts209_init(void)266*4882a593Smuzhiyun static void __init qnap_ts209_init(void)
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun /*
269*4882a593Smuzhiyun * Setup basic Orion functions. Need to be called early.
270*4882a593Smuzhiyun */
271*4882a593Smuzhiyun orion5x_init();
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun orion5x_mpp_conf(ts209_mpp_modes);
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun /*
276*4882a593Smuzhiyun * MPP[20] PCI clock 0
277*4882a593Smuzhiyun * MPP[21] PCI clock 1
278*4882a593Smuzhiyun * MPP[22] USB 0 over current
279*4882a593Smuzhiyun * MPP[23-25] Reserved
280*4882a593Smuzhiyun */
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun /*
283*4882a593Smuzhiyun * Configure peripherals.
284*4882a593Smuzhiyun */
285*4882a593Smuzhiyun mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
286*4882a593Smuzhiyun ORION_MBUS_DEVBUS_BOOT_ATTR,
287*4882a593Smuzhiyun QNAP_TS209_NOR_BOOT_BASE,
288*4882a593Smuzhiyun QNAP_TS209_NOR_BOOT_SIZE);
289*4882a593Smuzhiyun platform_device_register(&qnap_ts209_nor_flash);
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun orion5x_ehci0_init();
292*4882a593Smuzhiyun orion5x_ehci1_init();
293*4882a593Smuzhiyun qnap_tsx09_find_mac_addr(QNAP_TS209_NOR_BOOT_BASE +
294*4882a593Smuzhiyun qnap_ts209_partitions[5].offset,
295*4882a593Smuzhiyun qnap_ts209_partitions[5].size);
296*4882a593Smuzhiyun orion5x_eth_init(&qnap_tsx09_eth_data);
297*4882a593Smuzhiyun orion5x_i2c_init();
298*4882a593Smuzhiyun orion5x_sata_init(&qnap_ts209_sata_data);
299*4882a593Smuzhiyun orion5x_uart0_init();
300*4882a593Smuzhiyun orion5x_uart1_init();
301*4882a593Smuzhiyun orion5x_xor_init();
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun platform_device_register(&qnap_ts209_button_device);
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun /* Get RTC IRQ and register the chip */
306*4882a593Smuzhiyun if (gpio_request(TS209_RTC_GPIO, "rtc") == 0) {
307*4882a593Smuzhiyun if (gpio_direction_input(TS209_RTC_GPIO) == 0)
308*4882a593Smuzhiyun qnap_ts209_i2c_rtc.irq = gpio_to_irq(TS209_RTC_GPIO);
309*4882a593Smuzhiyun else
310*4882a593Smuzhiyun gpio_free(TS209_RTC_GPIO);
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun if (qnap_ts209_i2c_rtc.irq == 0)
313*4882a593Smuzhiyun pr_warn("qnap_ts209_init: failed to get RTC IRQ\n");
314*4882a593Smuzhiyun i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun /* register tsx09 specific power-off method */
317*4882a593Smuzhiyun pm_power_off = qnap_tsx09_power_off;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun MACHINE_START(TS209, "QNAP TS-109/TS-209")
321*4882a593Smuzhiyun /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
322*4882a593Smuzhiyun .atag_offset = 0x100,
323*4882a593Smuzhiyun .nr_irqs = ORION5X_NR_IRQS,
324*4882a593Smuzhiyun .init_machine = qnap_ts209_init,
325*4882a593Smuzhiyun .map_io = orion5x_map_io,
326*4882a593Smuzhiyun .init_early = orion5x_init_early,
327*4882a593Smuzhiyun .init_irq = orion5x_init_irq,
328*4882a593Smuzhiyun .init_time = orion5x_timer_init,
329*4882a593Smuzhiyun .fixup = tag_fixup_mem32,
330*4882a593Smuzhiyun .restart = orion5x_restart,
331*4882a593Smuzhiyun MACHINE_END
332