1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include "am33xx.dtsi" 11*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun cpus { 15*4882a593Smuzhiyun cpu@0 { 16*4882a593Smuzhiyun cpu0-supply = <&vdd1_reg>; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun memory@80000000 { 21*4882a593Smuzhiyun device_type = "memory"; 22*4882a593Smuzhiyun reg = <0x80000000 0x10000000>; /* 256 MB */ 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun leds { 26*4882a593Smuzhiyun pinctrl-names = "default"; 27*4882a593Smuzhiyun pinctrl-0 = <&leds_pins>; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun compatible = "gpio-leds"; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun led0 { 32*4882a593Smuzhiyun label = "com:green:user"; 33*4882a593Smuzhiyun gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; 34*4882a593Smuzhiyun default-state = "on"; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun vbat: fixedregulator0 { 39*4882a593Smuzhiyun compatible = "regulator-fixed"; 40*4882a593Smuzhiyun regulator-name = "vbat"; 41*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 42*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 43*4882a593Smuzhiyun regulator-boot-on; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun vmmc: fixedregulator1 { 47*4882a593Smuzhiyun compatible = "regulator-fixed"; 48*4882a593Smuzhiyun regulator-name = "vmmc"; 49*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 50*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun}; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun&am33xx_pinmux { 55*4882a593Smuzhiyun i2c0_pins: pinmux_i2c0_pins { 56*4882a593Smuzhiyun pinctrl-single,pins = < 57*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) 58*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) 59*4882a593Smuzhiyun >; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun nandflash_pins: pinmux_nandflash_pins { 63*4882a593Smuzhiyun pinctrl-single,pins = < 64*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) 65*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) 66*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) 67*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) 68*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) 69*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) 70*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) 71*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) 72*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) 73*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */ 74*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) 75*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) 76*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) 77*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) 78*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) 79*4882a593Smuzhiyun >; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun uart0_pins: pinmux_uart0_pins { 83*4882a593Smuzhiyun pinctrl-single,pins = < 84*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 85*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 86*4882a593Smuzhiyun >; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun leds_pins: pinmux_leds_pins { 90*4882a593Smuzhiyun pinctrl-single,pins = < 91*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ 92*4882a593Smuzhiyun >; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun}; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun&mac { 97*4882a593Smuzhiyun status = "okay"; 98*4882a593Smuzhiyun}; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun&davinci_mdio { 101*4882a593Smuzhiyun status = "okay"; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun ethphy0: ethernet-phy@0 { 104*4882a593Smuzhiyun reg = <0>; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun ethphy1: ethernet-phy@1 { 108*4882a593Smuzhiyun reg = <1>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun}; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun&cpsw_emac0 { 113*4882a593Smuzhiyun phy-handle = <ðphy0>; 114*4882a593Smuzhiyun phy-mode = "rmii"; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun}; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun&cpsw_emac1 { 119*4882a593Smuzhiyun phy-handle = <ðphy1>; 120*4882a593Smuzhiyun phy-mode = "rmii"; 121*4882a593Smuzhiyun}; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun&elm { 124*4882a593Smuzhiyun status = "okay"; 125*4882a593Smuzhiyun}; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun&gpmc { 128*4882a593Smuzhiyun status = "okay"; 129*4882a593Smuzhiyun pinctrl-names = "default"; 130*4882a593Smuzhiyun pinctrl-0 = <&nandflash_pins>; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun nand@0,0 { 135*4882a593Smuzhiyun compatible = "ti,omap2-nand"; 136*4882a593Smuzhiyun reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 137*4882a593Smuzhiyun interrupt-parent = <&gpmc>; 138*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 139*4882a593Smuzhiyun <1 IRQ_TYPE_NONE>; /* termcount */ 140*4882a593Smuzhiyun rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ 141*4882a593Smuzhiyun nand-bus-width = <8>; 142*4882a593Smuzhiyun ti,nand-ecc-opt = "bch8"; 143*4882a593Smuzhiyun gpmc,device-width = <1>; 144*4882a593Smuzhiyun gpmc,sync-clk-ps = <0>; 145*4882a593Smuzhiyun gpmc,cs-on-ns = <0>; 146*4882a593Smuzhiyun gpmc,cs-rd-off-ns = <44>; 147*4882a593Smuzhiyun gpmc,cs-wr-off-ns = <44>; 148*4882a593Smuzhiyun gpmc,adv-on-ns = <6>; 149*4882a593Smuzhiyun gpmc,adv-rd-off-ns = <34>; 150*4882a593Smuzhiyun gpmc,adv-wr-off-ns = <44>; 151*4882a593Smuzhiyun gpmc,we-on-ns = <0>; 152*4882a593Smuzhiyun gpmc,we-off-ns = <40>; 153*4882a593Smuzhiyun gpmc,oe-on-ns = <0>; 154*4882a593Smuzhiyun gpmc,oe-off-ns = <54>; 155*4882a593Smuzhiyun gpmc,access-ns = <64>; 156*4882a593Smuzhiyun gpmc,rd-cycle-ns = <82>; 157*4882a593Smuzhiyun gpmc,wr-cycle-ns = <82>; 158*4882a593Smuzhiyun gpmc,bus-turnaround-ns = <0>; 159*4882a593Smuzhiyun gpmc,cycle2cycle-delay-ns = <0>; 160*4882a593Smuzhiyun gpmc,clk-activation-ns = <0>; 161*4882a593Smuzhiyun gpmc,wr-access-ns = <40>; 162*4882a593Smuzhiyun gpmc,wr-data-mux-bus-ns = <0>; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun #address-cells = <1>; 165*4882a593Smuzhiyun #size-cells = <1>; 166*4882a593Smuzhiyun ti,elm-id = <&elm>; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* MTD partition table */ 169*4882a593Smuzhiyun partition@0 { 170*4882a593Smuzhiyun label = "SPL"; 171*4882a593Smuzhiyun reg = <0x00000000 0x000080000>; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun partition@1 { 175*4882a593Smuzhiyun label = "U-boot"; 176*4882a593Smuzhiyun reg = <0x00080000 0x001e0000>; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun partition@2 { 180*4882a593Smuzhiyun label = "U-Boot Env"; 181*4882a593Smuzhiyun reg = <0x00260000 0x00020000>; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun partition@3 { 185*4882a593Smuzhiyun label = "Kernel"; 186*4882a593Smuzhiyun reg = <0x00280000 0x00500000>; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun partition@4 { 190*4882a593Smuzhiyun label = "File System"; 191*4882a593Smuzhiyun reg = <0x00780000 0x007880000>; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun}; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun&i2c0 { 197*4882a593Smuzhiyun status = "okay"; 198*4882a593Smuzhiyun pinctrl-names = "default"; 199*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins>; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun clock-frequency = <400000>; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun tps: tps@2d { 204*4882a593Smuzhiyun reg = <0x2d>; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun}; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun&mmc1 { 209*4882a593Smuzhiyun status = "okay"; 210*4882a593Smuzhiyun vmmc-supply = <&vmmc>; 211*4882a593Smuzhiyun bus-width = <4>; 212*4882a593Smuzhiyun}; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun&uart0 { 215*4882a593Smuzhiyun status = "okay"; 216*4882a593Smuzhiyun pinctrl-names = "default"; 217*4882a593Smuzhiyun pinctrl-0 = <&uart0_pins>; 218*4882a593Smuzhiyun}; 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun&usb1 { 221*4882a593Smuzhiyun dr_mode = "host"; 222*4882a593Smuzhiyun}; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun#include "tps65910.dtsi" 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun&tps { 227*4882a593Smuzhiyun vcc1-supply = <&vbat>; 228*4882a593Smuzhiyun vcc2-supply = <&vbat>; 229*4882a593Smuzhiyun vcc3-supply = <&vbat>; 230*4882a593Smuzhiyun vcc4-supply = <&vbat>; 231*4882a593Smuzhiyun vcc5-supply = <&vbat>; 232*4882a593Smuzhiyun vcc6-supply = <&vbat>; 233*4882a593Smuzhiyun vcc7-supply = <&vbat>; 234*4882a593Smuzhiyun vccio-supply = <&vbat>; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun regulators { 237*4882a593Smuzhiyun vrtc_reg: regulator@0 { 238*4882a593Smuzhiyun regulator-always-on; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun vio_reg: regulator@1 { 242*4882a593Smuzhiyun regulator-always-on; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun vdd1_reg: regulator@2 { 246*4882a593Smuzhiyun /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 247*4882a593Smuzhiyun regulator-name = "vdd_mpu"; 248*4882a593Smuzhiyun regulator-min-microvolt = <912500>; 249*4882a593Smuzhiyun regulator-max-microvolt = <1312500>; 250*4882a593Smuzhiyun regulator-boot-on; 251*4882a593Smuzhiyun regulator-always-on; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun vdd2_reg: regulator@3 { 255*4882a593Smuzhiyun /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 256*4882a593Smuzhiyun regulator-name = "vdd_core"; 257*4882a593Smuzhiyun regulator-min-microvolt = <912500>; 258*4882a593Smuzhiyun regulator-max-microvolt = <1150000>; 259*4882a593Smuzhiyun regulator-boot-on; 260*4882a593Smuzhiyun regulator-always-on; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun vdd3_reg: regulator@4 { 264*4882a593Smuzhiyun regulator-always-on; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun vdig1_reg: regulator@5 { 268*4882a593Smuzhiyun regulator-always-on; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun vdig2_reg: regulator@6 { 272*4882a593Smuzhiyun regulator-always-on; 273*4882a593Smuzhiyun }; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun vpll_reg: regulator@7 { 276*4882a593Smuzhiyun regulator-always-on; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun vdac_reg: regulator@8 { 280*4882a593Smuzhiyun regulator-always-on; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun vaux1_reg: regulator@9 { 284*4882a593Smuzhiyun regulator-always-on; 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun vaux2_reg: regulator@10 { 288*4882a593Smuzhiyun regulator-always-on; 289*4882a593Smuzhiyun }; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun vaux33_reg: regulator@11 { 292*4882a593Smuzhiyun regulator-always-on; 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun vmmc_reg: regulator@12 { 296*4882a593Smuzhiyun regulator-always-on; 297*4882a593Smuzhiyun }; 298*4882a593Smuzhiyun }; 299*4882a593Smuzhiyun}; 300*4882a593Smuzhiyun 301