1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * This file is provided under a dual BSD/GPLv2 license. When using or 4*4882a593Smuzhiyun * redistributing this file, you may do so under either license. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * GPL LICENSE SUMMARY 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 11*4882a593Smuzhiyun * it under the terms of version 2 of the GNU General Public License as 12*4882a593Smuzhiyun * published by the Free Software Foundation. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but 15*4882a593Smuzhiyun * WITHOUT ANY WARRANTY; without even the implied warranty of 16*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17*4882a593Smuzhiyun * General Public License for more details. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * The full GNU General Public License is included in this distribution 20*4882a593Smuzhiyun * in the file called COPYING. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Contact Information: 23*4882a593Smuzhiyun * Intel Linux Wireless <linuxwifi@intel.com> 24*4882a593Smuzhiyun * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * BSD LICENSE 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 29*4882a593Smuzhiyun * All rights reserved. 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without 32*4882a593Smuzhiyun * modification, are permitted provided that the following conditions 33*4882a593Smuzhiyun * are met: 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * * Redistributions of source code must retain the above copyright 36*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer. 37*4882a593Smuzhiyun * * Redistributions in binary form must reproduce the above copyright 38*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in 39*4882a593Smuzhiyun * the documentation and/or other materials provided with the 40*4882a593Smuzhiyun * distribution. 41*4882a593Smuzhiyun * * Neither the name Intel Corporation nor the names of its 42*4882a593Smuzhiyun * contributors may be used to endorse or promote products derived 43*4882a593Smuzhiyun * from this software without specific prior written permission. 44*4882a593Smuzhiyun * 45*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 46*4882a593Smuzhiyun * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 47*4882a593Smuzhiyun * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 48*4882a593Smuzhiyun * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 49*4882a593Smuzhiyun * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 50*4882a593Smuzhiyun * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 51*4882a593Smuzhiyun * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 52*4882a593Smuzhiyun * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 53*4882a593Smuzhiyun * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 54*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 55*4882a593Smuzhiyun * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56*4882a593Smuzhiyun * 57*4882a593Smuzhiyun *****************************************************************************/ 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * Please use this file (commands.h) only for uCode API definitions. 60*4882a593Smuzhiyun * Please use iwl-xxxx-hw.h for hardware-related definitions. 61*4882a593Smuzhiyun * Please use dev.h for driver implementation definitions. 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #ifndef __iwl_commands_h__ 65*4882a593Smuzhiyun #define __iwl_commands_h__ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #include <linux/ieee80211.h> 68*4882a593Smuzhiyun #include <linux/types.h> 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun enum { 72*4882a593Smuzhiyun REPLY_ALIVE = 0x1, 73*4882a593Smuzhiyun REPLY_ERROR = 0x2, 74*4882a593Smuzhiyun REPLY_ECHO = 0x3, /* test command */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* RXON and QOS commands */ 77*4882a593Smuzhiyun REPLY_RXON = 0x10, 78*4882a593Smuzhiyun REPLY_RXON_ASSOC = 0x11, 79*4882a593Smuzhiyun REPLY_QOS_PARAM = 0x13, 80*4882a593Smuzhiyun REPLY_RXON_TIMING = 0x14, 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Multi-Station support */ 83*4882a593Smuzhiyun REPLY_ADD_STA = 0x18, 84*4882a593Smuzhiyun REPLY_REMOVE_STA = 0x19, 85*4882a593Smuzhiyun REPLY_REMOVE_ALL_STA = 0x1a, /* not used */ 86*4882a593Smuzhiyun REPLY_TXFIFO_FLUSH = 0x1e, 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* Security */ 89*4882a593Smuzhiyun REPLY_WEPKEY = 0x20, 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* RX, TX, LEDs */ 92*4882a593Smuzhiyun REPLY_TX = 0x1c, 93*4882a593Smuzhiyun REPLY_LEDS_CMD = 0x48, 94*4882a593Smuzhiyun REPLY_TX_LINK_QUALITY_CMD = 0x4e, 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* WiMAX coexistence */ 97*4882a593Smuzhiyun COEX_PRIORITY_TABLE_CMD = 0x5a, 98*4882a593Smuzhiyun COEX_MEDIUM_NOTIFICATION = 0x5b, 99*4882a593Smuzhiyun COEX_EVENT_CMD = 0x5c, 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* Calibration */ 102*4882a593Smuzhiyun TEMPERATURE_NOTIFICATION = 0x62, 103*4882a593Smuzhiyun CALIBRATION_CFG_CMD = 0x65, 104*4882a593Smuzhiyun CALIBRATION_RES_NOTIFICATION = 0x66, 105*4882a593Smuzhiyun CALIBRATION_COMPLETE_NOTIFICATION = 0x67, 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* 802.11h related */ 108*4882a593Smuzhiyun REPLY_QUIET_CMD = 0x71, /* not used */ 109*4882a593Smuzhiyun REPLY_CHANNEL_SWITCH = 0x72, 110*4882a593Smuzhiyun CHANNEL_SWITCH_NOTIFICATION = 0x73, 111*4882a593Smuzhiyun REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74, 112*4882a593Smuzhiyun SPECTRUM_MEASURE_NOTIFICATION = 0x75, 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* Power Management */ 115*4882a593Smuzhiyun POWER_TABLE_CMD = 0x77, 116*4882a593Smuzhiyun PM_SLEEP_NOTIFICATION = 0x7A, 117*4882a593Smuzhiyun PM_DEBUG_STATISTIC_NOTIFIC = 0x7B, 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* Scan commands and notifications */ 120*4882a593Smuzhiyun REPLY_SCAN_CMD = 0x80, 121*4882a593Smuzhiyun REPLY_SCAN_ABORT_CMD = 0x81, 122*4882a593Smuzhiyun SCAN_START_NOTIFICATION = 0x82, 123*4882a593Smuzhiyun SCAN_RESULTS_NOTIFICATION = 0x83, 124*4882a593Smuzhiyun SCAN_COMPLETE_NOTIFICATION = 0x84, 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* IBSS/AP commands */ 127*4882a593Smuzhiyun BEACON_NOTIFICATION = 0x90, 128*4882a593Smuzhiyun REPLY_TX_BEACON = 0x91, 129*4882a593Smuzhiyun WHO_IS_AWAKE_NOTIFICATION = 0x94, /* not used */ 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* Miscellaneous commands */ 132*4882a593Smuzhiyun REPLY_TX_POWER_DBM_CMD = 0x95, 133*4882a593Smuzhiyun QUIET_NOTIFICATION = 0x96, /* not used */ 134*4882a593Smuzhiyun REPLY_TX_PWR_TABLE_CMD = 0x97, 135*4882a593Smuzhiyun REPLY_TX_POWER_DBM_CMD_V1 = 0x98, /* old version of API */ 136*4882a593Smuzhiyun TX_ANT_CONFIGURATION_CMD = 0x98, 137*4882a593Smuzhiyun MEASURE_ABORT_NOTIFICATION = 0x99, /* not used */ 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* Bluetooth device coexistence config command */ 140*4882a593Smuzhiyun REPLY_BT_CONFIG = 0x9b, 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* Statistics */ 143*4882a593Smuzhiyun REPLY_STATISTICS_CMD = 0x9c, 144*4882a593Smuzhiyun STATISTICS_NOTIFICATION = 0x9d, 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* RF-KILL commands and notifications */ 147*4882a593Smuzhiyun REPLY_CARD_STATE_CMD = 0xa0, 148*4882a593Smuzhiyun CARD_STATE_NOTIFICATION = 0xa1, 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* Missed beacons notification */ 151*4882a593Smuzhiyun MISSED_BEACONS_NOTIFICATION = 0xa2, 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun REPLY_CT_KILL_CONFIG_CMD = 0xa4, 154*4882a593Smuzhiyun SENSITIVITY_CMD = 0xa8, 155*4882a593Smuzhiyun REPLY_PHY_CALIBRATION_CMD = 0xb0, 156*4882a593Smuzhiyun REPLY_RX_PHY_CMD = 0xc0, 157*4882a593Smuzhiyun REPLY_RX_MPDU_CMD = 0xc1, 158*4882a593Smuzhiyun REPLY_RX = 0xc3, 159*4882a593Smuzhiyun REPLY_COMPRESSED_BA = 0xc5, 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* BT Coex */ 162*4882a593Smuzhiyun REPLY_BT_COEX_PRIO_TABLE = 0xcc, 163*4882a593Smuzhiyun REPLY_BT_COEX_PROT_ENV = 0xcd, 164*4882a593Smuzhiyun REPLY_BT_COEX_PROFILE_NOTIF = 0xce, 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* PAN commands */ 167*4882a593Smuzhiyun REPLY_WIPAN_PARAMS = 0xb2, 168*4882a593Smuzhiyun REPLY_WIPAN_RXON = 0xb3, /* use REPLY_RXON structure */ 169*4882a593Smuzhiyun REPLY_WIPAN_RXON_TIMING = 0xb4, /* use REPLY_RXON_TIMING structure */ 170*4882a593Smuzhiyun REPLY_WIPAN_RXON_ASSOC = 0xb6, /* use REPLY_RXON_ASSOC structure */ 171*4882a593Smuzhiyun REPLY_WIPAN_QOS_PARAM = 0xb7, /* use REPLY_QOS_PARAM structure */ 172*4882a593Smuzhiyun REPLY_WIPAN_WEPKEY = 0xb8, /* use REPLY_WEPKEY structure */ 173*4882a593Smuzhiyun REPLY_WIPAN_P2P_CHANNEL_SWITCH = 0xb9, 174*4882a593Smuzhiyun REPLY_WIPAN_NOA_NOTIFICATION = 0xbc, 175*4882a593Smuzhiyun REPLY_WIPAN_DEACTIVATION_COMPLETE = 0xbd, 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun REPLY_WOWLAN_PATTERNS = 0xe0, 178*4882a593Smuzhiyun REPLY_WOWLAN_WAKEUP_FILTER = 0xe1, 179*4882a593Smuzhiyun REPLY_WOWLAN_TSC_RSC_PARAMS = 0xe2, 180*4882a593Smuzhiyun REPLY_WOWLAN_TKIP_PARAMS = 0xe3, 181*4882a593Smuzhiyun REPLY_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 182*4882a593Smuzhiyun REPLY_WOWLAN_GET_STATUS = 0xe5, 183*4882a593Smuzhiyun REPLY_D3_CONFIG = 0xd3, 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun REPLY_MAX = 0xff 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* 189*4882a593Smuzhiyun * Minimum number of queues. MAX_NUM is defined in hw specific files. 190*4882a593Smuzhiyun * Set the minimum to accommodate 191*4882a593Smuzhiyun * - 4 standard TX queues 192*4882a593Smuzhiyun * - the command queue 193*4882a593Smuzhiyun * - 4 PAN TX queues 194*4882a593Smuzhiyun * - the PAN multicast queue, and 195*4882a593Smuzhiyun * - the AUX (TX during scan dwell) queue. 196*4882a593Smuzhiyun */ 197*4882a593Smuzhiyun #define IWL_MIN_NUM_QUEUES 11 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* 200*4882a593Smuzhiyun * Command queue depends on iPAN support. 201*4882a593Smuzhiyun */ 202*4882a593Smuzhiyun #define IWL_DEFAULT_CMD_QUEUE_NUM 4 203*4882a593Smuzhiyun #define IWL_IPAN_CMD_QUEUE_NUM 9 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun #define IWL_TX_FIFO_BK 0 /* shared */ 206*4882a593Smuzhiyun #define IWL_TX_FIFO_BE 1 207*4882a593Smuzhiyun #define IWL_TX_FIFO_VI 2 /* shared */ 208*4882a593Smuzhiyun #define IWL_TX_FIFO_VO 3 209*4882a593Smuzhiyun #define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK 210*4882a593Smuzhiyun #define IWL_TX_FIFO_BE_IPAN 4 211*4882a593Smuzhiyun #define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI 212*4882a593Smuzhiyun #define IWL_TX_FIFO_VO_IPAN 5 213*4882a593Smuzhiyun /* re-uses the VO FIFO, uCode will properly flush/schedule */ 214*4882a593Smuzhiyun #define IWL_TX_FIFO_AUX 5 215*4882a593Smuzhiyun #define IWL_TX_FIFO_UNUSED 255 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun #define IWLAGN_CMD_FIFO_NUM 7 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun /* 220*4882a593Smuzhiyun * This queue number is required for proper operation 221*4882a593Smuzhiyun * because the ucode will stop/start the scheduler as 222*4882a593Smuzhiyun * required. 223*4882a593Smuzhiyun */ 224*4882a593Smuzhiyun #define IWL_IPAN_MCAST_QUEUE 8 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun /****************************************************************************** 227*4882a593Smuzhiyun * (0) 228*4882a593Smuzhiyun * Commonly used structures and definitions: 229*4882a593Smuzhiyun * Command header, rate_n_flags, txpower 230*4882a593Smuzhiyun * 231*4882a593Smuzhiyun *****************************************************************************/ 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun /** 234*4882a593Smuzhiyun * iwlagn rate_n_flags bit fields 235*4882a593Smuzhiyun * 236*4882a593Smuzhiyun * rate_n_flags format is used in following iwlagn commands: 237*4882a593Smuzhiyun * REPLY_RX (response only) 238*4882a593Smuzhiyun * REPLY_RX_MPDU (response only) 239*4882a593Smuzhiyun * REPLY_TX (both command and response) 240*4882a593Smuzhiyun * REPLY_TX_LINK_QUALITY_CMD 241*4882a593Smuzhiyun * 242*4882a593Smuzhiyun * High-throughput (HT) rate format for bits 7:0 (bit 8 must be "1"): 243*4882a593Smuzhiyun * 2-0: 0) 6 Mbps 244*4882a593Smuzhiyun * 1) 12 Mbps 245*4882a593Smuzhiyun * 2) 18 Mbps 246*4882a593Smuzhiyun * 3) 24 Mbps 247*4882a593Smuzhiyun * 4) 36 Mbps 248*4882a593Smuzhiyun * 5) 48 Mbps 249*4882a593Smuzhiyun * 6) 54 Mbps 250*4882a593Smuzhiyun * 7) 60 Mbps 251*4882a593Smuzhiyun * 252*4882a593Smuzhiyun * 4-3: 0) Single stream (SISO) 253*4882a593Smuzhiyun * 1) Dual stream (MIMO) 254*4882a593Smuzhiyun * 2) Triple stream (MIMO) 255*4882a593Smuzhiyun * 256*4882a593Smuzhiyun * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 257*4882a593Smuzhiyun * 258*4882a593Smuzhiyun * Legacy OFDM rate format for bits 7:0 (bit 8 must be "0", bit 9 "0"): 259*4882a593Smuzhiyun * 3-0: 0xD) 6 Mbps 260*4882a593Smuzhiyun * 0xF) 9 Mbps 261*4882a593Smuzhiyun * 0x5) 12 Mbps 262*4882a593Smuzhiyun * 0x7) 18 Mbps 263*4882a593Smuzhiyun * 0x9) 24 Mbps 264*4882a593Smuzhiyun * 0xB) 36 Mbps 265*4882a593Smuzhiyun * 0x1) 48 Mbps 266*4882a593Smuzhiyun * 0x3) 54 Mbps 267*4882a593Smuzhiyun * 268*4882a593Smuzhiyun * Legacy CCK rate format for bits 7:0 (bit 8 must be "0", bit 9 "1"): 269*4882a593Smuzhiyun * 6-0: 10) 1 Mbps 270*4882a593Smuzhiyun * 20) 2 Mbps 271*4882a593Smuzhiyun * 55) 5.5 Mbps 272*4882a593Smuzhiyun * 110) 11 Mbps 273*4882a593Smuzhiyun */ 274*4882a593Smuzhiyun #define RATE_MCS_CODE_MSK 0x7 275*4882a593Smuzhiyun #define RATE_MCS_SPATIAL_POS 3 276*4882a593Smuzhiyun #define RATE_MCS_SPATIAL_MSK 0x18 277*4882a593Smuzhiyun #define RATE_MCS_HT_DUP_POS 5 278*4882a593Smuzhiyun #define RATE_MCS_HT_DUP_MSK 0x20 279*4882a593Smuzhiyun /* Both legacy and HT use bits 7:0 as the CCK/OFDM rate or HT MCS */ 280*4882a593Smuzhiyun #define RATE_MCS_RATE_MSK 0xff 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun /* Bit 8: (1) HT format, (0) legacy format in bits 7:0 */ 283*4882a593Smuzhiyun #define RATE_MCS_FLAGS_POS 8 284*4882a593Smuzhiyun #define RATE_MCS_HT_POS 8 285*4882a593Smuzhiyun #define RATE_MCS_HT_MSK 0x100 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 288*4882a593Smuzhiyun #define RATE_MCS_CCK_POS 9 289*4882a593Smuzhiyun #define RATE_MCS_CCK_MSK 0x200 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun /* Bit 10: (1) Use Green Field preamble */ 292*4882a593Smuzhiyun #define RATE_MCS_GF_POS 10 293*4882a593Smuzhiyun #define RATE_MCS_GF_MSK 0x400 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun /* Bit 11: (1) Use 40Mhz HT40 chnl width, (0) use 20 MHz legacy chnl width */ 296*4882a593Smuzhiyun #define RATE_MCS_HT40_POS 11 297*4882a593Smuzhiyun #define RATE_MCS_HT40_MSK 0x800 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun /* Bit 12: (1) Duplicate data on both 20MHz chnls. HT40 (bit 11) must be set. */ 300*4882a593Smuzhiyun #define RATE_MCS_DUP_POS 12 301*4882a593Smuzhiyun #define RATE_MCS_DUP_MSK 0x1000 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 304*4882a593Smuzhiyun #define RATE_MCS_SGI_POS 13 305*4882a593Smuzhiyun #define RATE_MCS_SGI_MSK 0x2000 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun /** 308*4882a593Smuzhiyun * rate_n_flags Tx antenna masks 309*4882a593Smuzhiyun * bit14:16 310*4882a593Smuzhiyun */ 311*4882a593Smuzhiyun #define RATE_MCS_ANT_POS 14 312*4882a593Smuzhiyun #define RATE_MCS_ANT_A_MSK 0x04000 313*4882a593Smuzhiyun #define RATE_MCS_ANT_B_MSK 0x08000 314*4882a593Smuzhiyun #define RATE_MCS_ANT_C_MSK 0x10000 315*4882a593Smuzhiyun #define RATE_MCS_ANT_AB_MSK (RATE_MCS_ANT_A_MSK | RATE_MCS_ANT_B_MSK) 316*4882a593Smuzhiyun #define RATE_MCS_ANT_ABC_MSK (RATE_MCS_ANT_AB_MSK | RATE_MCS_ANT_C_MSK) 317*4882a593Smuzhiyun #define RATE_ANT_NUM 3 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun #define POWER_TABLE_NUM_ENTRIES 33 320*4882a593Smuzhiyun #define POWER_TABLE_NUM_HT_OFDM_ENTRIES 32 321*4882a593Smuzhiyun #define POWER_TABLE_CCK_ENTRY 32 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun #define IWL_PWR_NUM_HT_OFDM_ENTRIES 24 324*4882a593Smuzhiyun #define IWL_PWR_CCK_ENTRIES 2 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun /** 327*4882a593Smuzhiyun * struct tx_power_dual_stream 328*4882a593Smuzhiyun * 329*4882a593Smuzhiyun * Table entries in REPLY_TX_PWR_TABLE_CMD, REPLY_CHANNEL_SWITCH 330*4882a593Smuzhiyun * 331*4882a593Smuzhiyun * Same format as iwl_tx_power_dual_stream, but __le32 332*4882a593Smuzhiyun */ 333*4882a593Smuzhiyun struct tx_power_dual_stream { 334*4882a593Smuzhiyun __le32 dw; 335*4882a593Smuzhiyun } __packed; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun /** 338*4882a593Smuzhiyun * Command REPLY_TX_POWER_DBM_CMD = 0x98 339*4882a593Smuzhiyun * struct iwlagn_tx_power_dbm_cmd 340*4882a593Smuzhiyun */ 341*4882a593Smuzhiyun #define IWLAGN_TX_POWER_AUTO 0x7f 342*4882a593Smuzhiyun #define IWLAGN_TX_POWER_NO_CLOSED (0x1 << 6) 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun struct iwlagn_tx_power_dbm_cmd { 345*4882a593Smuzhiyun s8 global_lmt; /*in half-dBm (e.g. 30 = 15 dBm) */ 346*4882a593Smuzhiyun u8 flags; 347*4882a593Smuzhiyun s8 srv_chan_lmt; /*in half-dBm (e.g. 30 = 15 dBm) */ 348*4882a593Smuzhiyun u8 reserved; 349*4882a593Smuzhiyun } __packed; 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun /** 352*4882a593Smuzhiyun * Command TX_ANT_CONFIGURATION_CMD = 0x98 353*4882a593Smuzhiyun * This command is used to configure valid Tx antenna. 354*4882a593Smuzhiyun * By default uCode concludes the valid antenna according to the radio flavor. 355*4882a593Smuzhiyun * This command enables the driver to override/modify this conclusion. 356*4882a593Smuzhiyun */ 357*4882a593Smuzhiyun struct iwl_tx_ant_config_cmd { 358*4882a593Smuzhiyun __le32 valid; 359*4882a593Smuzhiyun } __packed; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun /****************************************************************************** 362*4882a593Smuzhiyun * (0a) 363*4882a593Smuzhiyun * Alive and Error Commands & Responses: 364*4882a593Smuzhiyun * 365*4882a593Smuzhiyun *****************************************************************************/ 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun #define UCODE_VALID_OK cpu_to_le32(0x1) 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun /** 370*4882a593Smuzhiyun * REPLY_ALIVE = 0x1 (response only, not a command) 371*4882a593Smuzhiyun * 372*4882a593Smuzhiyun * uCode issues this "alive" notification once the runtime image is ready 373*4882a593Smuzhiyun * to receive commands from the driver. This is the *second* "alive" 374*4882a593Smuzhiyun * notification that the driver will receive after rebooting uCode; 375*4882a593Smuzhiyun * this "alive" is indicated by subtype field != 9. 376*4882a593Smuzhiyun * 377*4882a593Smuzhiyun * See comments documenting "BSM" (bootstrap state machine). 378*4882a593Smuzhiyun * 379*4882a593Smuzhiyun * This response includes two pointers to structures within the device's 380*4882a593Smuzhiyun * data SRAM (access via HBUS_TARG_MEM_* regs) that are useful for debugging: 381*4882a593Smuzhiyun * 382*4882a593Smuzhiyun * 1) log_event_table_ptr indicates base of the event log. This traces 383*4882a593Smuzhiyun * a 256-entry history of uCode execution within a circular buffer. 384*4882a593Smuzhiyun * Its header format is: 385*4882a593Smuzhiyun * 386*4882a593Smuzhiyun * __le32 log_size; log capacity (in number of entries) 387*4882a593Smuzhiyun * __le32 type; (1) timestamp with each entry, (0) no timestamp 388*4882a593Smuzhiyun * __le32 wraps; # times uCode has wrapped to top of circular buffer 389*4882a593Smuzhiyun * __le32 write_index; next circular buffer entry that uCode would fill 390*4882a593Smuzhiyun * 391*4882a593Smuzhiyun * The header is followed by the circular buffer of log entries. Entries 392*4882a593Smuzhiyun * with timestamps have the following format: 393*4882a593Smuzhiyun * 394*4882a593Smuzhiyun * __le32 event_id; range 0 - 1500 395*4882a593Smuzhiyun * __le32 timestamp; low 32 bits of TSF (of network, if associated) 396*4882a593Smuzhiyun * __le32 data; event_id-specific data value 397*4882a593Smuzhiyun * 398*4882a593Smuzhiyun * Entries without timestamps contain only event_id and data. 399*4882a593Smuzhiyun * 400*4882a593Smuzhiyun * 401*4882a593Smuzhiyun * 2) error_event_table_ptr indicates base of the error log. This contains 402*4882a593Smuzhiyun * information about any uCode error that occurs. For agn, the format 403*4882a593Smuzhiyun * of the error log is defined by struct iwl_error_event_table. 404*4882a593Smuzhiyun * 405*4882a593Smuzhiyun * The Linux driver can print both logs to the system log when a uCode error 406*4882a593Smuzhiyun * occurs. 407*4882a593Smuzhiyun */ 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun /* 410*4882a593Smuzhiyun * Note: This structure is read from the device with IO accesses, 411*4882a593Smuzhiyun * and the reading already does the endian conversion. As it is 412*4882a593Smuzhiyun * read with u32-sized accesses, any members with a different size 413*4882a593Smuzhiyun * need to be ordered correctly though! 414*4882a593Smuzhiyun */ 415*4882a593Smuzhiyun struct iwl_error_event_table { 416*4882a593Smuzhiyun u32 valid; /* (nonzero) valid, (0) log is empty */ 417*4882a593Smuzhiyun u32 error_id; /* type of error */ 418*4882a593Smuzhiyun u32 pc; /* program counter */ 419*4882a593Smuzhiyun u32 blink1; /* branch link */ 420*4882a593Smuzhiyun u32 blink2; /* branch link */ 421*4882a593Smuzhiyun u32 ilink1; /* interrupt link */ 422*4882a593Smuzhiyun u32 ilink2; /* interrupt link */ 423*4882a593Smuzhiyun u32 data1; /* error-specific data */ 424*4882a593Smuzhiyun u32 data2; /* error-specific data */ 425*4882a593Smuzhiyun u32 line; /* source code line of error */ 426*4882a593Smuzhiyun u32 bcon_time; /* beacon timer */ 427*4882a593Smuzhiyun u32 tsf_low; /* network timestamp function timer */ 428*4882a593Smuzhiyun u32 tsf_hi; /* network timestamp function timer */ 429*4882a593Smuzhiyun u32 gp1; /* GP1 timer register */ 430*4882a593Smuzhiyun u32 gp2; /* GP2 timer register */ 431*4882a593Smuzhiyun u32 gp3; /* GP3 timer register */ 432*4882a593Smuzhiyun u32 ucode_ver; /* uCode version */ 433*4882a593Smuzhiyun u32 hw_ver; /* HW Silicon version */ 434*4882a593Smuzhiyun u32 brd_ver; /* HW board version */ 435*4882a593Smuzhiyun u32 log_pc; /* log program counter */ 436*4882a593Smuzhiyun u32 frame_ptr; /* frame pointer */ 437*4882a593Smuzhiyun u32 stack_ptr; /* stack pointer */ 438*4882a593Smuzhiyun u32 hcmd; /* last host command header */ 439*4882a593Smuzhiyun u32 isr0; /* isr status register LMPM_NIC_ISR0: 440*4882a593Smuzhiyun * rxtx_flag */ 441*4882a593Smuzhiyun u32 isr1; /* isr status register LMPM_NIC_ISR1: 442*4882a593Smuzhiyun * host_flag */ 443*4882a593Smuzhiyun u32 isr2; /* isr status register LMPM_NIC_ISR2: 444*4882a593Smuzhiyun * enc_flag */ 445*4882a593Smuzhiyun u32 isr3; /* isr status register LMPM_NIC_ISR3: 446*4882a593Smuzhiyun * time_flag */ 447*4882a593Smuzhiyun u32 isr4; /* isr status register LMPM_NIC_ISR4: 448*4882a593Smuzhiyun * wico interrupt */ 449*4882a593Smuzhiyun u32 isr_pref; /* isr status register LMPM_NIC_PREF_STAT */ 450*4882a593Smuzhiyun u32 wait_event; /* wait event() caller address */ 451*4882a593Smuzhiyun u32 l2p_control; /* L2pControlField */ 452*4882a593Smuzhiyun u32 l2p_duration; /* L2pDurationField */ 453*4882a593Smuzhiyun u32 l2p_mhvalid; /* L2pMhValidBits */ 454*4882a593Smuzhiyun u32 l2p_addr_match; /* L2pAddrMatchStat */ 455*4882a593Smuzhiyun u32 lmpm_pmg_sel; /* indicate which clocks are turned on 456*4882a593Smuzhiyun * (LMPM_PMG_SEL) */ 457*4882a593Smuzhiyun u32 u_timestamp; /* indicate when the date and time of the 458*4882a593Smuzhiyun * compilation */ 459*4882a593Smuzhiyun u32 flow_handler; /* FH read/write pointers, RX credit */ 460*4882a593Smuzhiyun } __packed; 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun struct iwl_alive_resp { 463*4882a593Smuzhiyun u8 ucode_minor; 464*4882a593Smuzhiyun u8 ucode_major; 465*4882a593Smuzhiyun __le16 reserved1; 466*4882a593Smuzhiyun u8 sw_rev[8]; 467*4882a593Smuzhiyun u8 ver_type; 468*4882a593Smuzhiyun u8 ver_subtype; /* not "9" for runtime alive */ 469*4882a593Smuzhiyun __le16 reserved2; 470*4882a593Smuzhiyun __le32 log_event_table_ptr; /* SRAM address for event log */ 471*4882a593Smuzhiyun __le32 error_event_table_ptr; /* SRAM address for error log */ 472*4882a593Smuzhiyun __le32 timestamp; 473*4882a593Smuzhiyun __le32 is_valid; 474*4882a593Smuzhiyun } __packed; 475*4882a593Smuzhiyun 476*4882a593Smuzhiyun /* 477*4882a593Smuzhiyun * REPLY_ERROR = 0x2 (response only, not a command) 478*4882a593Smuzhiyun */ 479*4882a593Smuzhiyun struct iwl_error_resp { 480*4882a593Smuzhiyun __le32 error_type; 481*4882a593Smuzhiyun u8 cmd_id; 482*4882a593Smuzhiyun u8 reserved1; 483*4882a593Smuzhiyun __le16 bad_cmd_seq_num; 484*4882a593Smuzhiyun __le32 error_info; 485*4882a593Smuzhiyun __le64 timestamp; 486*4882a593Smuzhiyun } __packed; 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun /****************************************************************************** 489*4882a593Smuzhiyun * (1) 490*4882a593Smuzhiyun * RXON Commands & Responses: 491*4882a593Smuzhiyun * 492*4882a593Smuzhiyun *****************************************************************************/ 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun /* 495*4882a593Smuzhiyun * Rx config defines & structure 496*4882a593Smuzhiyun */ 497*4882a593Smuzhiyun /* rx_config device types */ 498*4882a593Smuzhiyun enum { 499*4882a593Smuzhiyun RXON_DEV_TYPE_AP = 1, 500*4882a593Smuzhiyun RXON_DEV_TYPE_ESS = 3, 501*4882a593Smuzhiyun RXON_DEV_TYPE_IBSS = 4, 502*4882a593Smuzhiyun RXON_DEV_TYPE_SNIFFER = 6, 503*4882a593Smuzhiyun RXON_DEV_TYPE_CP = 7, 504*4882a593Smuzhiyun RXON_DEV_TYPE_2STA = 8, 505*4882a593Smuzhiyun RXON_DEV_TYPE_P2P = 9, 506*4882a593Smuzhiyun }; 507*4882a593Smuzhiyun 508*4882a593Smuzhiyun 509*4882a593Smuzhiyun #define RXON_RX_CHAIN_DRIVER_FORCE_MSK cpu_to_le16(0x1 << 0) 510*4882a593Smuzhiyun #define RXON_RX_CHAIN_DRIVER_FORCE_POS (0) 511*4882a593Smuzhiyun #define RXON_RX_CHAIN_VALID_MSK cpu_to_le16(0x7 << 1) 512*4882a593Smuzhiyun #define RXON_RX_CHAIN_VALID_POS (1) 513*4882a593Smuzhiyun #define RXON_RX_CHAIN_FORCE_SEL_MSK cpu_to_le16(0x7 << 4) 514*4882a593Smuzhiyun #define RXON_RX_CHAIN_FORCE_SEL_POS (4) 515*4882a593Smuzhiyun #define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK cpu_to_le16(0x7 << 7) 516*4882a593Smuzhiyun #define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 517*4882a593Smuzhiyun #define RXON_RX_CHAIN_CNT_MSK cpu_to_le16(0x3 << 10) 518*4882a593Smuzhiyun #define RXON_RX_CHAIN_CNT_POS (10) 519*4882a593Smuzhiyun #define RXON_RX_CHAIN_MIMO_CNT_MSK cpu_to_le16(0x3 << 12) 520*4882a593Smuzhiyun #define RXON_RX_CHAIN_MIMO_CNT_POS (12) 521*4882a593Smuzhiyun #define RXON_RX_CHAIN_MIMO_FORCE_MSK cpu_to_le16(0x1 << 14) 522*4882a593Smuzhiyun #define RXON_RX_CHAIN_MIMO_FORCE_POS (14) 523*4882a593Smuzhiyun 524*4882a593Smuzhiyun /* rx_config flags */ 525*4882a593Smuzhiyun /* band & modulation selection */ 526*4882a593Smuzhiyun #define RXON_FLG_BAND_24G_MSK cpu_to_le32(1 << 0) 527*4882a593Smuzhiyun #define RXON_FLG_CCK_MSK cpu_to_le32(1 << 1) 528*4882a593Smuzhiyun /* auto detection enable */ 529*4882a593Smuzhiyun #define RXON_FLG_AUTO_DETECT_MSK cpu_to_le32(1 << 2) 530*4882a593Smuzhiyun /* TGg protection when tx */ 531*4882a593Smuzhiyun #define RXON_FLG_TGG_PROTECT_MSK cpu_to_le32(1 << 3) 532*4882a593Smuzhiyun /* cck short slot & preamble */ 533*4882a593Smuzhiyun #define RXON_FLG_SHORT_SLOT_MSK cpu_to_le32(1 << 4) 534*4882a593Smuzhiyun #define RXON_FLG_SHORT_PREAMBLE_MSK cpu_to_le32(1 << 5) 535*4882a593Smuzhiyun /* antenna selection */ 536*4882a593Smuzhiyun #define RXON_FLG_DIS_DIV_MSK cpu_to_le32(1 << 7) 537*4882a593Smuzhiyun #define RXON_FLG_ANT_SEL_MSK cpu_to_le32(0x0f00) 538*4882a593Smuzhiyun #define RXON_FLG_ANT_A_MSK cpu_to_le32(1 << 8) 539*4882a593Smuzhiyun #define RXON_FLG_ANT_B_MSK cpu_to_le32(1 << 9) 540*4882a593Smuzhiyun /* radar detection enable */ 541*4882a593Smuzhiyun #define RXON_FLG_RADAR_DETECT_MSK cpu_to_le32(1 << 12) 542*4882a593Smuzhiyun #define RXON_FLG_TGJ_NARROW_BAND_MSK cpu_to_le32(1 << 13) 543*4882a593Smuzhiyun /* rx response to host with 8-byte TSF 544*4882a593Smuzhiyun * (according to ON_AIR deassertion) */ 545*4882a593Smuzhiyun #define RXON_FLG_TSF2HOST_MSK cpu_to_le32(1 << 15) 546*4882a593Smuzhiyun 547*4882a593Smuzhiyun 548*4882a593Smuzhiyun /* HT flags */ 549*4882a593Smuzhiyun #define RXON_FLG_CTRL_CHANNEL_LOC_POS (22) 550*4882a593Smuzhiyun #define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK cpu_to_le32(0x1 << 22) 551*4882a593Smuzhiyun 552*4882a593Smuzhiyun #define RXON_FLG_HT_OPERATING_MODE_POS (23) 553*4882a593Smuzhiyun 554*4882a593Smuzhiyun #define RXON_FLG_HT_PROT_MSK cpu_to_le32(0x1 << 23) 555*4882a593Smuzhiyun #define RXON_FLG_HT40_PROT_MSK cpu_to_le32(0x2 << 23) 556*4882a593Smuzhiyun 557*4882a593Smuzhiyun #define RXON_FLG_CHANNEL_MODE_POS (25) 558*4882a593Smuzhiyun #define RXON_FLG_CHANNEL_MODE_MSK cpu_to_le32(0x3 << 25) 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun /* channel mode */ 561*4882a593Smuzhiyun enum { 562*4882a593Smuzhiyun CHANNEL_MODE_LEGACY = 0, 563*4882a593Smuzhiyun CHANNEL_MODE_PURE_40 = 1, 564*4882a593Smuzhiyun CHANNEL_MODE_MIXED = 2, 565*4882a593Smuzhiyun CHANNEL_MODE_RESERVED = 3, 566*4882a593Smuzhiyun }; 567*4882a593Smuzhiyun #define RXON_FLG_CHANNEL_MODE_LEGACY cpu_to_le32(CHANNEL_MODE_LEGACY << RXON_FLG_CHANNEL_MODE_POS) 568*4882a593Smuzhiyun #define RXON_FLG_CHANNEL_MODE_PURE_40 cpu_to_le32(CHANNEL_MODE_PURE_40 << RXON_FLG_CHANNEL_MODE_POS) 569*4882a593Smuzhiyun #define RXON_FLG_CHANNEL_MODE_MIXED cpu_to_le32(CHANNEL_MODE_MIXED << RXON_FLG_CHANNEL_MODE_POS) 570*4882a593Smuzhiyun 571*4882a593Smuzhiyun /* CTS to self (if spec allows) flag */ 572*4882a593Smuzhiyun #define RXON_FLG_SELF_CTS_EN cpu_to_le32(0x1<<30) 573*4882a593Smuzhiyun 574*4882a593Smuzhiyun /* rx_config filter flags */ 575*4882a593Smuzhiyun /* accept all data frames */ 576*4882a593Smuzhiyun #define RXON_FILTER_PROMISC_MSK cpu_to_le32(1 << 0) 577*4882a593Smuzhiyun /* pass control & management to host */ 578*4882a593Smuzhiyun #define RXON_FILTER_CTL2HOST_MSK cpu_to_le32(1 << 1) 579*4882a593Smuzhiyun /* accept multi-cast */ 580*4882a593Smuzhiyun #define RXON_FILTER_ACCEPT_GRP_MSK cpu_to_le32(1 << 2) 581*4882a593Smuzhiyun /* don't decrypt uni-cast frames */ 582*4882a593Smuzhiyun #define RXON_FILTER_DIS_DECRYPT_MSK cpu_to_le32(1 << 3) 583*4882a593Smuzhiyun /* don't decrypt multi-cast frames */ 584*4882a593Smuzhiyun #define RXON_FILTER_DIS_GRP_DECRYPT_MSK cpu_to_le32(1 << 4) 585*4882a593Smuzhiyun /* STA is associated */ 586*4882a593Smuzhiyun #define RXON_FILTER_ASSOC_MSK cpu_to_le32(1 << 5) 587*4882a593Smuzhiyun /* transfer to host non bssid beacons in associated state */ 588*4882a593Smuzhiyun #define RXON_FILTER_BCON_AWARE_MSK cpu_to_le32(1 << 6) 589*4882a593Smuzhiyun 590*4882a593Smuzhiyun /** 591*4882a593Smuzhiyun * REPLY_RXON = 0x10 (command, has simple generic response) 592*4882a593Smuzhiyun * 593*4882a593Smuzhiyun * RXON tunes the radio tuner to a service channel, and sets up a number 594*4882a593Smuzhiyun * of parameters that are used primarily for Rx, but also for Tx operations. 595*4882a593Smuzhiyun * 596*4882a593Smuzhiyun * NOTE: When tuning to a new channel, driver must set the 597*4882a593Smuzhiyun * RXON_FILTER_ASSOC_MSK to 0. This will clear station-dependent 598*4882a593Smuzhiyun * info within the device, including the station tables, tx retry 599*4882a593Smuzhiyun * rate tables, and txpower tables. Driver must build a new station 600*4882a593Smuzhiyun * table and txpower table before transmitting anything on the RXON 601*4882a593Smuzhiyun * channel. 602*4882a593Smuzhiyun * 603*4882a593Smuzhiyun * NOTE: All RXONs wipe clean the internal txpower table. Driver must 604*4882a593Smuzhiyun * issue a new REPLY_TX_PWR_TABLE_CMD after each REPLY_RXON (0x10), 605*4882a593Smuzhiyun * regardless of whether RXON_FILTER_ASSOC_MSK is set. 606*4882a593Smuzhiyun */ 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun struct iwl_rxon_cmd { 609*4882a593Smuzhiyun u8 node_addr[6]; 610*4882a593Smuzhiyun __le16 reserved1; 611*4882a593Smuzhiyun u8 bssid_addr[6]; 612*4882a593Smuzhiyun __le16 reserved2; 613*4882a593Smuzhiyun u8 wlap_bssid_addr[6]; 614*4882a593Smuzhiyun __le16 reserved3; 615*4882a593Smuzhiyun u8 dev_type; 616*4882a593Smuzhiyun u8 air_propagation; 617*4882a593Smuzhiyun __le16 rx_chain; 618*4882a593Smuzhiyun u8 ofdm_basic_rates; 619*4882a593Smuzhiyun u8 cck_basic_rates; 620*4882a593Smuzhiyun __le16 assoc_id; 621*4882a593Smuzhiyun __le32 flags; 622*4882a593Smuzhiyun __le32 filter_flags; 623*4882a593Smuzhiyun __le16 channel; 624*4882a593Smuzhiyun u8 ofdm_ht_single_stream_basic_rates; 625*4882a593Smuzhiyun u8 ofdm_ht_dual_stream_basic_rates; 626*4882a593Smuzhiyun u8 ofdm_ht_triple_stream_basic_rates; 627*4882a593Smuzhiyun u8 reserved5; 628*4882a593Smuzhiyun __le16 acquisition_data; 629*4882a593Smuzhiyun __le16 reserved6; 630*4882a593Smuzhiyun } __packed; 631*4882a593Smuzhiyun 632*4882a593Smuzhiyun /* 633*4882a593Smuzhiyun * REPLY_RXON_ASSOC = 0x11 (command, has simple generic response) 634*4882a593Smuzhiyun */ 635*4882a593Smuzhiyun struct iwl_rxon_assoc_cmd { 636*4882a593Smuzhiyun __le32 flags; 637*4882a593Smuzhiyun __le32 filter_flags; 638*4882a593Smuzhiyun u8 ofdm_basic_rates; 639*4882a593Smuzhiyun u8 cck_basic_rates; 640*4882a593Smuzhiyun __le16 reserved1; 641*4882a593Smuzhiyun u8 ofdm_ht_single_stream_basic_rates; 642*4882a593Smuzhiyun u8 ofdm_ht_dual_stream_basic_rates; 643*4882a593Smuzhiyun u8 ofdm_ht_triple_stream_basic_rates; 644*4882a593Smuzhiyun u8 reserved2; 645*4882a593Smuzhiyun __le16 rx_chain_select_flags; 646*4882a593Smuzhiyun __le16 acquisition_data; 647*4882a593Smuzhiyun __le32 reserved3; 648*4882a593Smuzhiyun } __packed; 649*4882a593Smuzhiyun 650*4882a593Smuzhiyun #define IWL_CONN_MAX_LISTEN_INTERVAL 10 651*4882a593Smuzhiyun #define IWL_MAX_UCODE_BEACON_INTERVAL 4 /* 4096 */ 652*4882a593Smuzhiyun 653*4882a593Smuzhiyun /* 654*4882a593Smuzhiyun * REPLY_RXON_TIMING = 0x14 (command, has simple generic response) 655*4882a593Smuzhiyun */ 656*4882a593Smuzhiyun struct iwl_rxon_time_cmd { 657*4882a593Smuzhiyun __le64 timestamp; 658*4882a593Smuzhiyun __le16 beacon_interval; 659*4882a593Smuzhiyun __le16 atim_window; 660*4882a593Smuzhiyun __le32 beacon_init_val; 661*4882a593Smuzhiyun __le16 listen_interval; 662*4882a593Smuzhiyun u8 dtim_period; 663*4882a593Smuzhiyun u8 delta_cp_bss_tbtts; 664*4882a593Smuzhiyun } __packed; 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun /* 667*4882a593Smuzhiyun * REPLY_CHANNEL_SWITCH = 0x72 (command, has simple generic response) 668*4882a593Smuzhiyun */ 669*4882a593Smuzhiyun /** 670*4882a593Smuzhiyun * struct iwl5000_channel_switch_cmd 671*4882a593Smuzhiyun * @band: 0- 5.2GHz, 1- 2.4GHz 672*4882a593Smuzhiyun * @expect_beacon: 0- resume transmits after channel switch 673*4882a593Smuzhiyun * 1- wait for beacon to resume transmits 674*4882a593Smuzhiyun * @channel: new channel number 675*4882a593Smuzhiyun * @rxon_flags: Rx on flags 676*4882a593Smuzhiyun * @rxon_filter_flags: filtering parameters 677*4882a593Smuzhiyun * @switch_time: switch time in extended beacon format 678*4882a593Smuzhiyun * @reserved: reserved bytes 679*4882a593Smuzhiyun */ 680*4882a593Smuzhiyun struct iwl5000_channel_switch_cmd { 681*4882a593Smuzhiyun u8 band; 682*4882a593Smuzhiyun u8 expect_beacon; 683*4882a593Smuzhiyun __le16 channel; 684*4882a593Smuzhiyun __le32 rxon_flags; 685*4882a593Smuzhiyun __le32 rxon_filter_flags; 686*4882a593Smuzhiyun __le32 switch_time; 687*4882a593Smuzhiyun __le32 reserved[2][IWL_PWR_NUM_HT_OFDM_ENTRIES + IWL_PWR_CCK_ENTRIES]; 688*4882a593Smuzhiyun } __packed; 689*4882a593Smuzhiyun 690*4882a593Smuzhiyun /** 691*4882a593Smuzhiyun * struct iwl6000_channel_switch_cmd 692*4882a593Smuzhiyun * @band: 0- 5.2GHz, 1- 2.4GHz 693*4882a593Smuzhiyun * @expect_beacon: 0- resume transmits after channel switch 694*4882a593Smuzhiyun * 1- wait for beacon to resume transmits 695*4882a593Smuzhiyun * @channel: new channel number 696*4882a593Smuzhiyun * @rxon_flags: Rx on flags 697*4882a593Smuzhiyun * @rxon_filter_flags: filtering parameters 698*4882a593Smuzhiyun * @switch_time: switch time in extended beacon format 699*4882a593Smuzhiyun * @reserved: reserved bytes 700*4882a593Smuzhiyun */ 701*4882a593Smuzhiyun struct iwl6000_channel_switch_cmd { 702*4882a593Smuzhiyun u8 band; 703*4882a593Smuzhiyun u8 expect_beacon; 704*4882a593Smuzhiyun __le16 channel; 705*4882a593Smuzhiyun __le32 rxon_flags; 706*4882a593Smuzhiyun __le32 rxon_filter_flags; 707*4882a593Smuzhiyun __le32 switch_time; 708*4882a593Smuzhiyun __le32 reserved[3][IWL_PWR_NUM_HT_OFDM_ENTRIES + IWL_PWR_CCK_ENTRIES]; 709*4882a593Smuzhiyun } __packed; 710*4882a593Smuzhiyun 711*4882a593Smuzhiyun /* 712*4882a593Smuzhiyun * CHANNEL_SWITCH_NOTIFICATION = 0x73 (notification only, not a command) 713*4882a593Smuzhiyun */ 714*4882a593Smuzhiyun struct iwl_csa_notification { 715*4882a593Smuzhiyun __le16 band; 716*4882a593Smuzhiyun __le16 channel; 717*4882a593Smuzhiyun __le32 status; /* 0 - OK, 1 - fail */ 718*4882a593Smuzhiyun } __packed; 719*4882a593Smuzhiyun 720*4882a593Smuzhiyun /****************************************************************************** 721*4882a593Smuzhiyun * (2) 722*4882a593Smuzhiyun * Quality-of-Service (QOS) Commands & Responses: 723*4882a593Smuzhiyun * 724*4882a593Smuzhiyun *****************************************************************************/ 725*4882a593Smuzhiyun 726*4882a593Smuzhiyun /** 727*4882a593Smuzhiyun * struct iwl_ac_qos -- QOS timing params for REPLY_QOS_PARAM 728*4882a593Smuzhiyun * One for each of 4 EDCA access categories in struct iwl_qosparam_cmd 729*4882a593Smuzhiyun * 730*4882a593Smuzhiyun * @cw_min: Contention window, start value in numbers of slots. 731*4882a593Smuzhiyun * Should be a power-of-2, minus 1. Device's default is 0x0f. 732*4882a593Smuzhiyun * @cw_max: Contention window, max value in numbers of slots. 733*4882a593Smuzhiyun * Should be a power-of-2, minus 1. Device's default is 0x3f. 734*4882a593Smuzhiyun * @aifsn: Number of slots in Arbitration Interframe Space (before 735*4882a593Smuzhiyun * performing random backoff timing prior to Tx). Device default 1. 736*4882a593Smuzhiyun * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 737*4882a593Smuzhiyun * 738*4882a593Smuzhiyun * Device will automatically increase contention window by (2*CW) + 1 for each 739*4882a593Smuzhiyun * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 740*4882a593Smuzhiyun * value, to cap the CW value. 741*4882a593Smuzhiyun */ 742*4882a593Smuzhiyun struct iwl_ac_qos { 743*4882a593Smuzhiyun __le16 cw_min; 744*4882a593Smuzhiyun __le16 cw_max; 745*4882a593Smuzhiyun u8 aifsn; 746*4882a593Smuzhiyun u8 reserved1; 747*4882a593Smuzhiyun __le16 edca_txop; 748*4882a593Smuzhiyun } __packed; 749*4882a593Smuzhiyun 750*4882a593Smuzhiyun /* QoS flags defines */ 751*4882a593Smuzhiyun #define QOS_PARAM_FLG_UPDATE_EDCA_MSK cpu_to_le32(0x01) 752*4882a593Smuzhiyun #define QOS_PARAM_FLG_TGN_MSK cpu_to_le32(0x02) 753*4882a593Smuzhiyun #define QOS_PARAM_FLG_TXOP_TYPE_MSK cpu_to_le32(0x10) 754*4882a593Smuzhiyun 755*4882a593Smuzhiyun /* Number of Access Categories (AC) (EDCA), queues 0..3 */ 756*4882a593Smuzhiyun #define AC_NUM 4 757*4882a593Smuzhiyun 758*4882a593Smuzhiyun /* 759*4882a593Smuzhiyun * REPLY_QOS_PARAM = 0x13 (command, has simple generic response) 760*4882a593Smuzhiyun * 761*4882a593Smuzhiyun * This command sets up timings for each of the 4 prioritized EDCA Tx FIFOs 762*4882a593Smuzhiyun * 0: Background, 1: Best Effort, 2: Video, 3: Voice. 763*4882a593Smuzhiyun */ 764*4882a593Smuzhiyun struct iwl_qosparam_cmd { 765*4882a593Smuzhiyun __le32 qos_flags; 766*4882a593Smuzhiyun struct iwl_ac_qos ac[AC_NUM]; 767*4882a593Smuzhiyun } __packed; 768*4882a593Smuzhiyun 769*4882a593Smuzhiyun /****************************************************************************** 770*4882a593Smuzhiyun * (3) 771*4882a593Smuzhiyun * Add/Modify Stations Commands & Responses: 772*4882a593Smuzhiyun * 773*4882a593Smuzhiyun *****************************************************************************/ 774*4882a593Smuzhiyun /* 775*4882a593Smuzhiyun * Multi station support 776*4882a593Smuzhiyun */ 777*4882a593Smuzhiyun 778*4882a593Smuzhiyun /* Special, dedicated locations within device's station table */ 779*4882a593Smuzhiyun #define IWL_AP_ID 0 780*4882a593Smuzhiyun #define IWL_AP_ID_PAN 1 781*4882a593Smuzhiyun #define IWL_STA_ID 2 782*4882a593Smuzhiyun #define IWLAGN_PAN_BCAST_ID 14 783*4882a593Smuzhiyun #define IWLAGN_BROADCAST_ID 15 784*4882a593Smuzhiyun #define IWLAGN_STATION_COUNT 16 785*4882a593Smuzhiyun 786*4882a593Smuzhiyun #define IWL_TID_NON_QOS IWL_MAX_TID_COUNT 787*4882a593Smuzhiyun 788*4882a593Smuzhiyun #define STA_FLG_TX_RATE_MSK cpu_to_le32(1 << 2) 789*4882a593Smuzhiyun #define STA_FLG_PWR_SAVE_MSK cpu_to_le32(1 << 8) 790*4882a593Smuzhiyun #define STA_FLG_PAN_STATION cpu_to_le32(1 << 13) 791*4882a593Smuzhiyun #define STA_FLG_RTS_MIMO_PROT_MSK cpu_to_le32(1 << 17) 792*4882a593Smuzhiyun #define STA_FLG_AGG_MPDU_8US_MSK cpu_to_le32(1 << 18) 793*4882a593Smuzhiyun #define STA_FLG_MAX_AGG_SIZE_POS (19) 794*4882a593Smuzhiyun #define STA_FLG_MAX_AGG_SIZE_MSK cpu_to_le32(3 << 19) 795*4882a593Smuzhiyun #define STA_FLG_HT40_EN_MSK cpu_to_le32(1 << 21) 796*4882a593Smuzhiyun #define STA_FLG_MIMO_DIS_MSK cpu_to_le32(1 << 22) 797*4882a593Smuzhiyun #define STA_FLG_AGG_MPDU_DENSITY_POS (23) 798*4882a593Smuzhiyun #define STA_FLG_AGG_MPDU_DENSITY_MSK cpu_to_le32(7 << 23) 799*4882a593Smuzhiyun 800*4882a593Smuzhiyun /* Use in mode field. 1: modify existing entry, 0: add new station entry */ 801*4882a593Smuzhiyun #define STA_CONTROL_MODIFY_MSK 0x01 802*4882a593Smuzhiyun 803*4882a593Smuzhiyun /* key flags __le16*/ 804*4882a593Smuzhiyun #define STA_KEY_FLG_ENCRYPT_MSK cpu_to_le16(0x0007) 805*4882a593Smuzhiyun #define STA_KEY_FLG_NO_ENC cpu_to_le16(0x0000) 806*4882a593Smuzhiyun #define STA_KEY_FLG_WEP cpu_to_le16(0x0001) 807*4882a593Smuzhiyun #define STA_KEY_FLG_CCMP cpu_to_le16(0x0002) 808*4882a593Smuzhiyun #define STA_KEY_FLG_TKIP cpu_to_le16(0x0003) 809*4882a593Smuzhiyun 810*4882a593Smuzhiyun #define STA_KEY_FLG_KEYID_POS 8 811*4882a593Smuzhiyun #define STA_KEY_FLG_INVALID cpu_to_le16(0x0800) 812*4882a593Smuzhiyun /* wep key is either from global key (0) or from station info array (1) */ 813*4882a593Smuzhiyun #define STA_KEY_FLG_MAP_KEY_MSK cpu_to_le16(0x0008) 814*4882a593Smuzhiyun 815*4882a593Smuzhiyun /* wep key in STA: 5-bytes (0) or 13-bytes (1) */ 816*4882a593Smuzhiyun #define STA_KEY_FLG_KEY_SIZE_MSK cpu_to_le16(0x1000) 817*4882a593Smuzhiyun #define STA_KEY_MULTICAST_MSK cpu_to_le16(0x4000) 818*4882a593Smuzhiyun #define STA_KEY_MAX_NUM 8 819*4882a593Smuzhiyun #define STA_KEY_MAX_NUM_PAN 16 820*4882a593Smuzhiyun /* must not match WEP_INVALID_OFFSET */ 821*4882a593Smuzhiyun #define IWLAGN_HW_KEY_DEFAULT 0xfe 822*4882a593Smuzhiyun 823*4882a593Smuzhiyun /* Flags indicate whether to modify vs. don't change various station params */ 824*4882a593Smuzhiyun #define STA_MODIFY_KEY_MASK 0x01 825*4882a593Smuzhiyun #define STA_MODIFY_TID_DISABLE_TX 0x02 826*4882a593Smuzhiyun #define STA_MODIFY_TX_RATE_MSK 0x04 827*4882a593Smuzhiyun #define STA_MODIFY_ADDBA_TID_MSK 0x08 828*4882a593Smuzhiyun #define STA_MODIFY_DELBA_TID_MSK 0x10 829*4882a593Smuzhiyun #define STA_MODIFY_SLEEP_TX_COUNT_MSK 0x20 830*4882a593Smuzhiyun 831*4882a593Smuzhiyun /* agn */ 832*4882a593Smuzhiyun struct iwl_keyinfo { 833*4882a593Smuzhiyun __le16 key_flags; 834*4882a593Smuzhiyun u8 tkip_rx_tsc_byte2; /* TSC[2] for key mix ph1 detection */ 835*4882a593Smuzhiyun u8 reserved1; 836*4882a593Smuzhiyun __le16 tkip_rx_ttak[5]; /* 10-byte unicast TKIP TTAK */ 837*4882a593Smuzhiyun u8 key_offset; 838*4882a593Smuzhiyun u8 reserved2; 839*4882a593Smuzhiyun u8 key[16]; /* 16-byte unicast decryption key */ 840*4882a593Smuzhiyun __le64 tx_secur_seq_cnt; 841*4882a593Smuzhiyun __le64 hw_tkip_mic_rx_key; 842*4882a593Smuzhiyun __le64 hw_tkip_mic_tx_key; 843*4882a593Smuzhiyun } __packed; 844*4882a593Smuzhiyun 845*4882a593Smuzhiyun /** 846*4882a593Smuzhiyun * struct sta_id_modify 847*4882a593Smuzhiyun * @addr[ETH_ALEN]: station's MAC address 848*4882a593Smuzhiyun * @sta_id: index of station in uCode's station table 849*4882a593Smuzhiyun * @modify_mask: STA_MODIFY_*, 1: modify, 0: don't change 850*4882a593Smuzhiyun * 851*4882a593Smuzhiyun * Driver selects unused table index when adding new station, 852*4882a593Smuzhiyun * or the index to a pre-existing station entry when modifying that station. 853*4882a593Smuzhiyun * Some indexes have special purposes (IWL_AP_ID, index 0, is for AP). 854*4882a593Smuzhiyun * 855*4882a593Smuzhiyun * modify_mask flags select which parameters to modify vs. leave alone. 856*4882a593Smuzhiyun */ 857*4882a593Smuzhiyun struct sta_id_modify { 858*4882a593Smuzhiyun u8 addr[ETH_ALEN]; 859*4882a593Smuzhiyun __le16 reserved1; 860*4882a593Smuzhiyun u8 sta_id; 861*4882a593Smuzhiyun u8 modify_mask; 862*4882a593Smuzhiyun __le16 reserved2; 863*4882a593Smuzhiyun } __packed; 864*4882a593Smuzhiyun 865*4882a593Smuzhiyun /* 866*4882a593Smuzhiyun * REPLY_ADD_STA = 0x18 (command) 867*4882a593Smuzhiyun * 868*4882a593Smuzhiyun * The device contains an internal table of per-station information, 869*4882a593Smuzhiyun * with info on security keys, aggregation parameters, and Tx rates for 870*4882a593Smuzhiyun * initial Tx attempt and any retries (agn devices uses 871*4882a593Smuzhiyun * REPLY_TX_LINK_QUALITY_CMD, 872*4882a593Smuzhiyun * 873*4882a593Smuzhiyun * REPLY_ADD_STA sets up the table entry for one station, either creating 874*4882a593Smuzhiyun * a new entry, or modifying a pre-existing one. 875*4882a593Smuzhiyun * 876*4882a593Smuzhiyun * NOTE: RXON command (without "associated" bit set) wipes the station table 877*4882a593Smuzhiyun * clean. Moving into RF_KILL state does this also. Driver must set up 878*4882a593Smuzhiyun * new station table before transmitting anything on the RXON channel 879*4882a593Smuzhiyun * (except active scans or active measurements; those commands carry 880*4882a593Smuzhiyun * their own txpower/rate setup data). 881*4882a593Smuzhiyun * 882*4882a593Smuzhiyun * When getting started on a new channel, driver must set up the 883*4882a593Smuzhiyun * IWL_BROADCAST_ID entry (last entry in the table). For a client 884*4882a593Smuzhiyun * station in a BSS, once an AP is selected, driver sets up the AP STA 885*4882a593Smuzhiyun * in the IWL_AP_ID entry (1st entry in the table). BROADCAST and AP 886*4882a593Smuzhiyun * are all that are needed for a BSS client station. If the device is 887*4882a593Smuzhiyun * used as AP, or in an IBSS network, driver must set up station table 888*4882a593Smuzhiyun * entries for all STAs in network, starting with index IWL_STA_ID. 889*4882a593Smuzhiyun */ 890*4882a593Smuzhiyun 891*4882a593Smuzhiyun struct iwl_addsta_cmd { 892*4882a593Smuzhiyun u8 mode; /* 1: modify existing, 0: add new station */ 893*4882a593Smuzhiyun u8 reserved[3]; 894*4882a593Smuzhiyun struct sta_id_modify sta; 895*4882a593Smuzhiyun struct iwl_keyinfo key; 896*4882a593Smuzhiyun __le32 station_flags; /* STA_FLG_* */ 897*4882a593Smuzhiyun __le32 station_flags_msk; /* STA_FLG_* */ 898*4882a593Smuzhiyun 899*4882a593Smuzhiyun /* bit field to disable (1) or enable (0) Tx for Traffic ID (TID) 900*4882a593Smuzhiyun * corresponding to bit (e.g. bit 5 controls TID 5). 901*4882a593Smuzhiyun * Set modify_mask bit STA_MODIFY_TID_DISABLE_TX to use this field. */ 902*4882a593Smuzhiyun __le16 tid_disable_tx; 903*4882a593Smuzhiyun __le16 legacy_reserved; 904*4882a593Smuzhiyun 905*4882a593Smuzhiyun /* TID for which to add block-ack support. 906*4882a593Smuzhiyun * Set modify_mask bit STA_MODIFY_ADDBA_TID_MSK to use this field. */ 907*4882a593Smuzhiyun u8 add_immediate_ba_tid; 908*4882a593Smuzhiyun 909*4882a593Smuzhiyun /* TID for which to remove block-ack support. 910*4882a593Smuzhiyun * Set modify_mask bit STA_MODIFY_DELBA_TID_MSK to use this field. */ 911*4882a593Smuzhiyun u8 remove_immediate_ba_tid; 912*4882a593Smuzhiyun 913*4882a593Smuzhiyun /* Starting Sequence Number for added block-ack support. 914*4882a593Smuzhiyun * Set modify_mask bit STA_MODIFY_ADDBA_TID_MSK to use this field. */ 915*4882a593Smuzhiyun __le16 add_immediate_ba_ssn; 916*4882a593Smuzhiyun 917*4882a593Smuzhiyun /* 918*4882a593Smuzhiyun * Number of packets OK to transmit to station even though 919*4882a593Smuzhiyun * it is asleep -- used to synchronise PS-poll and u-APSD 920*4882a593Smuzhiyun * responses while ucode keeps track of STA sleep state. 921*4882a593Smuzhiyun */ 922*4882a593Smuzhiyun __le16 sleep_tx_count; 923*4882a593Smuzhiyun 924*4882a593Smuzhiyun __le16 reserved2; 925*4882a593Smuzhiyun } __packed; 926*4882a593Smuzhiyun 927*4882a593Smuzhiyun 928*4882a593Smuzhiyun #define ADD_STA_SUCCESS_MSK 0x1 929*4882a593Smuzhiyun #define ADD_STA_NO_ROOM_IN_TABLE 0x2 930*4882a593Smuzhiyun #define ADD_STA_NO_BLOCK_ACK_RESOURCE 0x4 931*4882a593Smuzhiyun #define ADD_STA_MODIFY_NON_EXIST_STA 0x8 932*4882a593Smuzhiyun /* 933*4882a593Smuzhiyun * REPLY_ADD_STA = 0x18 (response) 934*4882a593Smuzhiyun */ 935*4882a593Smuzhiyun struct iwl_add_sta_resp { 936*4882a593Smuzhiyun u8 status; /* ADD_STA_* */ 937*4882a593Smuzhiyun } __packed; 938*4882a593Smuzhiyun 939*4882a593Smuzhiyun #define REM_STA_SUCCESS_MSK 0x1 940*4882a593Smuzhiyun /* 941*4882a593Smuzhiyun * REPLY_REM_STA = 0x19 (response) 942*4882a593Smuzhiyun */ 943*4882a593Smuzhiyun struct iwl_rem_sta_resp { 944*4882a593Smuzhiyun u8 status; 945*4882a593Smuzhiyun } __packed; 946*4882a593Smuzhiyun 947*4882a593Smuzhiyun /* 948*4882a593Smuzhiyun * REPLY_REM_STA = 0x19 (command) 949*4882a593Smuzhiyun */ 950*4882a593Smuzhiyun struct iwl_rem_sta_cmd { 951*4882a593Smuzhiyun u8 num_sta; /* number of removed stations */ 952*4882a593Smuzhiyun u8 reserved[3]; 953*4882a593Smuzhiyun u8 addr[ETH_ALEN]; /* MAC addr of the first station */ 954*4882a593Smuzhiyun u8 reserved2[2]; 955*4882a593Smuzhiyun } __packed; 956*4882a593Smuzhiyun 957*4882a593Smuzhiyun 958*4882a593Smuzhiyun /* WiFi queues mask */ 959*4882a593Smuzhiyun #define IWL_SCD_BK_MSK BIT(0) 960*4882a593Smuzhiyun #define IWL_SCD_BE_MSK BIT(1) 961*4882a593Smuzhiyun #define IWL_SCD_VI_MSK BIT(2) 962*4882a593Smuzhiyun #define IWL_SCD_VO_MSK BIT(3) 963*4882a593Smuzhiyun #define IWL_SCD_MGMT_MSK BIT(3) 964*4882a593Smuzhiyun 965*4882a593Smuzhiyun /* PAN queues mask */ 966*4882a593Smuzhiyun #define IWL_PAN_SCD_BK_MSK BIT(4) 967*4882a593Smuzhiyun #define IWL_PAN_SCD_BE_MSK BIT(5) 968*4882a593Smuzhiyun #define IWL_PAN_SCD_VI_MSK BIT(6) 969*4882a593Smuzhiyun #define IWL_PAN_SCD_VO_MSK BIT(7) 970*4882a593Smuzhiyun #define IWL_PAN_SCD_MGMT_MSK BIT(7) 971*4882a593Smuzhiyun #define IWL_PAN_SCD_MULTICAST_MSK BIT(8) 972*4882a593Smuzhiyun 973*4882a593Smuzhiyun #define IWL_AGG_TX_QUEUE_MSK 0xffc00 974*4882a593Smuzhiyun 975*4882a593Smuzhiyun #define IWL_DROP_ALL BIT(1) 976*4882a593Smuzhiyun 977*4882a593Smuzhiyun /* 978*4882a593Smuzhiyun * REPLY_TXFIFO_FLUSH = 0x1e(command and response) 979*4882a593Smuzhiyun * 980*4882a593Smuzhiyun * When using full FIFO flush this command checks the scheduler HW block WR/RD 981*4882a593Smuzhiyun * pointers to check if all the frames were transferred by DMA into the 982*4882a593Smuzhiyun * relevant TX FIFO queue. Only when the DMA is finished and the queue is 983*4882a593Smuzhiyun * empty the command can finish. 984*4882a593Smuzhiyun * This command is used to flush the TXFIFO from transmit commands, it may 985*4882a593Smuzhiyun * operate on single or multiple queues, the command queue can't be flushed by 986*4882a593Smuzhiyun * this command. The command response is returned when all the queue flush 987*4882a593Smuzhiyun * operations are done. Each TX command flushed return response with the FLUSH 988*4882a593Smuzhiyun * status set in the TX response status. When FIFO flush operation is used, 989*4882a593Smuzhiyun * the flush operation ends when both the scheduler DMA done and TXFIFO empty 990*4882a593Smuzhiyun * are set. 991*4882a593Smuzhiyun * 992*4882a593Smuzhiyun * @queue_control: bit mask for which queues to flush 993*4882a593Smuzhiyun * @flush_control: flush controls 994*4882a593Smuzhiyun * 0: Dump single MSDU 995*4882a593Smuzhiyun * 1: Dump multiple MSDU according to PS, INVALID STA, TTL, TID disable. 996*4882a593Smuzhiyun * 2: Dump all FIFO 997*4882a593Smuzhiyun */ 998*4882a593Smuzhiyun struct iwl_txfifo_flush_cmd_v3 { 999*4882a593Smuzhiyun __le32 queue_control; 1000*4882a593Smuzhiyun __le16 flush_control; 1001*4882a593Smuzhiyun __le16 reserved; 1002*4882a593Smuzhiyun } __packed; 1003*4882a593Smuzhiyun 1004*4882a593Smuzhiyun struct iwl_txfifo_flush_cmd_v2 { 1005*4882a593Smuzhiyun __le16 queue_control; 1006*4882a593Smuzhiyun __le16 flush_control; 1007*4882a593Smuzhiyun } __packed; 1008*4882a593Smuzhiyun 1009*4882a593Smuzhiyun /* 1010*4882a593Smuzhiyun * REPLY_WEP_KEY = 0x20 1011*4882a593Smuzhiyun */ 1012*4882a593Smuzhiyun struct iwl_wep_key { 1013*4882a593Smuzhiyun u8 key_index; 1014*4882a593Smuzhiyun u8 key_offset; 1015*4882a593Smuzhiyun u8 reserved1[2]; 1016*4882a593Smuzhiyun u8 key_size; 1017*4882a593Smuzhiyun u8 reserved2[3]; 1018*4882a593Smuzhiyun u8 key[16]; 1019*4882a593Smuzhiyun } __packed; 1020*4882a593Smuzhiyun 1021*4882a593Smuzhiyun struct iwl_wep_cmd { 1022*4882a593Smuzhiyun u8 num_keys; 1023*4882a593Smuzhiyun u8 global_key_type; 1024*4882a593Smuzhiyun u8 flags; 1025*4882a593Smuzhiyun u8 reserved; 1026*4882a593Smuzhiyun struct iwl_wep_key key[]; 1027*4882a593Smuzhiyun } __packed; 1028*4882a593Smuzhiyun 1029*4882a593Smuzhiyun #define WEP_KEY_WEP_TYPE 1 1030*4882a593Smuzhiyun #define WEP_KEYS_MAX 4 1031*4882a593Smuzhiyun #define WEP_INVALID_OFFSET 0xff 1032*4882a593Smuzhiyun #define WEP_KEY_LEN_64 5 1033*4882a593Smuzhiyun #define WEP_KEY_LEN_128 13 1034*4882a593Smuzhiyun 1035*4882a593Smuzhiyun /****************************************************************************** 1036*4882a593Smuzhiyun * (4) 1037*4882a593Smuzhiyun * Rx Responses: 1038*4882a593Smuzhiyun * 1039*4882a593Smuzhiyun *****************************************************************************/ 1040*4882a593Smuzhiyun 1041*4882a593Smuzhiyun #define RX_RES_STATUS_NO_CRC32_ERROR cpu_to_le32(1 << 0) 1042*4882a593Smuzhiyun #define RX_RES_STATUS_NO_RXE_OVERFLOW cpu_to_le32(1 << 1) 1043*4882a593Smuzhiyun 1044*4882a593Smuzhiyun #define RX_RES_PHY_FLAGS_BAND_24_MSK cpu_to_le16(1 << 0) 1045*4882a593Smuzhiyun #define RX_RES_PHY_FLAGS_MOD_CCK_MSK cpu_to_le16(1 << 1) 1046*4882a593Smuzhiyun #define RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK cpu_to_le16(1 << 2) 1047*4882a593Smuzhiyun #define RX_RES_PHY_FLAGS_NARROW_BAND_MSK cpu_to_le16(1 << 3) 1048*4882a593Smuzhiyun #define RX_RES_PHY_FLAGS_ANTENNA_MSK 0x70 1049*4882a593Smuzhiyun #define RX_RES_PHY_FLAGS_ANTENNA_POS 4 1050*4882a593Smuzhiyun #define RX_RES_PHY_FLAGS_AGG_MSK cpu_to_le16(1 << 7) 1051*4882a593Smuzhiyun 1052*4882a593Smuzhiyun #define RX_RES_STATUS_SEC_TYPE_MSK (0x7 << 8) 1053*4882a593Smuzhiyun #define RX_RES_STATUS_SEC_TYPE_NONE (0x0 << 8) 1054*4882a593Smuzhiyun #define RX_RES_STATUS_SEC_TYPE_WEP (0x1 << 8) 1055*4882a593Smuzhiyun #define RX_RES_STATUS_SEC_TYPE_CCMP (0x2 << 8) 1056*4882a593Smuzhiyun #define RX_RES_STATUS_SEC_TYPE_TKIP (0x3 << 8) 1057*4882a593Smuzhiyun #define RX_RES_STATUS_SEC_TYPE_ERR (0x7 << 8) 1058*4882a593Smuzhiyun 1059*4882a593Smuzhiyun #define RX_RES_STATUS_STATION_FOUND (1<<6) 1060*4882a593Smuzhiyun #define RX_RES_STATUS_NO_STATION_INFO_MISMATCH (1<<7) 1061*4882a593Smuzhiyun 1062*4882a593Smuzhiyun #define RX_RES_STATUS_DECRYPT_TYPE_MSK (0x3 << 11) 1063*4882a593Smuzhiyun #define RX_RES_STATUS_NOT_DECRYPT (0x0 << 11) 1064*4882a593Smuzhiyun #define RX_RES_STATUS_DECRYPT_OK (0x3 << 11) 1065*4882a593Smuzhiyun #define RX_RES_STATUS_BAD_ICV_MIC (0x1 << 11) 1066*4882a593Smuzhiyun #define RX_RES_STATUS_BAD_KEY_TTAK (0x2 << 11) 1067*4882a593Smuzhiyun 1068*4882a593Smuzhiyun #define RX_MPDU_RES_STATUS_ICV_OK (0x20) 1069*4882a593Smuzhiyun #define RX_MPDU_RES_STATUS_MIC_OK (0x40) 1070*4882a593Smuzhiyun #define RX_MPDU_RES_STATUS_TTAK_OK (1 << 7) 1071*4882a593Smuzhiyun #define RX_MPDU_RES_STATUS_DEC_DONE_MSK (0x800) 1072*4882a593Smuzhiyun 1073*4882a593Smuzhiyun 1074*4882a593Smuzhiyun #define IWLAGN_RX_RES_PHY_CNT 8 1075*4882a593Smuzhiyun #define IWLAGN_RX_RES_AGC_IDX 1 1076*4882a593Smuzhiyun #define IWLAGN_RX_RES_RSSI_AB_IDX 2 1077*4882a593Smuzhiyun #define IWLAGN_RX_RES_RSSI_C_IDX 3 1078*4882a593Smuzhiyun #define IWLAGN_OFDM_AGC_MSK 0xfe00 1079*4882a593Smuzhiyun #define IWLAGN_OFDM_AGC_BIT_POS 9 1080*4882a593Smuzhiyun #define IWLAGN_OFDM_RSSI_INBAND_A_BITMSK 0x00ff 1081*4882a593Smuzhiyun #define IWLAGN_OFDM_RSSI_ALLBAND_A_BITMSK 0xff00 1082*4882a593Smuzhiyun #define IWLAGN_OFDM_RSSI_A_BIT_POS 0 1083*4882a593Smuzhiyun #define IWLAGN_OFDM_RSSI_INBAND_B_BITMSK 0xff0000 1084*4882a593Smuzhiyun #define IWLAGN_OFDM_RSSI_ALLBAND_B_BITMSK 0xff000000 1085*4882a593Smuzhiyun #define IWLAGN_OFDM_RSSI_B_BIT_POS 16 1086*4882a593Smuzhiyun #define IWLAGN_OFDM_RSSI_INBAND_C_BITMSK 0x00ff 1087*4882a593Smuzhiyun #define IWLAGN_OFDM_RSSI_ALLBAND_C_BITMSK 0xff00 1088*4882a593Smuzhiyun #define IWLAGN_OFDM_RSSI_C_BIT_POS 0 1089*4882a593Smuzhiyun 1090*4882a593Smuzhiyun struct iwlagn_non_cfg_phy { 1091*4882a593Smuzhiyun __le32 non_cfg_phy[IWLAGN_RX_RES_PHY_CNT]; /* up to 8 phy entries */ 1092*4882a593Smuzhiyun } __packed; 1093*4882a593Smuzhiyun 1094*4882a593Smuzhiyun 1095*4882a593Smuzhiyun /* 1096*4882a593Smuzhiyun * REPLY_RX = 0xc3 (response only, not a command) 1097*4882a593Smuzhiyun * Used only for legacy (non 11n) frames. 1098*4882a593Smuzhiyun */ 1099*4882a593Smuzhiyun struct iwl_rx_phy_res { 1100*4882a593Smuzhiyun u8 non_cfg_phy_cnt; /* non configurable DSP phy data byte count */ 1101*4882a593Smuzhiyun u8 cfg_phy_cnt; /* configurable DSP phy data byte count */ 1102*4882a593Smuzhiyun u8 stat_id; /* configurable DSP phy data set ID */ 1103*4882a593Smuzhiyun u8 reserved1; 1104*4882a593Smuzhiyun __le64 timestamp; /* TSF at on air rise */ 1105*4882a593Smuzhiyun __le32 beacon_time_stamp; /* beacon at on-air rise */ 1106*4882a593Smuzhiyun __le16 phy_flags; /* general phy flags: band, modulation, ... */ 1107*4882a593Smuzhiyun __le16 channel; /* channel number */ 1108*4882a593Smuzhiyun u8 non_cfg_phy_buf[32]; /* for various implementations of non_cfg_phy */ 1109*4882a593Smuzhiyun __le32 rate_n_flags; /* RATE_MCS_* */ 1110*4882a593Smuzhiyun __le16 byte_count; /* frame's byte-count */ 1111*4882a593Smuzhiyun __le16 frame_time; /* frame's time on the air */ 1112*4882a593Smuzhiyun } __packed; 1113*4882a593Smuzhiyun 1114*4882a593Smuzhiyun struct iwl_rx_mpdu_res_start { 1115*4882a593Smuzhiyun __le16 byte_count; 1116*4882a593Smuzhiyun __le16 reserved; 1117*4882a593Smuzhiyun } __packed; 1118*4882a593Smuzhiyun 1119*4882a593Smuzhiyun 1120*4882a593Smuzhiyun /****************************************************************************** 1121*4882a593Smuzhiyun * (5) 1122*4882a593Smuzhiyun * Tx Commands & Responses: 1123*4882a593Smuzhiyun * 1124*4882a593Smuzhiyun * Driver must place each REPLY_TX command into one of the prioritized Tx 1125*4882a593Smuzhiyun * queues in host DRAM, shared between driver and device (see comments for 1126*4882a593Smuzhiyun * SCD registers and Tx/Rx Queues). When the device's Tx scheduler and uCode 1127*4882a593Smuzhiyun * are preparing to transmit, the device pulls the Tx command over the PCI 1128*4882a593Smuzhiyun * bus via one of the device's Tx DMA channels, to fill an internal FIFO 1129*4882a593Smuzhiyun * from which data will be transmitted. 1130*4882a593Smuzhiyun * 1131*4882a593Smuzhiyun * uCode handles all timing and protocol related to control frames 1132*4882a593Smuzhiyun * (RTS/CTS/ACK), based on flags in the Tx command. uCode and Tx scheduler 1133*4882a593Smuzhiyun * handle reception of block-acks; uCode updates the host driver via 1134*4882a593Smuzhiyun * REPLY_COMPRESSED_BA. 1135*4882a593Smuzhiyun * 1136*4882a593Smuzhiyun * uCode handles retrying Tx when an ACK is expected but not received. 1137*4882a593Smuzhiyun * This includes trying lower data rates than the one requested in the Tx 1138*4882a593Smuzhiyun * command, as set up by the REPLY_TX_LINK_QUALITY_CMD (agn). 1139*4882a593Smuzhiyun * 1140*4882a593Smuzhiyun * Driver sets up transmit power for various rates via REPLY_TX_PWR_TABLE_CMD. 1141*4882a593Smuzhiyun * This command must be executed after every RXON command, before Tx can occur. 1142*4882a593Smuzhiyun *****************************************************************************/ 1143*4882a593Smuzhiyun 1144*4882a593Smuzhiyun /* REPLY_TX Tx flags field */ 1145*4882a593Smuzhiyun 1146*4882a593Smuzhiyun /* 1147*4882a593Smuzhiyun * 1: Use RTS/CTS protocol or CTS-to-self if spec allows it 1148*4882a593Smuzhiyun * before this frame. if CTS-to-self required check 1149*4882a593Smuzhiyun * RXON_FLG_SELF_CTS_EN status. 1150*4882a593Smuzhiyun */ 1151*4882a593Smuzhiyun #define TX_CMD_FLG_PROT_REQUIRE_MSK cpu_to_le32(1 << 0) 1152*4882a593Smuzhiyun 1153*4882a593Smuzhiyun /* 1: Expect ACK from receiving station 1154*4882a593Smuzhiyun * 0: Don't expect ACK (MAC header's duration field s/b 0) 1155*4882a593Smuzhiyun * Set this for unicast frames, but not broadcast/multicast. */ 1156*4882a593Smuzhiyun #define TX_CMD_FLG_ACK_MSK cpu_to_le32(1 << 3) 1157*4882a593Smuzhiyun 1158*4882a593Smuzhiyun /* For agn devices: 1159*4882a593Smuzhiyun * 1: Use rate scale table (see REPLY_TX_LINK_QUALITY_CMD). 1160*4882a593Smuzhiyun * Tx command's initial_rate_index indicates first rate to try; 1161*4882a593Smuzhiyun * uCode walks through table for additional Tx attempts. 1162*4882a593Smuzhiyun * 0: Use Tx rate/MCS from Tx command's rate_n_flags field. 1163*4882a593Smuzhiyun * This rate will be used for all Tx attempts; it will not be scaled. */ 1164*4882a593Smuzhiyun #define TX_CMD_FLG_STA_RATE_MSK cpu_to_le32(1 << 4) 1165*4882a593Smuzhiyun 1166*4882a593Smuzhiyun /* 1: Expect immediate block-ack. 1167*4882a593Smuzhiyun * Set when Txing a block-ack request frame. Also set TX_CMD_FLG_ACK_MSK. */ 1168*4882a593Smuzhiyun #define TX_CMD_FLG_IMM_BA_RSP_MASK cpu_to_le32(1 << 6) 1169*4882a593Smuzhiyun 1170*4882a593Smuzhiyun /* Tx antenna selection field; reserved (0) for agn devices. */ 1171*4882a593Smuzhiyun #define TX_CMD_FLG_ANT_SEL_MSK cpu_to_le32(0xf00) 1172*4882a593Smuzhiyun 1173*4882a593Smuzhiyun /* 1: Ignore Bluetooth priority for this frame. 1174*4882a593Smuzhiyun * 0: Delay Tx until Bluetooth device is done (normal usage). */ 1175*4882a593Smuzhiyun #define TX_CMD_FLG_IGNORE_BT cpu_to_le32(1 << 12) 1176*4882a593Smuzhiyun 1177*4882a593Smuzhiyun /* 1: uCode overrides sequence control field in MAC header. 1178*4882a593Smuzhiyun * 0: Driver provides sequence control field in MAC header. 1179*4882a593Smuzhiyun * Set this for management frames, non-QOS data frames, non-unicast frames, 1180*4882a593Smuzhiyun * and also in Tx command embedded in REPLY_SCAN_CMD for active scans. */ 1181*4882a593Smuzhiyun #define TX_CMD_FLG_SEQ_CTL_MSK cpu_to_le32(1 << 13) 1182*4882a593Smuzhiyun 1183*4882a593Smuzhiyun /* 1: This frame is non-last MPDU; more fragments are coming. 1184*4882a593Smuzhiyun * 0: Last fragment, or not using fragmentation. */ 1185*4882a593Smuzhiyun #define TX_CMD_FLG_MORE_FRAG_MSK cpu_to_le32(1 << 14) 1186*4882a593Smuzhiyun 1187*4882a593Smuzhiyun /* 1: uCode calculates and inserts Timestamp Function (TSF) in outgoing frame. 1188*4882a593Smuzhiyun * 0: No TSF required in outgoing frame. 1189*4882a593Smuzhiyun * Set this for transmitting beacons and probe responses. */ 1190*4882a593Smuzhiyun #define TX_CMD_FLG_TSF_MSK cpu_to_le32(1 << 16) 1191*4882a593Smuzhiyun 1192*4882a593Smuzhiyun /* 1: Driver inserted 2 bytes pad after the MAC header, for (required) dword 1193*4882a593Smuzhiyun * alignment of frame's payload data field. 1194*4882a593Smuzhiyun * 0: No pad 1195*4882a593Smuzhiyun * Set this for MAC headers with 26 or 30 bytes, i.e. those with QOS or ADDR4 1196*4882a593Smuzhiyun * field (but not both). Driver must align frame data (i.e. data following 1197*4882a593Smuzhiyun * MAC header) to DWORD boundary. */ 1198*4882a593Smuzhiyun #define TX_CMD_FLG_MH_PAD_MSK cpu_to_le32(1 << 20) 1199*4882a593Smuzhiyun 1200*4882a593Smuzhiyun /* accelerate aggregation support 1201*4882a593Smuzhiyun * 0 - no CCMP encryption; 1 - CCMP encryption */ 1202*4882a593Smuzhiyun #define TX_CMD_FLG_AGG_CCMP_MSK cpu_to_le32(1 << 22) 1203*4882a593Smuzhiyun 1204*4882a593Smuzhiyun /* HCCA-AP - disable duration overwriting. */ 1205*4882a593Smuzhiyun #define TX_CMD_FLG_DUR_MSK cpu_to_le32(1 << 25) 1206*4882a593Smuzhiyun 1207*4882a593Smuzhiyun 1208*4882a593Smuzhiyun /* 1209*4882a593Smuzhiyun * TX command security control 1210*4882a593Smuzhiyun */ 1211*4882a593Smuzhiyun #define TX_CMD_SEC_WEP 0x01 1212*4882a593Smuzhiyun #define TX_CMD_SEC_CCM 0x02 1213*4882a593Smuzhiyun #define TX_CMD_SEC_TKIP 0x03 1214*4882a593Smuzhiyun #define TX_CMD_SEC_MSK 0x03 1215*4882a593Smuzhiyun #define TX_CMD_SEC_SHIFT 6 1216*4882a593Smuzhiyun #define TX_CMD_SEC_KEY128 0x08 1217*4882a593Smuzhiyun 1218*4882a593Smuzhiyun /* 1219*4882a593Smuzhiyun * REPLY_TX = 0x1c (command) 1220*4882a593Smuzhiyun */ 1221*4882a593Smuzhiyun 1222*4882a593Smuzhiyun /* 1223*4882a593Smuzhiyun * Used for managing Tx retries when expecting block-acks. 1224*4882a593Smuzhiyun * Driver should set these fields to 0. 1225*4882a593Smuzhiyun */ 1226*4882a593Smuzhiyun struct iwl_dram_scratch { 1227*4882a593Smuzhiyun u8 try_cnt; /* Tx attempts */ 1228*4882a593Smuzhiyun u8 bt_kill_cnt; /* Tx attempts blocked by Bluetooth device */ 1229*4882a593Smuzhiyun __le16 reserved; 1230*4882a593Smuzhiyun } __packed; 1231*4882a593Smuzhiyun 1232*4882a593Smuzhiyun struct iwl_tx_cmd { 1233*4882a593Smuzhiyun /* 1234*4882a593Smuzhiyun * MPDU byte count: 1235*4882a593Smuzhiyun * MAC header (24/26/30/32 bytes) + 2 bytes pad if 26/30 header size, 1236*4882a593Smuzhiyun * + 8 byte IV for CCM or TKIP (not used for WEP) 1237*4882a593Smuzhiyun * + Data payload 1238*4882a593Smuzhiyun * + 8-byte MIC (not used for CCM/WEP) 1239*4882a593Smuzhiyun * NOTE: Does not include Tx command bytes, post-MAC pad bytes, 1240*4882a593Smuzhiyun * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes.i 1241*4882a593Smuzhiyun * Range: 14-2342 bytes. 1242*4882a593Smuzhiyun */ 1243*4882a593Smuzhiyun __le16 len; 1244*4882a593Smuzhiyun 1245*4882a593Smuzhiyun /* 1246*4882a593Smuzhiyun * MPDU or MSDU byte count for next frame. 1247*4882a593Smuzhiyun * Used for fragmentation and bursting, but not 11n aggregation. 1248*4882a593Smuzhiyun * Same as "len", but for next frame. Set to 0 if not applicable. 1249*4882a593Smuzhiyun */ 1250*4882a593Smuzhiyun __le16 next_frame_len; 1251*4882a593Smuzhiyun 1252*4882a593Smuzhiyun __le32 tx_flags; /* TX_CMD_FLG_* */ 1253*4882a593Smuzhiyun 1254*4882a593Smuzhiyun /* uCode may modify this field of the Tx command (in host DRAM!). 1255*4882a593Smuzhiyun * Driver must also set dram_lsb_ptr and dram_msb_ptr in this cmd. */ 1256*4882a593Smuzhiyun struct iwl_dram_scratch scratch; 1257*4882a593Smuzhiyun 1258*4882a593Smuzhiyun /* Rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is cleared. */ 1259*4882a593Smuzhiyun __le32 rate_n_flags; /* RATE_MCS_* */ 1260*4882a593Smuzhiyun 1261*4882a593Smuzhiyun /* Index of destination station in uCode's station table */ 1262*4882a593Smuzhiyun u8 sta_id; 1263*4882a593Smuzhiyun 1264*4882a593Smuzhiyun /* Type of security encryption: CCM or TKIP */ 1265*4882a593Smuzhiyun u8 sec_ctl; /* TX_CMD_SEC_* */ 1266*4882a593Smuzhiyun 1267*4882a593Smuzhiyun /* 1268*4882a593Smuzhiyun * Index into rate table (see REPLY_TX_LINK_QUALITY_CMD) for initial 1269*4882a593Smuzhiyun * Tx attempt, if TX_CMD_FLG_STA_RATE_MSK is set. Normally "0" for 1270*4882a593Smuzhiyun * data frames, this field may be used to selectively reduce initial 1271*4882a593Smuzhiyun * rate (via non-0 value) for special frames (e.g. management), while 1272*4882a593Smuzhiyun * still supporting rate scaling for all frames. 1273*4882a593Smuzhiyun */ 1274*4882a593Smuzhiyun u8 initial_rate_index; 1275*4882a593Smuzhiyun u8 reserved; 1276*4882a593Smuzhiyun u8 key[16]; 1277*4882a593Smuzhiyun __le16 next_frame_flags; 1278*4882a593Smuzhiyun __le16 reserved2; 1279*4882a593Smuzhiyun union { 1280*4882a593Smuzhiyun __le32 life_time; 1281*4882a593Smuzhiyun __le32 attempt; 1282*4882a593Smuzhiyun } stop_time; 1283*4882a593Smuzhiyun 1284*4882a593Smuzhiyun /* Host DRAM physical address pointer to "scratch" in this command. 1285*4882a593Smuzhiyun * Must be dword aligned. "0" in dram_lsb_ptr disables usage. */ 1286*4882a593Smuzhiyun __le32 dram_lsb_ptr; 1287*4882a593Smuzhiyun u8 dram_msb_ptr; 1288*4882a593Smuzhiyun 1289*4882a593Smuzhiyun u8 rts_retry_limit; /*byte 50 */ 1290*4882a593Smuzhiyun u8 data_retry_limit; /*byte 51 */ 1291*4882a593Smuzhiyun u8 tid_tspec; 1292*4882a593Smuzhiyun union { 1293*4882a593Smuzhiyun __le16 pm_frame_timeout; 1294*4882a593Smuzhiyun __le16 attempt_duration; 1295*4882a593Smuzhiyun } timeout; 1296*4882a593Smuzhiyun 1297*4882a593Smuzhiyun /* 1298*4882a593Smuzhiyun * Duration of EDCA burst Tx Opportunity, in 32-usec units. 1299*4882a593Smuzhiyun * Set this if txop time is not specified by HCCA protocol (e.g. by AP). 1300*4882a593Smuzhiyun */ 1301*4882a593Smuzhiyun __le16 driver_txop; 1302*4882a593Smuzhiyun 1303*4882a593Smuzhiyun /* 1304*4882a593Smuzhiyun * MAC header goes here, followed by 2 bytes padding if MAC header 1305*4882a593Smuzhiyun * length is 26 or 30 bytes, followed by payload data 1306*4882a593Smuzhiyun */ 1307*4882a593Smuzhiyun u8 payload[0]; 1308*4882a593Smuzhiyun struct ieee80211_hdr hdr[]; 1309*4882a593Smuzhiyun } __packed; 1310*4882a593Smuzhiyun 1311*4882a593Smuzhiyun /* 1312*4882a593Smuzhiyun * TX command response is sent after *agn* transmission attempts. 1313*4882a593Smuzhiyun * 1314*4882a593Smuzhiyun * both postpone and abort status are expected behavior from uCode. there is 1315*4882a593Smuzhiyun * no special operation required from driver; except for RFKILL_FLUSH, 1316*4882a593Smuzhiyun * which required tx flush host command to flush all the tx frames in queues 1317*4882a593Smuzhiyun */ 1318*4882a593Smuzhiyun enum { 1319*4882a593Smuzhiyun TX_STATUS_SUCCESS = 0x01, 1320*4882a593Smuzhiyun TX_STATUS_DIRECT_DONE = 0x02, 1321*4882a593Smuzhiyun /* postpone TX */ 1322*4882a593Smuzhiyun TX_STATUS_POSTPONE_DELAY = 0x40, 1323*4882a593Smuzhiyun TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 1324*4882a593Smuzhiyun TX_STATUS_POSTPONE_BT_PRIO = 0x42, 1325*4882a593Smuzhiyun TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 1326*4882a593Smuzhiyun TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 1327*4882a593Smuzhiyun /* abort TX */ 1328*4882a593Smuzhiyun TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 1329*4882a593Smuzhiyun TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 1330*4882a593Smuzhiyun TX_STATUS_FAIL_LONG_LIMIT = 0x83, 1331*4882a593Smuzhiyun TX_STATUS_FAIL_FIFO_UNDERRUN = 0x84, 1332*4882a593Smuzhiyun TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 1333*4882a593Smuzhiyun TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 1334*4882a593Smuzhiyun TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 1335*4882a593Smuzhiyun TX_STATUS_FAIL_DEST_PS = 0x88, 1336*4882a593Smuzhiyun TX_STATUS_FAIL_HOST_ABORTED = 0x89, 1337*4882a593Smuzhiyun TX_STATUS_FAIL_BT_RETRY = 0x8a, 1338*4882a593Smuzhiyun TX_STATUS_FAIL_STA_INVALID = 0x8b, 1339*4882a593Smuzhiyun TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 1340*4882a593Smuzhiyun TX_STATUS_FAIL_TID_DISABLE = 0x8d, 1341*4882a593Smuzhiyun TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 1342*4882a593Smuzhiyun TX_STATUS_FAIL_INSUFFICIENT_CF_POLL = 0x8f, 1343*4882a593Smuzhiyun TX_STATUS_FAIL_PASSIVE_NO_RX = 0x90, 1344*4882a593Smuzhiyun TX_STATUS_FAIL_NO_BEACON_ON_RADAR = 0x91, 1345*4882a593Smuzhiyun }; 1346*4882a593Smuzhiyun 1347*4882a593Smuzhiyun #define TX_PACKET_MODE_REGULAR 0x0000 1348*4882a593Smuzhiyun #define TX_PACKET_MODE_BURST_SEQ 0x0100 1349*4882a593Smuzhiyun #define TX_PACKET_MODE_BURST_FIRST 0x0200 1350*4882a593Smuzhiyun 1351*4882a593Smuzhiyun enum { 1352*4882a593Smuzhiyun TX_POWER_PA_NOT_ACTIVE = 0x0, 1353*4882a593Smuzhiyun }; 1354*4882a593Smuzhiyun 1355*4882a593Smuzhiyun enum { 1356*4882a593Smuzhiyun TX_STATUS_MSK = 0x000000ff, /* bits 0:7 */ 1357*4882a593Smuzhiyun TX_STATUS_DELAY_MSK = 0x00000040, 1358*4882a593Smuzhiyun TX_STATUS_ABORT_MSK = 0x00000080, 1359*4882a593Smuzhiyun TX_PACKET_MODE_MSK = 0x0000ff00, /* bits 8:15 */ 1360*4882a593Smuzhiyun TX_FIFO_NUMBER_MSK = 0x00070000, /* bits 16:18 */ 1361*4882a593Smuzhiyun TX_RESERVED = 0x00780000, /* bits 19:22 */ 1362*4882a593Smuzhiyun TX_POWER_PA_DETECT_MSK = 0x7f800000, /* bits 23:30 */ 1363*4882a593Smuzhiyun TX_ABORT_REQUIRED_MSK = 0x80000000, /* bits 31:31 */ 1364*4882a593Smuzhiyun }; 1365*4882a593Smuzhiyun 1366*4882a593Smuzhiyun /* ******************************* 1367*4882a593Smuzhiyun * TX aggregation status 1368*4882a593Smuzhiyun ******************************* */ 1369*4882a593Smuzhiyun 1370*4882a593Smuzhiyun enum { 1371*4882a593Smuzhiyun AGG_TX_STATE_TRANSMITTED = 0x00, 1372*4882a593Smuzhiyun AGG_TX_STATE_UNDERRUN_MSK = 0x01, 1373*4882a593Smuzhiyun AGG_TX_STATE_BT_PRIO_MSK = 0x02, 1374*4882a593Smuzhiyun AGG_TX_STATE_FEW_BYTES_MSK = 0x04, 1375*4882a593Smuzhiyun AGG_TX_STATE_ABORT_MSK = 0x08, 1376*4882a593Smuzhiyun AGG_TX_STATE_LAST_SENT_TTL_MSK = 0x10, 1377*4882a593Smuzhiyun AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK = 0x20, 1378*4882a593Smuzhiyun AGG_TX_STATE_LAST_SENT_BT_KILL_MSK = 0x40, 1379*4882a593Smuzhiyun AGG_TX_STATE_SCD_QUERY_MSK = 0x80, 1380*4882a593Smuzhiyun AGG_TX_STATE_TEST_BAD_CRC32_MSK = 0x100, 1381*4882a593Smuzhiyun AGG_TX_STATE_RESPONSE_MSK = 0x1ff, 1382*4882a593Smuzhiyun AGG_TX_STATE_DUMP_TX_MSK = 0x200, 1383*4882a593Smuzhiyun AGG_TX_STATE_DELAY_TX_MSK = 0x400 1384*4882a593Smuzhiyun }; 1385*4882a593Smuzhiyun 1386*4882a593Smuzhiyun #define AGG_TX_STATUS_MSK 0x00000fff /* bits 0:11 */ 1387*4882a593Smuzhiyun #define AGG_TX_TRY_MSK 0x0000f000 /* bits 12:15 */ 1388*4882a593Smuzhiyun #define AGG_TX_TRY_POS 12 1389*4882a593Smuzhiyun 1390*4882a593Smuzhiyun #define AGG_TX_STATE_LAST_SENT_MSK (AGG_TX_STATE_LAST_SENT_TTL_MSK | \ 1391*4882a593Smuzhiyun AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK | \ 1392*4882a593Smuzhiyun AGG_TX_STATE_LAST_SENT_BT_KILL_MSK) 1393*4882a593Smuzhiyun 1394*4882a593Smuzhiyun /* # tx attempts for first frame in aggregation */ 1395*4882a593Smuzhiyun #define AGG_TX_STATE_TRY_CNT_POS 12 1396*4882a593Smuzhiyun #define AGG_TX_STATE_TRY_CNT_MSK 0xf000 1397*4882a593Smuzhiyun 1398*4882a593Smuzhiyun /* Command ID and sequence number of Tx command for this frame */ 1399*4882a593Smuzhiyun #define AGG_TX_STATE_SEQ_NUM_POS 16 1400*4882a593Smuzhiyun #define AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000 1401*4882a593Smuzhiyun 1402*4882a593Smuzhiyun /* 1403*4882a593Smuzhiyun * REPLY_TX = 0x1c (response) 1404*4882a593Smuzhiyun * 1405*4882a593Smuzhiyun * This response may be in one of two slightly different formats, indicated 1406*4882a593Smuzhiyun * by the frame_count field: 1407*4882a593Smuzhiyun * 1408*4882a593Smuzhiyun * 1) No aggregation (frame_count == 1). This reports Tx results for 1409*4882a593Smuzhiyun * a single frame. Multiple attempts, at various bit rates, may have 1410*4882a593Smuzhiyun * been made for this frame. 1411*4882a593Smuzhiyun * 1412*4882a593Smuzhiyun * 2) Aggregation (frame_count > 1). This reports Tx results for 1413*4882a593Smuzhiyun * 2 or more frames that used block-acknowledge. All frames were 1414*4882a593Smuzhiyun * transmitted at same rate. Rate scaling may have been used if first 1415*4882a593Smuzhiyun * frame in this new agg block failed in previous agg block(s). 1416*4882a593Smuzhiyun * 1417*4882a593Smuzhiyun * Note that, for aggregation, ACK (block-ack) status is not delivered here; 1418*4882a593Smuzhiyun * block-ack has not been received by the time the agn device records 1419*4882a593Smuzhiyun * this status. 1420*4882a593Smuzhiyun * This status relates to reasons the tx might have been blocked or aborted 1421*4882a593Smuzhiyun * within the sending station (this agn device), rather than whether it was 1422*4882a593Smuzhiyun * received successfully by the destination station. 1423*4882a593Smuzhiyun */ 1424*4882a593Smuzhiyun struct agg_tx_status { 1425*4882a593Smuzhiyun __le16 status; 1426*4882a593Smuzhiyun __le16 sequence; 1427*4882a593Smuzhiyun } __packed; 1428*4882a593Smuzhiyun 1429*4882a593Smuzhiyun /* refer to ra_tid */ 1430*4882a593Smuzhiyun #define IWLAGN_TX_RES_TID_POS 0 1431*4882a593Smuzhiyun #define IWLAGN_TX_RES_TID_MSK 0x0f 1432*4882a593Smuzhiyun #define IWLAGN_TX_RES_RA_POS 4 1433*4882a593Smuzhiyun #define IWLAGN_TX_RES_RA_MSK 0xf0 1434*4882a593Smuzhiyun 1435*4882a593Smuzhiyun struct iwlagn_tx_resp { 1436*4882a593Smuzhiyun u8 frame_count; /* 1 no aggregation, >1 aggregation */ 1437*4882a593Smuzhiyun u8 bt_kill_count; /* # blocked by bluetooth (unused for agg) */ 1438*4882a593Smuzhiyun u8 failure_rts; /* # failures due to unsuccessful RTS */ 1439*4882a593Smuzhiyun u8 failure_frame; /* # failures due to no ACK (unused for agg) */ 1440*4882a593Smuzhiyun 1441*4882a593Smuzhiyun /* For non-agg: Rate at which frame was successful. 1442*4882a593Smuzhiyun * For agg: Rate at which all frames were transmitted. */ 1443*4882a593Smuzhiyun __le32 rate_n_flags; /* RATE_MCS_* */ 1444*4882a593Smuzhiyun 1445*4882a593Smuzhiyun /* For non-agg: RTS + CTS + frame tx attempts time + ACK. 1446*4882a593Smuzhiyun * For agg: RTS + CTS + aggregation tx time + block-ack time. */ 1447*4882a593Smuzhiyun __le16 wireless_media_time; /* uSecs */ 1448*4882a593Smuzhiyun 1449*4882a593Smuzhiyun u8 pa_status; /* RF power amplifier measurement (not used) */ 1450*4882a593Smuzhiyun u8 pa_integ_res_a[3]; 1451*4882a593Smuzhiyun u8 pa_integ_res_b[3]; 1452*4882a593Smuzhiyun u8 pa_integ_res_C[3]; 1453*4882a593Smuzhiyun 1454*4882a593Smuzhiyun __le32 tfd_info; 1455*4882a593Smuzhiyun __le16 seq_ctl; 1456*4882a593Smuzhiyun __le16 byte_cnt; 1457*4882a593Smuzhiyun u8 tlc_info; 1458*4882a593Smuzhiyun u8 ra_tid; /* tid (0:3), sta_id (4:7) */ 1459*4882a593Smuzhiyun __le16 frame_ctrl; 1460*4882a593Smuzhiyun /* 1461*4882a593Smuzhiyun * For non-agg: frame status TX_STATUS_* 1462*4882a593Smuzhiyun * For agg: status of 1st frame, AGG_TX_STATE_*; other frame status 1463*4882a593Smuzhiyun * fields follow this one, up to frame_count. 1464*4882a593Smuzhiyun * Bit fields: 1465*4882a593Smuzhiyun * 11- 0: AGG_TX_STATE_* status code 1466*4882a593Smuzhiyun * 15-12: Retry count for 1st frame in aggregation (retries 1467*4882a593Smuzhiyun * occur if tx failed for this frame when it was a 1468*4882a593Smuzhiyun * member of a previous aggregation block). If rate 1469*4882a593Smuzhiyun * scaling is used, retry count indicates the rate 1470*4882a593Smuzhiyun * table entry used for all frames in the new agg. 1471*4882a593Smuzhiyun * 31-16: Sequence # for this frame's Tx cmd (not SSN!) 1472*4882a593Smuzhiyun */ 1473*4882a593Smuzhiyun struct agg_tx_status status; /* TX status (in aggregation - 1474*4882a593Smuzhiyun * status of 1st frame) */ 1475*4882a593Smuzhiyun } __packed; 1476*4882a593Smuzhiyun /* 1477*4882a593Smuzhiyun * REPLY_COMPRESSED_BA = 0xc5 (response only, not a command) 1478*4882a593Smuzhiyun * 1479*4882a593Smuzhiyun * Reports Block-Acknowledge from recipient station 1480*4882a593Smuzhiyun */ 1481*4882a593Smuzhiyun struct iwl_compressed_ba_resp { 1482*4882a593Smuzhiyun __le32 sta_addr_lo32; 1483*4882a593Smuzhiyun __le16 sta_addr_hi16; 1484*4882a593Smuzhiyun __le16 reserved; 1485*4882a593Smuzhiyun 1486*4882a593Smuzhiyun /* Index of recipient (BA-sending) station in uCode's station table */ 1487*4882a593Smuzhiyun u8 sta_id; 1488*4882a593Smuzhiyun u8 tid; 1489*4882a593Smuzhiyun __le16 seq_ctl; 1490*4882a593Smuzhiyun __le64 bitmap; 1491*4882a593Smuzhiyun __le16 scd_flow; 1492*4882a593Smuzhiyun __le16 scd_ssn; 1493*4882a593Smuzhiyun u8 txed; /* number of frames sent */ 1494*4882a593Smuzhiyun u8 txed_2_done; /* number of frames acked */ 1495*4882a593Smuzhiyun __le16 reserved1; 1496*4882a593Smuzhiyun } __packed; 1497*4882a593Smuzhiyun 1498*4882a593Smuzhiyun /* 1499*4882a593Smuzhiyun * REPLY_TX_PWR_TABLE_CMD = 0x97 (command, has simple generic response) 1500*4882a593Smuzhiyun * 1501*4882a593Smuzhiyun */ 1502*4882a593Smuzhiyun 1503*4882a593Smuzhiyun /*RS_NEW_API: only TLC_RTS remains and moved to bit 0 */ 1504*4882a593Smuzhiyun #define LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK (1 << 0) 1505*4882a593Smuzhiyun 1506*4882a593Smuzhiyun /* # of EDCA prioritized tx fifos */ 1507*4882a593Smuzhiyun #define LINK_QUAL_AC_NUM AC_NUM 1508*4882a593Smuzhiyun 1509*4882a593Smuzhiyun /* # entries in rate scale table to support Tx retries */ 1510*4882a593Smuzhiyun #define LINK_QUAL_MAX_RETRY_NUM 16 1511*4882a593Smuzhiyun 1512*4882a593Smuzhiyun /* Tx antenna selection values */ 1513*4882a593Smuzhiyun #define LINK_QUAL_ANT_A_MSK (1 << 0) 1514*4882a593Smuzhiyun #define LINK_QUAL_ANT_B_MSK (1 << 1) 1515*4882a593Smuzhiyun #define LINK_QUAL_ANT_MSK (LINK_QUAL_ANT_A_MSK|LINK_QUAL_ANT_B_MSK) 1516*4882a593Smuzhiyun 1517*4882a593Smuzhiyun 1518*4882a593Smuzhiyun /** 1519*4882a593Smuzhiyun * struct iwl_link_qual_general_params 1520*4882a593Smuzhiyun * 1521*4882a593Smuzhiyun * Used in REPLY_TX_LINK_QUALITY_CMD 1522*4882a593Smuzhiyun */ 1523*4882a593Smuzhiyun struct iwl_link_qual_general_params { 1524*4882a593Smuzhiyun u8 flags; 1525*4882a593Smuzhiyun 1526*4882a593Smuzhiyun /* No entries at or above this (driver chosen) index contain MIMO */ 1527*4882a593Smuzhiyun u8 mimo_delimiter; 1528*4882a593Smuzhiyun 1529*4882a593Smuzhiyun /* Best single antenna to use for single stream (legacy, SISO). */ 1530*4882a593Smuzhiyun u8 single_stream_ant_msk; /* LINK_QUAL_ANT_* */ 1531*4882a593Smuzhiyun 1532*4882a593Smuzhiyun /* Best antennas to use for MIMO */ 1533*4882a593Smuzhiyun u8 dual_stream_ant_msk; /* LINK_QUAL_ANT_* */ 1534*4882a593Smuzhiyun 1535*4882a593Smuzhiyun /* 1536*4882a593Smuzhiyun * If driver needs to use different initial rates for different 1537*4882a593Smuzhiyun * EDCA QOS access categories (as implemented by tx fifos 0-3), 1538*4882a593Smuzhiyun * this table will set that up, by indicating the indexes in the 1539*4882a593Smuzhiyun * rs_table[LINK_QUAL_MAX_RETRY_NUM] rate table at which to start. 1540*4882a593Smuzhiyun * Otherwise, driver should set all entries to 0. 1541*4882a593Smuzhiyun * 1542*4882a593Smuzhiyun * Entry usage: 1543*4882a593Smuzhiyun * 0 = Background, 1 = Best Effort (normal), 2 = Video, 3 = Voice 1544*4882a593Smuzhiyun * TX FIFOs above 3 use same value (typically 0) as TX FIFO 3. 1545*4882a593Smuzhiyun */ 1546*4882a593Smuzhiyun u8 start_rate_index[LINK_QUAL_AC_NUM]; 1547*4882a593Smuzhiyun } __packed; 1548*4882a593Smuzhiyun 1549*4882a593Smuzhiyun #define LINK_QUAL_AGG_TIME_LIMIT_DEF (4000) /* 4 milliseconds */ 1550*4882a593Smuzhiyun #define LINK_QUAL_AGG_TIME_LIMIT_MAX (8000) 1551*4882a593Smuzhiyun #define LINK_QUAL_AGG_TIME_LIMIT_MIN (100) 1552*4882a593Smuzhiyun 1553*4882a593Smuzhiyun #define LINK_QUAL_AGG_DISABLE_START_DEF (3) 1554*4882a593Smuzhiyun #define LINK_QUAL_AGG_DISABLE_START_MAX (255) 1555*4882a593Smuzhiyun #define LINK_QUAL_AGG_DISABLE_START_MIN (0) 1556*4882a593Smuzhiyun 1557*4882a593Smuzhiyun #define LINK_QUAL_AGG_FRAME_LIMIT_DEF (63) 1558*4882a593Smuzhiyun #define LINK_QUAL_AGG_FRAME_LIMIT_MAX (63) 1559*4882a593Smuzhiyun #define LINK_QUAL_AGG_FRAME_LIMIT_MIN (0) 1560*4882a593Smuzhiyun 1561*4882a593Smuzhiyun /** 1562*4882a593Smuzhiyun * struct iwl_link_qual_agg_params 1563*4882a593Smuzhiyun * 1564*4882a593Smuzhiyun * Used in REPLY_TX_LINK_QUALITY_CMD 1565*4882a593Smuzhiyun */ 1566*4882a593Smuzhiyun struct iwl_link_qual_agg_params { 1567*4882a593Smuzhiyun 1568*4882a593Smuzhiyun /* 1569*4882a593Smuzhiyun *Maximum number of uSec in aggregation. 1570*4882a593Smuzhiyun * default set to 4000 (4 milliseconds) if not configured in .cfg 1571*4882a593Smuzhiyun */ 1572*4882a593Smuzhiyun __le16 agg_time_limit; 1573*4882a593Smuzhiyun 1574*4882a593Smuzhiyun /* 1575*4882a593Smuzhiyun * Number of Tx retries allowed for a frame, before that frame will 1576*4882a593Smuzhiyun * no longer be considered for the start of an aggregation sequence 1577*4882a593Smuzhiyun * (scheduler will then try to tx it as single frame). 1578*4882a593Smuzhiyun * Driver should set this to 3. 1579*4882a593Smuzhiyun */ 1580*4882a593Smuzhiyun u8 agg_dis_start_th; 1581*4882a593Smuzhiyun 1582*4882a593Smuzhiyun /* 1583*4882a593Smuzhiyun * Maximum number of frames in aggregation. 1584*4882a593Smuzhiyun * 0 = no limit (default). 1 = no aggregation. 1585*4882a593Smuzhiyun * Other values = max # frames in aggregation. 1586*4882a593Smuzhiyun */ 1587*4882a593Smuzhiyun u8 agg_frame_cnt_limit; 1588*4882a593Smuzhiyun 1589*4882a593Smuzhiyun __le32 reserved; 1590*4882a593Smuzhiyun } __packed; 1591*4882a593Smuzhiyun 1592*4882a593Smuzhiyun /* 1593*4882a593Smuzhiyun * REPLY_TX_LINK_QUALITY_CMD = 0x4e (command, has simple generic response) 1594*4882a593Smuzhiyun * 1595*4882a593Smuzhiyun * For agn devices 1596*4882a593Smuzhiyun * 1597*4882a593Smuzhiyun * Each station in the agn device's internal station table has its own table 1598*4882a593Smuzhiyun * of 16 1599*4882a593Smuzhiyun * Tx rates and modulation modes (e.g. legacy/SISO/MIMO) for retrying Tx when 1600*4882a593Smuzhiyun * an ACK is not received. This command replaces the entire table for 1601*4882a593Smuzhiyun * one station. 1602*4882a593Smuzhiyun * 1603*4882a593Smuzhiyun * NOTE: Station must already be in agn device's station table. 1604*4882a593Smuzhiyun * Use REPLY_ADD_STA. 1605*4882a593Smuzhiyun * 1606*4882a593Smuzhiyun * The rate scaling procedures described below work well. Of course, other 1607*4882a593Smuzhiyun * procedures are possible, and may work better for particular environments. 1608*4882a593Smuzhiyun * 1609*4882a593Smuzhiyun * 1610*4882a593Smuzhiyun * FILLING THE RATE TABLE 1611*4882a593Smuzhiyun * 1612*4882a593Smuzhiyun * Given a particular initial rate and mode, as determined by the rate 1613*4882a593Smuzhiyun * scaling algorithm described below, the Linux driver uses the following 1614*4882a593Smuzhiyun * formula to fill the rs_table[LINK_QUAL_MAX_RETRY_NUM] rate table in the 1615*4882a593Smuzhiyun * Link Quality command: 1616*4882a593Smuzhiyun * 1617*4882a593Smuzhiyun * 1618*4882a593Smuzhiyun * 1) If using High-throughput (HT) (SISO or MIMO) initial rate: 1619*4882a593Smuzhiyun * a) Use this same initial rate for first 3 entries. 1620*4882a593Smuzhiyun * b) Find next lower available rate using same mode (SISO or MIMO), 1621*4882a593Smuzhiyun * use for next 3 entries. If no lower rate available, switch to 1622*4882a593Smuzhiyun * legacy mode (no HT40 channel, no MIMO, no short guard interval). 1623*4882a593Smuzhiyun * c) If using MIMO, set command's mimo_delimiter to number of entries 1624*4882a593Smuzhiyun * using MIMO (3 or 6). 1625*4882a593Smuzhiyun * d) After trying 2 HT rates, switch to legacy mode (no HT40 channel, 1626*4882a593Smuzhiyun * no MIMO, no short guard interval), at the next lower bit rate 1627*4882a593Smuzhiyun * (e.g. if second HT bit rate was 54, try 48 legacy), and follow 1628*4882a593Smuzhiyun * legacy procedure for remaining table entries. 1629*4882a593Smuzhiyun * 1630*4882a593Smuzhiyun * 2) If using legacy initial rate: 1631*4882a593Smuzhiyun * a) Use the initial rate for only one entry. 1632*4882a593Smuzhiyun * b) For each following entry, reduce the rate to next lower available 1633*4882a593Smuzhiyun * rate, until reaching the lowest available rate. 1634*4882a593Smuzhiyun * c) When reducing rate, also switch antenna selection. 1635*4882a593Smuzhiyun * d) Once lowest available rate is reached, repeat this rate until 1636*4882a593Smuzhiyun * rate table is filled (16 entries), switching antenna each entry. 1637*4882a593Smuzhiyun * 1638*4882a593Smuzhiyun * 1639*4882a593Smuzhiyun * ACCUMULATING HISTORY 1640*4882a593Smuzhiyun * 1641*4882a593Smuzhiyun * The rate scaling algorithm for agn devices, as implemented in Linux driver, 1642*4882a593Smuzhiyun * uses two sets of frame Tx success history: One for the current/active 1643*4882a593Smuzhiyun * modulation mode, and one for a speculative/search mode that is being 1644*4882a593Smuzhiyun * attempted. If the speculative mode turns out to be more effective (i.e. 1645*4882a593Smuzhiyun * actual transfer rate is better), then the driver continues to use the 1646*4882a593Smuzhiyun * speculative mode as the new current active mode. 1647*4882a593Smuzhiyun * 1648*4882a593Smuzhiyun * Each history set contains, separately for each possible rate, data for a 1649*4882a593Smuzhiyun * sliding window of the 62 most recent tx attempts at that rate. The data 1650*4882a593Smuzhiyun * includes a shifting bitmap of success(1)/failure(0), and sums of successful 1651*4882a593Smuzhiyun * and attempted frames, from which the driver can additionally calculate a 1652*4882a593Smuzhiyun * success ratio (success / attempted) and number of failures 1653*4882a593Smuzhiyun * (attempted - success), and control the size of the window (attempted). 1654*4882a593Smuzhiyun * The driver uses the bit map to remove successes from the success sum, as 1655*4882a593Smuzhiyun * the oldest tx attempts fall out of the window. 1656*4882a593Smuzhiyun * 1657*4882a593Smuzhiyun * When the agn device makes multiple tx attempts for a given frame, each 1658*4882a593Smuzhiyun * attempt might be at a different rate, and have different modulation 1659*4882a593Smuzhiyun * characteristics (e.g. antenna, fat channel, short guard interval), as set 1660*4882a593Smuzhiyun * up in the rate scaling table in the Link Quality command. The driver must 1661*4882a593Smuzhiyun * determine which rate table entry was used for each tx attempt, to determine 1662*4882a593Smuzhiyun * which rate-specific history to update, and record only those attempts that 1663*4882a593Smuzhiyun * match the modulation characteristics of the history set. 1664*4882a593Smuzhiyun * 1665*4882a593Smuzhiyun * When using block-ack (aggregation), all frames are transmitted at the same 1666*4882a593Smuzhiyun * rate, since there is no per-attempt acknowledgment from the destination 1667*4882a593Smuzhiyun * station. The Tx response struct iwl_tx_resp indicates the Tx rate in 1668*4882a593Smuzhiyun * rate_n_flags field. After receiving a block-ack, the driver can update 1669*4882a593Smuzhiyun * history for the entire block all at once. 1670*4882a593Smuzhiyun * 1671*4882a593Smuzhiyun * 1672*4882a593Smuzhiyun * FINDING BEST STARTING RATE: 1673*4882a593Smuzhiyun * 1674*4882a593Smuzhiyun * When working with a selected initial modulation mode (see below), the 1675*4882a593Smuzhiyun * driver attempts to find a best initial rate. The initial rate is the 1676*4882a593Smuzhiyun * first entry in the Link Quality command's rate table. 1677*4882a593Smuzhiyun * 1678*4882a593Smuzhiyun * 1) Calculate actual throughput (success ratio * expected throughput, see 1679*4882a593Smuzhiyun * table below) for current initial rate. Do this only if enough frames 1680*4882a593Smuzhiyun * have been attempted to make the value meaningful: at least 6 failed 1681*4882a593Smuzhiyun * tx attempts, or at least 8 successes. If not enough, don't try rate 1682*4882a593Smuzhiyun * scaling yet. 1683*4882a593Smuzhiyun * 1684*4882a593Smuzhiyun * 2) Find available rates adjacent to current initial rate. Available means: 1685*4882a593Smuzhiyun * a) supported by hardware && 1686*4882a593Smuzhiyun * b) supported by association && 1687*4882a593Smuzhiyun * c) within any constraints selected by user 1688*4882a593Smuzhiyun * 1689*4882a593Smuzhiyun * 3) Gather measured throughputs for adjacent rates. These might not have 1690*4882a593Smuzhiyun * enough history to calculate a throughput. That's okay, we might try 1691*4882a593Smuzhiyun * using one of them anyway! 1692*4882a593Smuzhiyun * 1693*4882a593Smuzhiyun * 4) Try decreasing rate if, for current rate: 1694*4882a593Smuzhiyun * a) success ratio is < 15% || 1695*4882a593Smuzhiyun * b) lower adjacent rate has better measured throughput || 1696*4882a593Smuzhiyun * c) higher adjacent rate has worse throughput, and lower is unmeasured 1697*4882a593Smuzhiyun * 1698*4882a593Smuzhiyun * As a sanity check, if decrease was determined above, leave rate 1699*4882a593Smuzhiyun * unchanged if: 1700*4882a593Smuzhiyun * a) lower rate unavailable 1701*4882a593Smuzhiyun * b) success ratio at current rate > 85% (very good) 1702*4882a593Smuzhiyun * c) current measured throughput is better than expected throughput 1703*4882a593Smuzhiyun * of lower rate (under perfect 100% tx conditions, see table below) 1704*4882a593Smuzhiyun * 1705*4882a593Smuzhiyun * 5) Try increasing rate if, for current rate: 1706*4882a593Smuzhiyun * a) success ratio is < 15% || 1707*4882a593Smuzhiyun * b) both adjacent rates' throughputs are unmeasured (try it!) || 1708*4882a593Smuzhiyun * b) higher adjacent rate has better measured throughput || 1709*4882a593Smuzhiyun * c) lower adjacent rate has worse throughput, and higher is unmeasured 1710*4882a593Smuzhiyun * 1711*4882a593Smuzhiyun * As a sanity check, if increase was determined above, leave rate 1712*4882a593Smuzhiyun * unchanged if: 1713*4882a593Smuzhiyun * a) success ratio at current rate < 70%. This is not particularly 1714*4882a593Smuzhiyun * good performance; higher rate is sure to have poorer success. 1715*4882a593Smuzhiyun * 1716*4882a593Smuzhiyun * 6) Re-evaluate the rate after each tx frame. If working with block- 1717*4882a593Smuzhiyun * acknowledge, history and statistics may be calculated for the entire 1718*4882a593Smuzhiyun * block (including prior history that fits within the history windows), 1719*4882a593Smuzhiyun * before re-evaluation. 1720*4882a593Smuzhiyun * 1721*4882a593Smuzhiyun * FINDING BEST STARTING MODULATION MODE: 1722*4882a593Smuzhiyun * 1723*4882a593Smuzhiyun * After working with a modulation mode for a "while" (and doing rate scaling), 1724*4882a593Smuzhiyun * the driver searches for a new initial mode in an attempt to improve 1725*4882a593Smuzhiyun * throughput. The "while" is measured by numbers of attempted frames: 1726*4882a593Smuzhiyun * 1727*4882a593Smuzhiyun * For legacy mode, search for new mode after: 1728*4882a593Smuzhiyun * 480 successful frames, or 160 failed frames 1729*4882a593Smuzhiyun * For high-throughput modes (SISO or MIMO), search for new mode after: 1730*4882a593Smuzhiyun * 4500 successful frames, or 400 failed frames 1731*4882a593Smuzhiyun * 1732*4882a593Smuzhiyun * Mode switch possibilities are (3 for each mode): 1733*4882a593Smuzhiyun * 1734*4882a593Smuzhiyun * For legacy: 1735*4882a593Smuzhiyun * Change antenna, try SISO (if HT association), try MIMO (if HT association) 1736*4882a593Smuzhiyun * For SISO: 1737*4882a593Smuzhiyun * Change antenna, try MIMO, try shortened guard interval (SGI) 1738*4882a593Smuzhiyun * For MIMO: 1739*4882a593Smuzhiyun * Try SISO antenna A, SISO antenna B, try shortened guard interval (SGI) 1740*4882a593Smuzhiyun * 1741*4882a593Smuzhiyun * When trying a new mode, use the same bit rate as the old/current mode when 1742*4882a593Smuzhiyun * trying antenna switches and shortened guard interval. When switching to 1743*4882a593Smuzhiyun * SISO from MIMO or legacy, or to MIMO from SISO or legacy, use a rate 1744*4882a593Smuzhiyun * for which the expected throughput (under perfect conditions) is about the 1745*4882a593Smuzhiyun * same or slightly better than the actual measured throughput delivered by 1746*4882a593Smuzhiyun * the old/current mode. 1747*4882a593Smuzhiyun * 1748*4882a593Smuzhiyun * Actual throughput can be estimated by multiplying the expected throughput 1749*4882a593Smuzhiyun * by the success ratio (successful / attempted tx frames). Frame size is 1750*4882a593Smuzhiyun * not considered in this calculation; it assumes that frame size will average 1751*4882a593Smuzhiyun * out to be fairly consistent over several samples. The following are 1752*4882a593Smuzhiyun * metric values for expected throughput assuming 100% success ratio. 1753*4882a593Smuzhiyun * Only G band has support for CCK rates: 1754*4882a593Smuzhiyun * 1755*4882a593Smuzhiyun * RATE: 1 2 5 11 6 9 12 18 24 36 48 54 60 1756*4882a593Smuzhiyun * 1757*4882a593Smuzhiyun * G: 7 13 35 58 40 57 72 98 121 154 177 186 186 1758*4882a593Smuzhiyun * A: 0 0 0 0 40 57 72 98 121 154 177 186 186 1759*4882a593Smuzhiyun * SISO 20MHz: 0 0 0 0 42 42 76 102 124 159 183 193 202 1760*4882a593Smuzhiyun * SGI SISO 20MHz: 0 0 0 0 46 46 82 110 132 168 192 202 211 1761*4882a593Smuzhiyun * MIMO 20MHz: 0 0 0 0 74 74 123 155 179 214 236 244 251 1762*4882a593Smuzhiyun * SGI MIMO 20MHz: 0 0 0 0 81 81 131 164 188 222 243 251 257 1763*4882a593Smuzhiyun * SISO 40MHz: 0 0 0 0 77 77 127 160 184 220 242 250 257 1764*4882a593Smuzhiyun * SGI SISO 40MHz: 0 0 0 0 83 83 135 169 193 229 250 257 264 1765*4882a593Smuzhiyun * MIMO 40MHz: 0 0 0 0 123 123 182 214 235 264 279 285 289 1766*4882a593Smuzhiyun * SGI MIMO 40MHz: 0 0 0 0 131 131 191 222 242 270 284 289 293 1767*4882a593Smuzhiyun * 1768*4882a593Smuzhiyun * After the new mode has been tried for a short while (minimum of 6 failed 1769*4882a593Smuzhiyun * frames or 8 successful frames), compare success ratio and actual throughput 1770*4882a593Smuzhiyun * estimate of the new mode with the old. If either is better with the new 1771*4882a593Smuzhiyun * mode, continue to use the new mode. 1772*4882a593Smuzhiyun * 1773*4882a593Smuzhiyun * Continue comparing modes until all 3 possibilities have been tried. 1774*4882a593Smuzhiyun * If moving from legacy to HT, try all 3 possibilities from the new HT 1775*4882a593Smuzhiyun * mode. After trying all 3, a best mode is found. Continue to use this mode 1776*4882a593Smuzhiyun * for the longer "while" described above (e.g. 480 successful frames for 1777*4882a593Smuzhiyun * legacy), and then repeat the search process. 1778*4882a593Smuzhiyun * 1779*4882a593Smuzhiyun */ 1780*4882a593Smuzhiyun struct iwl_link_quality_cmd { 1781*4882a593Smuzhiyun 1782*4882a593Smuzhiyun /* Index of destination/recipient station in uCode's station table */ 1783*4882a593Smuzhiyun u8 sta_id; 1784*4882a593Smuzhiyun u8 reserved1; 1785*4882a593Smuzhiyun __le16 control; /* not used */ 1786*4882a593Smuzhiyun struct iwl_link_qual_general_params general_params; 1787*4882a593Smuzhiyun struct iwl_link_qual_agg_params agg_params; 1788*4882a593Smuzhiyun 1789*4882a593Smuzhiyun /* 1790*4882a593Smuzhiyun * Rate info; when using rate-scaling, Tx command's initial_rate_index 1791*4882a593Smuzhiyun * specifies 1st Tx rate attempted, via index into this table. 1792*4882a593Smuzhiyun * agn devices works its way through table when retrying Tx. 1793*4882a593Smuzhiyun */ 1794*4882a593Smuzhiyun struct { 1795*4882a593Smuzhiyun __le32 rate_n_flags; /* RATE_MCS_*, IWL_RATE_* */ 1796*4882a593Smuzhiyun } rs_table[LINK_QUAL_MAX_RETRY_NUM]; 1797*4882a593Smuzhiyun __le32 reserved2; 1798*4882a593Smuzhiyun } __packed; 1799*4882a593Smuzhiyun 1800*4882a593Smuzhiyun /* 1801*4882a593Smuzhiyun * BT configuration enable flags: 1802*4882a593Smuzhiyun * bit 0 - 1: BT channel announcement enabled 1803*4882a593Smuzhiyun * 0: disable 1804*4882a593Smuzhiyun * bit 1 - 1: priority of BT device enabled 1805*4882a593Smuzhiyun * 0: disable 1806*4882a593Smuzhiyun * bit 2 - 1: BT 2 wire support enabled 1807*4882a593Smuzhiyun * 0: disable 1808*4882a593Smuzhiyun */ 1809*4882a593Smuzhiyun #define BT_COEX_DISABLE (0x0) 1810*4882a593Smuzhiyun #define BT_ENABLE_CHANNEL_ANNOUNCE BIT(0) 1811*4882a593Smuzhiyun #define BT_ENABLE_PRIORITY BIT(1) 1812*4882a593Smuzhiyun #define BT_ENABLE_2_WIRE BIT(2) 1813*4882a593Smuzhiyun 1814*4882a593Smuzhiyun #define BT_COEX_DISABLE (0x0) 1815*4882a593Smuzhiyun #define BT_COEX_ENABLE (BT_ENABLE_CHANNEL_ANNOUNCE | BT_ENABLE_PRIORITY) 1816*4882a593Smuzhiyun 1817*4882a593Smuzhiyun #define BT_LEAD_TIME_MIN (0x0) 1818*4882a593Smuzhiyun #define BT_LEAD_TIME_DEF (0x1E) 1819*4882a593Smuzhiyun #define BT_LEAD_TIME_MAX (0xFF) 1820*4882a593Smuzhiyun 1821*4882a593Smuzhiyun #define BT_MAX_KILL_MIN (0x1) 1822*4882a593Smuzhiyun #define BT_MAX_KILL_DEF (0x5) 1823*4882a593Smuzhiyun #define BT_MAX_KILL_MAX (0xFF) 1824*4882a593Smuzhiyun 1825*4882a593Smuzhiyun #define BT_DURATION_LIMIT_DEF 625 1826*4882a593Smuzhiyun #define BT_DURATION_LIMIT_MAX 1250 1827*4882a593Smuzhiyun #define BT_DURATION_LIMIT_MIN 625 1828*4882a593Smuzhiyun 1829*4882a593Smuzhiyun #define BT_ON_THRESHOLD_DEF 4 1830*4882a593Smuzhiyun #define BT_ON_THRESHOLD_MAX 1000 1831*4882a593Smuzhiyun #define BT_ON_THRESHOLD_MIN 1 1832*4882a593Smuzhiyun 1833*4882a593Smuzhiyun #define BT_FRAG_THRESHOLD_DEF 0 1834*4882a593Smuzhiyun #define BT_FRAG_THRESHOLD_MAX 0 1835*4882a593Smuzhiyun #define BT_FRAG_THRESHOLD_MIN 0 1836*4882a593Smuzhiyun 1837*4882a593Smuzhiyun #define BT_AGG_THRESHOLD_DEF 1200 1838*4882a593Smuzhiyun #define BT_AGG_THRESHOLD_MAX 8000 1839*4882a593Smuzhiyun #define BT_AGG_THRESHOLD_MIN 400 1840*4882a593Smuzhiyun 1841*4882a593Smuzhiyun /* 1842*4882a593Smuzhiyun * REPLY_BT_CONFIG = 0x9b (command, has simple generic response) 1843*4882a593Smuzhiyun * 1844*4882a593Smuzhiyun * agn devices support hardware handshake with Bluetooth device on 1845*4882a593Smuzhiyun * same platform. Bluetooth device alerts wireless device when it will Tx; 1846*4882a593Smuzhiyun * wireless device can delay or kill its own Tx to accommodate. 1847*4882a593Smuzhiyun */ 1848*4882a593Smuzhiyun struct iwl_bt_cmd { 1849*4882a593Smuzhiyun u8 flags; 1850*4882a593Smuzhiyun u8 lead_time; 1851*4882a593Smuzhiyun u8 max_kill; 1852*4882a593Smuzhiyun u8 reserved; 1853*4882a593Smuzhiyun __le32 kill_ack_mask; 1854*4882a593Smuzhiyun __le32 kill_cts_mask; 1855*4882a593Smuzhiyun } __packed; 1856*4882a593Smuzhiyun 1857*4882a593Smuzhiyun #define IWLAGN_BT_FLAG_CHANNEL_INHIBITION BIT(0) 1858*4882a593Smuzhiyun 1859*4882a593Smuzhiyun #define IWLAGN_BT_FLAG_COEX_MODE_MASK (BIT(3)|BIT(4)|BIT(5)) 1860*4882a593Smuzhiyun #define IWLAGN_BT_FLAG_COEX_MODE_SHIFT 3 1861*4882a593Smuzhiyun #define IWLAGN_BT_FLAG_COEX_MODE_DISABLED 0 1862*4882a593Smuzhiyun #define IWLAGN_BT_FLAG_COEX_MODE_LEGACY_2W 1 1863*4882a593Smuzhiyun #define IWLAGN_BT_FLAG_COEX_MODE_3W 2 1864*4882a593Smuzhiyun #define IWLAGN_BT_FLAG_COEX_MODE_4W 3 1865*4882a593Smuzhiyun 1866*4882a593Smuzhiyun #define IWLAGN_BT_FLAG_UCODE_DEFAULT BIT(6) 1867*4882a593Smuzhiyun /* Disable Sync PSPoll on SCO/eSCO */ 1868*4882a593Smuzhiyun #define IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE BIT(7) 1869*4882a593Smuzhiyun 1870*4882a593Smuzhiyun #define IWLAGN_BT_PSP_MIN_RSSI_THRESHOLD -75 /* dBm */ 1871*4882a593Smuzhiyun #define IWLAGN_BT_PSP_MAX_RSSI_THRESHOLD -65 /* dBm */ 1872*4882a593Smuzhiyun 1873*4882a593Smuzhiyun #define IWLAGN_BT_PRIO_BOOST_MAX 0xFF 1874*4882a593Smuzhiyun #define IWLAGN_BT_PRIO_BOOST_MIN 0x00 1875*4882a593Smuzhiyun #define IWLAGN_BT_PRIO_BOOST_DEFAULT 0xF0 1876*4882a593Smuzhiyun #define IWLAGN_BT_PRIO_BOOST_DEFAULT32 0xF0F0F0F0 1877*4882a593Smuzhiyun 1878*4882a593Smuzhiyun #define IWLAGN_BT_MAX_KILL_DEFAULT 5 1879*4882a593Smuzhiyun 1880*4882a593Smuzhiyun #define IWLAGN_BT3_T7_DEFAULT 1 1881*4882a593Smuzhiyun 1882*4882a593Smuzhiyun enum iwl_bt_kill_idx { 1883*4882a593Smuzhiyun IWL_BT_KILL_DEFAULT = 0, 1884*4882a593Smuzhiyun IWL_BT_KILL_OVERRIDE = 1, 1885*4882a593Smuzhiyun IWL_BT_KILL_REDUCE = 2, 1886*4882a593Smuzhiyun }; 1887*4882a593Smuzhiyun 1888*4882a593Smuzhiyun #define IWLAGN_BT_KILL_ACK_MASK_DEFAULT cpu_to_le32(0xffff0000) 1889*4882a593Smuzhiyun #define IWLAGN_BT_KILL_CTS_MASK_DEFAULT cpu_to_le32(0xffff0000) 1890*4882a593Smuzhiyun #define IWLAGN_BT_KILL_ACK_CTS_MASK_SCO cpu_to_le32(0xffffffff) 1891*4882a593Smuzhiyun #define IWLAGN_BT_KILL_ACK_CTS_MASK_REDUCE cpu_to_le32(0) 1892*4882a593Smuzhiyun 1893*4882a593Smuzhiyun #define IWLAGN_BT3_PRIO_SAMPLE_DEFAULT 2 1894*4882a593Smuzhiyun 1895*4882a593Smuzhiyun #define IWLAGN_BT3_T2_DEFAULT 0xc 1896*4882a593Smuzhiyun 1897*4882a593Smuzhiyun #define IWLAGN_BT_VALID_ENABLE_FLAGS cpu_to_le16(BIT(0)) 1898*4882a593Smuzhiyun #define IWLAGN_BT_VALID_BOOST cpu_to_le16(BIT(1)) 1899*4882a593Smuzhiyun #define IWLAGN_BT_VALID_MAX_KILL cpu_to_le16(BIT(2)) 1900*4882a593Smuzhiyun #define IWLAGN_BT_VALID_3W_TIMERS cpu_to_le16(BIT(3)) 1901*4882a593Smuzhiyun #define IWLAGN_BT_VALID_KILL_ACK_MASK cpu_to_le16(BIT(4)) 1902*4882a593Smuzhiyun #define IWLAGN_BT_VALID_KILL_CTS_MASK cpu_to_le16(BIT(5)) 1903*4882a593Smuzhiyun #define IWLAGN_BT_VALID_REDUCED_TX_PWR cpu_to_le16(BIT(6)) 1904*4882a593Smuzhiyun #define IWLAGN_BT_VALID_3W_LUT cpu_to_le16(BIT(7)) 1905*4882a593Smuzhiyun 1906*4882a593Smuzhiyun #define IWLAGN_BT_ALL_VALID_MSK (IWLAGN_BT_VALID_ENABLE_FLAGS | \ 1907*4882a593Smuzhiyun IWLAGN_BT_VALID_BOOST | \ 1908*4882a593Smuzhiyun IWLAGN_BT_VALID_MAX_KILL | \ 1909*4882a593Smuzhiyun IWLAGN_BT_VALID_3W_TIMERS | \ 1910*4882a593Smuzhiyun IWLAGN_BT_VALID_KILL_ACK_MASK | \ 1911*4882a593Smuzhiyun IWLAGN_BT_VALID_KILL_CTS_MASK | \ 1912*4882a593Smuzhiyun IWLAGN_BT_VALID_REDUCED_TX_PWR | \ 1913*4882a593Smuzhiyun IWLAGN_BT_VALID_3W_LUT) 1914*4882a593Smuzhiyun 1915*4882a593Smuzhiyun #define IWLAGN_BT_REDUCED_TX_PWR BIT(0) 1916*4882a593Smuzhiyun 1917*4882a593Smuzhiyun #define IWLAGN_BT_DECISION_LUT_SIZE 12 1918*4882a593Smuzhiyun 1919*4882a593Smuzhiyun struct iwl_basic_bt_cmd { 1920*4882a593Smuzhiyun u8 flags; 1921*4882a593Smuzhiyun u8 ledtime; /* unused */ 1922*4882a593Smuzhiyun u8 max_kill; 1923*4882a593Smuzhiyun u8 bt3_timer_t7_value; 1924*4882a593Smuzhiyun __le32 kill_ack_mask; 1925*4882a593Smuzhiyun __le32 kill_cts_mask; 1926*4882a593Smuzhiyun u8 bt3_prio_sample_time; 1927*4882a593Smuzhiyun u8 bt3_timer_t2_value; 1928*4882a593Smuzhiyun __le16 bt4_reaction_time; /* unused */ 1929*4882a593Smuzhiyun __le32 bt3_lookup_table[IWLAGN_BT_DECISION_LUT_SIZE]; 1930*4882a593Smuzhiyun /* 1931*4882a593Smuzhiyun * bit 0: use reduced tx power for control frame 1932*4882a593Smuzhiyun * bit 1 - 7: reserved 1933*4882a593Smuzhiyun */ 1934*4882a593Smuzhiyun u8 reduce_txpower; 1935*4882a593Smuzhiyun u8 reserved; 1936*4882a593Smuzhiyun __le16 valid; 1937*4882a593Smuzhiyun }; 1938*4882a593Smuzhiyun 1939*4882a593Smuzhiyun struct iwl_bt_cmd_v1 { 1940*4882a593Smuzhiyun struct iwl_basic_bt_cmd basic; 1941*4882a593Smuzhiyun u8 prio_boost; 1942*4882a593Smuzhiyun /* 1943*4882a593Smuzhiyun * set IWLAGN_BT_VALID_BOOST to "1" in "valid" bitmask 1944*4882a593Smuzhiyun * if configure the following patterns 1945*4882a593Smuzhiyun */ 1946*4882a593Smuzhiyun u8 tx_prio_boost; /* SW boost of WiFi tx priority */ 1947*4882a593Smuzhiyun __le16 rx_prio_boost; /* SW boost of WiFi rx priority */ 1948*4882a593Smuzhiyun }; 1949*4882a593Smuzhiyun 1950*4882a593Smuzhiyun struct iwl_bt_cmd_v2 { 1951*4882a593Smuzhiyun struct iwl_basic_bt_cmd basic; 1952*4882a593Smuzhiyun __le32 prio_boost; 1953*4882a593Smuzhiyun /* 1954*4882a593Smuzhiyun * set IWLAGN_BT_VALID_BOOST to "1" in "valid" bitmask 1955*4882a593Smuzhiyun * if configure the following patterns 1956*4882a593Smuzhiyun */ 1957*4882a593Smuzhiyun u8 reserved; 1958*4882a593Smuzhiyun u8 tx_prio_boost; /* SW boost of WiFi tx priority */ 1959*4882a593Smuzhiyun __le16 rx_prio_boost; /* SW boost of WiFi rx priority */ 1960*4882a593Smuzhiyun }; 1961*4882a593Smuzhiyun 1962*4882a593Smuzhiyun #define IWLAGN_BT_SCO_ACTIVE cpu_to_le32(BIT(0)) 1963*4882a593Smuzhiyun 1964*4882a593Smuzhiyun struct iwlagn_bt_sco_cmd { 1965*4882a593Smuzhiyun __le32 flags; 1966*4882a593Smuzhiyun }; 1967*4882a593Smuzhiyun 1968*4882a593Smuzhiyun /****************************************************************************** 1969*4882a593Smuzhiyun * (6) 1970*4882a593Smuzhiyun * Spectrum Management (802.11h) Commands, Responses, Notifications: 1971*4882a593Smuzhiyun * 1972*4882a593Smuzhiyun *****************************************************************************/ 1973*4882a593Smuzhiyun 1974*4882a593Smuzhiyun /* 1975*4882a593Smuzhiyun * Spectrum Management 1976*4882a593Smuzhiyun */ 1977*4882a593Smuzhiyun #define MEASUREMENT_FILTER_FLAG (RXON_FILTER_PROMISC_MSK | \ 1978*4882a593Smuzhiyun RXON_FILTER_CTL2HOST_MSK | \ 1979*4882a593Smuzhiyun RXON_FILTER_ACCEPT_GRP_MSK | \ 1980*4882a593Smuzhiyun RXON_FILTER_DIS_DECRYPT_MSK | \ 1981*4882a593Smuzhiyun RXON_FILTER_DIS_GRP_DECRYPT_MSK | \ 1982*4882a593Smuzhiyun RXON_FILTER_ASSOC_MSK | \ 1983*4882a593Smuzhiyun RXON_FILTER_BCON_AWARE_MSK) 1984*4882a593Smuzhiyun 1985*4882a593Smuzhiyun struct iwl_measure_channel { 1986*4882a593Smuzhiyun __le32 duration; /* measurement duration in extended beacon 1987*4882a593Smuzhiyun * format */ 1988*4882a593Smuzhiyun u8 channel; /* channel to measure */ 1989*4882a593Smuzhiyun u8 type; /* see enum iwl_measure_type */ 1990*4882a593Smuzhiyun __le16 reserved; 1991*4882a593Smuzhiyun } __packed; 1992*4882a593Smuzhiyun 1993*4882a593Smuzhiyun /* 1994*4882a593Smuzhiyun * REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74 (command) 1995*4882a593Smuzhiyun */ 1996*4882a593Smuzhiyun struct iwl_spectrum_cmd { 1997*4882a593Smuzhiyun __le16 len; /* number of bytes starting from token */ 1998*4882a593Smuzhiyun u8 token; /* token id */ 1999*4882a593Smuzhiyun u8 id; /* measurement id -- 0 or 1 */ 2000*4882a593Smuzhiyun u8 origin; /* 0 = TGh, 1 = other, 2 = TGk */ 2001*4882a593Smuzhiyun u8 periodic; /* 1 = periodic */ 2002*4882a593Smuzhiyun __le16 path_loss_timeout; 2003*4882a593Smuzhiyun __le32 start_time; /* start time in extended beacon format */ 2004*4882a593Smuzhiyun __le32 reserved2; 2005*4882a593Smuzhiyun __le32 flags; /* rxon flags */ 2006*4882a593Smuzhiyun __le32 filter_flags; /* rxon filter flags */ 2007*4882a593Smuzhiyun __le16 channel_count; /* minimum 1, maximum 10 */ 2008*4882a593Smuzhiyun __le16 reserved3; 2009*4882a593Smuzhiyun struct iwl_measure_channel channels[10]; 2010*4882a593Smuzhiyun } __packed; 2011*4882a593Smuzhiyun 2012*4882a593Smuzhiyun /* 2013*4882a593Smuzhiyun * REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74 (response) 2014*4882a593Smuzhiyun */ 2015*4882a593Smuzhiyun struct iwl_spectrum_resp { 2016*4882a593Smuzhiyun u8 token; 2017*4882a593Smuzhiyun u8 id; /* id of the prior command replaced, or 0xff */ 2018*4882a593Smuzhiyun __le16 status; /* 0 - command will be handled 2019*4882a593Smuzhiyun * 1 - cannot handle (conflicts with another 2020*4882a593Smuzhiyun * measurement) */ 2021*4882a593Smuzhiyun } __packed; 2022*4882a593Smuzhiyun 2023*4882a593Smuzhiyun enum iwl_measurement_state { 2024*4882a593Smuzhiyun IWL_MEASUREMENT_START = 0, 2025*4882a593Smuzhiyun IWL_MEASUREMENT_STOP = 1, 2026*4882a593Smuzhiyun }; 2027*4882a593Smuzhiyun 2028*4882a593Smuzhiyun enum iwl_measurement_status { 2029*4882a593Smuzhiyun IWL_MEASUREMENT_OK = 0, 2030*4882a593Smuzhiyun IWL_MEASUREMENT_CONCURRENT = 1, 2031*4882a593Smuzhiyun IWL_MEASUREMENT_CSA_CONFLICT = 2, 2032*4882a593Smuzhiyun IWL_MEASUREMENT_TGH_CONFLICT = 3, 2033*4882a593Smuzhiyun /* 4-5 reserved */ 2034*4882a593Smuzhiyun IWL_MEASUREMENT_STOPPED = 6, 2035*4882a593Smuzhiyun IWL_MEASUREMENT_TIMEOUT = 7, 2036*4882a593Smuzhiyun IWL_MEASUREMENT_PERIODIC_FAILED = 8, 2037*4882a593Smuzhiyun }; 2038*4882a593Smuzhiyun 2039*4882a593Smuzhiyun #define NUM_ELEMENTS_IN_HISTOGRAM 8 2040*4882a593Smuzhiyun 2041*4882a593Smuzhiyun struct iwl_measurement_histogram { 2042*4882a593Smuzhiyun __le32 ofdm[NUM_ELEMENTS_IN_HISTOGRAM]; /* in 0.8usec counts */ 2043*4882a593Smuzhiyun __le32 cck[NUM_ELEMENTS_IN_HISTOGRAM]; /* in 1usec counts */ 2044*4882a593Smuzhiyun } __packed; 2045*4882a593Smuzhiyun 2046*4882a593Smuzhiyun /* clear channel availability counters */ 2047*4882a593Smuzhiyun struct iwl_measurement_cca_counters { 2048*4882a593Smuzhiyun __le32 ofdm; 2049*4882a593Smuzhiyun __le32 cck; 2050*4882a593Smuzhiyun } __packed; 2051*4882a593Smuzhiyun 2052*4882a593Smuzhiyun enum iwl_measure_type { 2053*4882a593Smuzhiyun IWL_MEASURE_BASIC = (1 << 0), 2054*4882a593Smuzhiyun IWL_MEASURE_CHANNEL_LOAD = (1 << 1), 2055*4882a593Smuzhiyun IWL_MEASURE_HISTOGRAM_RPI = (1 << 2), 2056*4882a593Smuzhiyun IWL_MEASURE_HISTOGRAM_NOISE = (1 << 3), 2057*4882a593Smuzhiyun IWL_MEASURE_FRAME = (1 << 4), 2058*4882a593Smuzhiyun /* bits 5:6 are reserved */ 2059*4882a593Smuzhiyun IWL_MEASURE_IDLE = (1 << 7), 2060*4882a593Smuzhiyun }; 2061*4882a593Smuzhiyun 2062*4882a593Smuzhiyun /* 2063*4882a593Smuzhiyun * SPECTRUM_MEASURE_NOTIFICATION = 0x75 (notification only, not a command) 2064*4882a593Smuzhiyun */ 2065*4882a593Smuzhiyun struct iwl_spectrum_notification { 2066*4882a593Smuzhiyun u8 id; /* measurement id -- 0 or 1 */ 2067*4882a593Smuzhiyun u8 token; 2068*4882a593Smuzhiyun u8 channel_index; /* index in measurement channel list */ 2069*4882a593Smuzhiyun u8 state; /* 0 - start, 1 - stop */ 2070*4882a593Smuzhiyun __le32 start_time; /* lower 32-bits of TSF */ 2071*4882a593Smuzhiyun u8 band; /* 0 - 5.2GHz, 1 - 2.4GHz */ 2072*4882a593Smuzhiyun u8 channel; 2073*4882a593Smuzhiyun u8 type; /* see enum iwl_measurement_type */ 2074*4882a593Smuzhiyun u8 reserved1; 2075*4882a593Smuzhiyun /* NOTE: cca_ofdm, cca_cck, basic_type, and histogram are only only 2076*4882a593Smuzhiyun * valid if applicable for measurement type requested. */ 2077*4882a593Smuzhiyun __le32 cca_ofdm; /* cca fraction time in 40Mhz clock periods */ 2078*4882a593Smuzhiyun __le32 cca_cck; /* cca fraction time in 44Mhz clock periods */ 2079*4882a593Smuzhiyun __le32 cca_time; /* channel load time in usecs */ 2080*4882a593Smuzhiyun u8 basic_type; /* 0 - bss, 1 - ofdm preamble, 2 - 2081*4882a593Smuzhiyun * unidentified */ 2082*4882a593Smuzhiyun u8 reserved2[3]; 2083*4882a593Smuzhiyun struct iwl_measurement_histogram histogram; 2084*4882a593Smuzhiyun __le32 stop_time; /* lower 32-bits of TSF */ 2085*4882a593Smuzhiyun __le32 status; /* see iwl_measurement_status */ 2086*4882a593Smuzhiyun } __packed; 2087*4882a593Smuzhiyun 2088*4882a593Smuzhiyun /****************************************************************************** 2089*4882a593Smuzhiyun * (7) 2090*4882a593Smuzhiyun * Power Management Commands, Responses, Notifications: 2091*4882a593Smuzhiyun * 2092*4882a593Smuzhiyun *****************************************************************************/ 2093*4882a593Smuzhiyun 2094*4882a593Smuzhiyun /** 2095*4882a593Smuzhiyun * struct iwl_powertable_cmd - Power Table Command 2096*4882a593Smuzhiyun * @flags: See below: 2097*4882a593Smuzhiyun * 2098*4882a593Smuzhiyun * POWER_TABLE_CMD = 0x77 (command, has simple generic response) 2099*4882a593Smuzhiyun * 2100*4882a593Smuzhiyun * PM allow: 2101*4882a593Smuzhiyun * bit 0 - '0' Driver not allow power management 2102*4882a593Smuzhiyun * '1' Driver allow PM (use rest of parameters) 2103*4882a593Smuzhiyun * 2104*4882a593Smuzhiyun * uCode send sleep notifications: 2105*4882a593Smuzhiyun * bit 1 - '0' Don't send sleep notification 2106*4882a593Smuzhiyun * '1' send sleep notification (SEND_PM_NOTIFICATION) 2107*4882a593Smuzhiyun * 2108*4882a593Smuzhiyun * Sleep over DTIM 2109*4882a593Smuzhiyun * bit 2 - '0' PM have to walk up every DTIM 2110*4882a593Smuzhiyun * '1' PM could sleep over DTIM till listen Interval. 2111*4882a593Smuzhiyun * 2112*4882a593Smuzhiyun * PCI power managed 2113*4882a593Smuzhiyun * bit 3 - '0' (PCI_CFG_LINK_CTRL & 0x1) 2114*4882a593Smuzhiyun * '1' !(PCI_CFG_LINK_CTRL & 0x1) 2115*4882a593Smuzhiyun * 2116*4882a593Smuzhiyun * Fast PD 2117*4882a593Smuzhiyun * bit 4 - '1' Put radio to sleep when receiving frame for others 2118*4882a593Smuzhiyun * 2119*4882a593Smuzhiyun * Force sleep Modes 2120*4882a593Smuzhiyun * bit 31/30- '00' use both mac/xtal sleeps 2121*4882a593Smuzhiyun * '01' force Mac sleep 2122*4882a593Smuzhiyun * '10' force xtal sleep 2123*4882a593Smuzhiyun * '11' Illegal set 2124*4882a593Smuzhiyun * 2125*4882a593Smuzhiyun * NOTE: if sleep_interval[SLEEP_INTRVL_TABLE_SIZE-1] > DTIM period then 2126*4882a593Smuzhiyun * ucode assume sleep over DTIM is allowed and we don't need to wake up 2127*4882a593Smuzhiyun * for every DTIM. 2128*4882a593Smuzhiyun */ 2129*4882a593Smuzhiyun #define IWL_POWER_VEC_SIZE 5 2130*4882a593Smuzhiyun 2131*4882a593Smuzhiyun #define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK cpu_to_le16(BIT(0)) 2132*4882a593Smuzhiyun #define IWL_POWER_POWER_SAVE_ENA_MSK cpu_to_le16(BIT(0)) 2133*4882a593Smuzhiyun #define IWL_POWER_POWER_MANAGEMENT_ENA_MSK cpu_to_le16(BIT(1)) 2134*4882a593Smuzhiyun #define IWL_POWER_SLEEP_OVER_DTIM_MSK cpu_to_le16(BIT(2)) 2135*4882a593Smuzhiyun #define IWL_POWER_PCI_PM_MSK cpu_to_le16(BIT(3)) 2136*4882a593Smuzhiyun #define IWL_POWER_FAST_PD cpu_to_le16(BIT(4)) 2137*4882a593Smuzhiyun #define IWL_POWER_BEACON_FILTERING cpu_to_le16(BIT(5)) 2138*4882a593Smuzhiyun #define IWL_POWER_SHADOW_REG_ENA cpu_to_le16(BIT(6)) 2139*4882a593Smuzhiyun #define IWL_POWER_CT_KILL_SET cpu_to_le16(BIT(7)) 2140*4882a593Smuzhiyun #define IWL_POWER_BT_SCO_ENA cpu_to_le16(BIT(8)) 2141*4882a593Smuzhiyun #define IWL_POWER_ADVANCE_PM_ENA_MSK cpu_to_le16(BIT(9)) 2142*4882a593Smuzhiyun 2143*4882a593Smuzhiyun struct iwl_powertable_cmd { 2144*4882a593Smuzhiyun __le16 flags; 2145*4882a593Smuzhiyun u8 keep_alive_seconds; 2146*4882a593Smuzhiyun u8 debug_flags; 2147*4882a593Smuzhiyun __le32 rx_data_timeout; 2148*4882a593Smuzhiyun __le32 tx_data_timeout; 2149*4882a593Smuzhiyun __le32 sleep_interval[IWL_POWER_VEC_SIZE]; 2150*4882a593Smuzhiyun __le32 keep_alive_beacons; 2151*4882a593Smuzhiyun } __packed; 2152*4882a593Smuzhiyun 2153*4882a593Smuzhiyun /* 2154*4882a593Smuzhiyun * PM_SLEEP_NOTIFICATION = 0x7A (notification only, not a command) 2155*4882a593Smuzhiyun * all devices identical. 2156*4882a593Smuzhiyun */ 2157*4882a593Smuzhiyun struct iwl_sleep_notification { 2158*4882a593Smuzhiyun u8 pm_sleep_mode; 2159*4882a593Smuzhiyun u8 pm_wakeup_src; 2160*4882a593Smuzhiyun __le16 reserved; 2161*4882a593Smuzhiyun __le32 sleep_time; 2162*4882a593Smuzhiyun __le32 tsf_low; 2163*4882a593Smuzhiyun __le32 bcon_timer; 2164*4882a593Smuzhiyun } __packed; 2165*4882a593Smuzhiyun 2166*4882a593Smuzhiyun /* Sleep states. all devices identical. */ 2167*4882a593Smuzhiyun enum { 2168*4882a593Smuzhiyun IWL_PM_NO_SLEEP = 0, 2169*4882a593Smuzhiyun IWL_PM_SLP_MAC = 1, 2170*4882a593Smuzhiyun IWL_PM_SLP_FULL_MAC_UNASSOCIATE = 2, 2171*4882a593Smuzhiyun IWL_PM_SLP_FULL_MAC_CARD_STATE = 3, 2172*4882a593Smuzhiyun IWL_PM_SLP_PHY = 4, 2173*4882a593Smuzhiyun IWL_PM_SLP_REPENT = 5, 2174*4882a593Smuzhiyun IWL_PM_WAKEUP_BY_TIMER = 6, 2175*4882a593Smuzhiyun IWL_PM_WAKEUP_BY_DRIVER = 7, 2176*4882a593Smuzhiyun IWL_PM_WAKEUP_BY_RFKILL = 8, 2177*4882a593Smuzhiyun /* 3 reserved */ 2178*4882a593Smuzhiyun IWL_PM_NUM_OF_MODES = 12, 2179*4882a593Smuzhiyun }; 2180*4882a593Smuzhiyun 2181*4882a593Smuzhiyun /* 2182*4882a593Smuzhiyun * REPLY_CARD_STATE_CMD = 0xa0 (command, has simple generic response) 2183*4882a593Smuzhiyun */ 2184*4882a593Smuzhiyun #define CARD_STATE_CMD_DISABLE 0x00 /* Put card to sleep */ 2185*4882a593Smuzhiyun #define CARD_STATE_CMD_ENABLE 0x01 /* Wake up card */ 2186*4882a593Smuzhiyun #define CARD_STATE_CMD_HALT 0x02 /* Power down permanently */ 2187*4882a593Smuzhiyun struct iwl_card_state_cmd { 2188*4882a593Smuzhiyun __le32 status; /* CARD_STATE_CMD_* request new power state */ 2189*4882a593Smuzhiyun } __packed; 2190*4882a593Smuzhiyun 2191*4882a593Smuzhiyun /* 2192*4882a593Smuzhiyun * CARD_STATE_NOTIFICATION = 0xa1 (notification only, not a command) 2193*4882a593Smuzhiyun */ 2194*4882a593Smuzhiyun struct iwl_card_state_notif { 2195*4882a593Smuzhiyun __le32 flags; 2196*4882a593Smuzhiyun } __packed; 2197*4882a593Smuzhiyun 2198*4882a593Smuzhiyun #define HW_CARD_DISABLED 0x01 2199*4882a593Smuzhiyun #define SW_CARD_DISABLED 0x02 2200*4882a593Smuzhiyun #define CT_CARD_DISABLED 0x04 2201*4882a593Smuzhiyun #define RXON_CARD_DISABLED 0x10 2202*4882a593Smuzhiyun 2203*4882a593Smuzhiyun struct iwl_ct_kill_config { 2204*4882a593Smuzhiyun __le32 reserved; 2205*4882a593Smuzhiyun __le32 critical_temperature_M; 2206*4882a593Smuzhiyun __le32 critical_temperature_R; 2207*4882a593Smuzhiyun } __packed; 2208*4882a593Smuzhiyun 2209*4882a593Smuzhiyun /* 1000, and 6x00 */ 2210*4882a593Smuzhiyun struct iwl_ct_kill_throttling_config { 2211*4882a593Smuzhiyun __le32 critical_temperature_exit; 2212*4882a593Smuzhiyun __le32 reserved; 2213*4882a593Smuzhiyun __le32 critical_temperature_enter; 2214*4882a593Smuzhiyun } __packed; 2215*4882a593Smuzhiyun 2216*4882a593Smuzhiyun /****************************************************************************** 2217*4882a593Smuzhiyun * (8) 2218*4882a593Smuzhiyun * Scan Commands, Responses, Notifications: 2219*4882a593Smuzhiyun * 2220*4882a593Smuzhiyun *****************************************************************************/ 2221*4882a593Smuzhiyun 2222*4882a593Smuzhiyun #define SCAN_CHANNEL_TYPE_PASSIVE cpu_to_le32(0) 2223*4882a593Smuzhiyun #define SCAN_CHANNEL_TYPE_ACTIVE cpu_to_le32(1) 2224*4882a593Smuzhiyun 2225*4882a593Smuzhiyun /** 2226*4882a593Smuzhiyun * struct iwl_scan_channel - entry in REPLY_SCAN_CMD channel table 2227*4882a593Smuzhiyun * 2228*4882a593Smuzhiyun * One for each channel in the scan list. 2229*4882a593Smuzhiyun * Each channel can independently select: 2230*4882a593Smuzhiyun * 1) SSID for directed active scans 2231*4882a593Smuzhiyun * 2) Txpower setting (for rate specified within Tx command) 2232*4882a593Smuzhiyun * 3) How long to stay on-channel (behavior may be modified by quiet_time, 2233*4882a593Smuzhiyun * quiet_plcp_th, good_CRC_th) 2234*4882a593Smuzhiyun * 2235*4882a593Smuzhiyun * To avoid uCode errors, make sure the following are true (see comments 2236*4882a593Smuzhiyun * under struct iwl_scan_cmd about max_out_time and quiet_time): 2237*4882a593Smuzhiyun * 1) If using passive_dwell (i.e. passive_dwell != 0): 2238*4882a593Smuzhiyun * active_dwell <= passive_dwell (< max_out_time if max_out_time != 0) 2239*4882a593Smuzhiyun * 2) quiet_time <= active_dwell 2240*4882a593Smuzhiyun * 3) If restricting off-channel time (i.e. max_out_time !=0): 2241*4882a593Smuzhiyun * passive_dwell < max_out_time 2242*4882a593Smuzhiyun * active_dwell < max_out_time 2243*4882a593Smuzhiyun */ 2244*4882a593Smuzhiyun 2245*4882a593Smuzhiyun struct iwl_scan_channel { 2246*4882a593Smuzhiyun /* 2247*4882a593Smuzhiyun * type is defined as: 2248*4882a593Smuzhiyun * 0:0 1 = active, 0 = passive 2249*4882a593Smuzhiyun * 1:20 SSID direct bit map; if a bit is set, then corresponding 2250*4882a593Smuzhiyun * SSID IE is transmitted in probe request. 2251*4882a593Smuzhiyun * 21:31 reserved 2252*4882a593Smuzhiyun */ 2253*4882a593Smuzhiyun __le32 type; 2254*4882a593Smuzhiyun __le16 channel; /* band is selected by iwl_scan_cmd "flags" field */ 2255*4882a593Smuzhiyun u8 tx_gain; /* gain for analog radio */ 2256*4882a593Smuzhiyun u8 dsp_atten; /* gain for DSP */ 2257*4882a593Smuzhiyun __le16 active_dwell; /* in 1024-uSec TU (time units), typ 5-50 */ 2258*4882a593Smuzhiyun __le16 passive_dwell; /* in 1024-uSec TU (time units), typ 20-500 */ 2259*4882a593Smuzhiyun } __packed; 2260*4882a593Smuzhiyun 2261*4882a593Smuzhiyun /* set number of direct probes __le32 type */ 2262*4882a593Smuzhiyun #define IWL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1)))) 2263*4882a593Smuzhiyun 2264*4882a593Smuzhiyun /** 2265*4882a593Smuzhiyun * struct iwl_ssid_ie - directed scan network information element 2266*4882a593Smuzhiyun * 2267*4882a593Smuzhiyun * Up to 20 of these may appear in REPLY_SCAN_CMD, 2268*4882a593Smuzhiyun * selected by "type" bit field in struct iwl_scan_channel; 2269*4882a593Smuzhiyun * each channel may select different ssids from among the 20 entries. 2270*4882a593Smuzhiyun * SSID IEs get transmitted in reverse order of entry. 2271*4882a593Smuzhiyun */ 2272*4882a593Smuzhiyun struct iwl_ssid_ie { 2273*4882a593Smuzhiyun u8 id; 2274*4882a593Smuzhiyun u8 len; 2275*4882a593Smuzhiyun u8 ssid[32]; 2276*4882a593Smuzhiyun } __packed; 2277*4882a593Smuzhiyun 2278*4882a593Smuzhiyun #define PROBE_OPTION_MAX 20 2279*4882a593Smuzhiyun #define TX_CMD_LIFE_TIME_INFINITE cpu_to_le32(0xFFFFFFFF) 2280*4882a593Smuzhiyun #define IWL_GOOD_CRC_TH_DISABLED 0 2281*4882a593Smuzhiyun #define IWL_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 2282*4882a593Smuzhiyun #define IWL_GOOD_CRC_TH_NEVER cpu_to_le16(0xffff) 2283*4882a593Smuzhiyun #define IWL_MAX_CMD_SIZE 4096 2284*4882a593Smuzhiyun 2285*4882a593Smuzhiyun /* 2286*4882a593Smuzhiyun * REPLY_SCAN_CMD = 0x80 (command) 2287*4882a593Smuzhiyun * 2288*4882a593Smuzhiyun * The hardware scan command is very powerful; the driver can set it up to 2289*4882a593Smuzhiyun * maintain (relatively) normal network traffic while doing a scan in the 2290*4882a593Smuzhiyun * background. The max_out_time and suspend_time control the ratio of how 2291*4882a593Smuzhiyun * long the device stays on an associated network channel ("service channel") 2292*4882a593Smuzhiyun * vs. how long it's away from the service channel, i.e. tuned to other channels 2293*4882a593Smuzhiyun * for scanning. 2294*4882a593Smuzhiyun * 2295*4882a593Smuzhiyun * max_out_time is the max time off-channel (in usec), and suspend_time 2296*4882a593Smuzhiyun * is how long (in "extended beacon" format) that the scan is "suspended" 2297*4882a593Smuzhiyun * after returning to the service channel. That is, suspend_time is the 2298*4882a593Smuzhiyun * time that we stay on the service channel, doing normal work, between 2299*4882a593Smuzhiyun * scan segments. The driver may set these parameters differently to support 2300*4882a593Smuzhiyun * scanning when associated vs. not associated, and light vs. heavy traffic 2301*4882a593Smuzhiyun * loads when associated. 2302*4882a593Smuzhiyun * 2303*4882a593Smuzhiyun * After receiving this command, the device's scan engine does the following; 2304*4882a593Smuzhiyun * 2305*4882a593Smuzhiyun * 1) Sends SCAN_START notification to driver 2306*4882a593Smuzhiyun * 2) Checks to see if it has time to do scan for one channel 2307*4882a593Smuzhiyun * 3) Sends NULL packet, with power-save (PS) bit set to 1, 2308*4882a593Smuzhiyun * to tell AP that we're going off-channel 2309*4882a593Smuzhiyun * 4) Tunes to first channel in scan list, does active or passive scan 2310*4882a593Smuzhiyun * 5) Sends SCAN_RESULT notification to driver 2311*4882a593Smuzhiyun * 6) Checks to see if it has time to do scan on *next* channel in list 2312*4882a593Smuzhiyun * 7) Repeats 4-6 until it no longer has time to scan the next channel 2313*4882a593Smuzhiyun * before max_out_time expires 2314*4882a593Smuzhiyun * 8) Returns to service channel 2315*4882a593Smuzhiyun * 9) Sends NULL packet with PS=0 to tell AP that we're back 2316*4882a593Smuzhiyun * 10) Stays on service channel until suspend_time expires 2317*4882a593Smuzhiyun * 11) Repeats entire process 2-10 until list is complete 2318*4882a593Smuzhiyun * 12) Sends SCAN_COMPLETE notification 2319*4882a593Smuzhiyun * 2320*4882a593Smuzhiyun * For fast, efficient scans, the scan command also has support for staying on 2321*4882a593Smuzhiyun * a channel for just a short time, if doing active scanning and getting no 2322*4882a593Smuzhiyun * responses to the transmitted probe request. This time is controlled by 2323*4882a593Smuzhiyun * quiet_time, and the number of received packets below which a channel is 2324*4882a593Smuzhiyun * considered "quiet" is controlled by quiet_plcp_threshold. 2325*4882a593Smuzhiyun * 2326*4882a593Smuzhiyun * For active scanning on channels that have regulatory restrictions against 2327*4882a593Smuzhiyun * blindly transmitting, the scan can listen before transmitting, to make sure 2328*4882a593Smuzhiyun * that there is already legitimate activity on the channel. If enough 2329*4882a593Smuzhiyun * packets are cleanly received on the channel (controlled by good_CRC_th, 2330*4882a593Smuzhiyun * typical value 1), the scan engine starts transmitting probe requests. 2331*4882a593Smuzhiyun * 2332*4882a593Smuzhiyun * Driver must use separate scan commands for 2.4 vs. 5 GHz bands. 2333*4882a593Smuzhiyun * 2334*4882a593Smuzhiyun * To avoid uCode errors, see timing restrictions described under 2335*4882a593Smuzhiyun * struct iwl_scan_channel. 2336*4882a593Smuzhiyun */ 2337*4882a593Smuzhiyun 2338*4882a593Smuzhiyun enum iwl_scan_flags { 2339*4882a593Smuzhiyun /* BIT(0) currently unused */ 2340*4882a593Smuzhiyun IWL_SCAN_FLAGS_ACTION_FRAME_TX = BIT(1), 2341*4882a593Smuzhiyun /* bits 2-7 reserved */ 2342*4882a593Smuzhiyun }; 2343*4882a593Smuzhiyun 2344*4882a593Smuzhiyun struct iwl_scan_cmd { 2345*4882a593Smuzhiyun __le16 len; 2346*4882a593Smuzhiyun u8 scan_flags; /* scan flags: see enum iwl_scan_flags */ 2347*4882a593Smuzhiyun u8 channel_count; /* # channels in channel list */ 2348*4882a593Smuzhiyun __le16 quiet_time; /* dwell only this # millisecs on quiet channel 2349*4882a593Smuzhiyun * (only for active scan) */ 2350*4882a593Smuzhiyun __le16 quiet_plcp_th; /* quiet chnl is < this # pkts (typ. 1) */ 2351*4882a593Smuzhiyun __le16 good_CRC_th; /* passive -> active promotion threshold */ 2352*4882a593Smuzhiyun __le16 rx_chain; /* RXON_RX_CHAIN_* */ 2353*4882a593Smuzhiyun __le32 max_out_time; /* max usec to be away from associated (service) 2354*4882a593Smuzhiyun * channel */ 2355*4882a593Smuzhiyun __le32 suspend_time; /* pause scan this long (in "extended beacon 2356*4882a593Smuzhiyun * format") when returning to service chnl: 2357*4882a593Smuzhiyun */ 2358*4882a593Smuzhiyun __le32 flags; /* RXON_FLG_* */ 2359*4882a593Smuzhiyun __le32 filter_flags; /* RXON_FILTER_* */ 2360*4882a593Smuzhiyun 2361*4882a593Smuzhiyun /* For active scans (set to all-0s for passive scans). 2362*4882a593Smuzhiyun * Does not include payload. Must specify Tx rate; no rate scaling. */ 2363*4882a593Smuzhiyun struct iwl_tx_cmd tx_cmd; 2364*4882a593Smuzhiyun 2365*4882a593Smuzhiyun /* For directed active scans (set to all-0s otherwise) */ 2366*4882a593Smuzhiyun struct iwl_ssid_ie direct_scan[PROBE_OPTION_MAX]; 2367*4882a593Smuzhiyun 2368*4882a593Smuzhiyun /* 2369*4882a593Smuzhiyun * Probe request frame, followed by channel list. 2370*4882a593Smuzhiyun * 2371*4882a593Smuzhiyun * Size of probe request frame is specified by byte count in tx_cmd. 2372*4882a593Smuzhiyun * Channel list follows immediately after probe request frame. 2373*4882a593Smuzhiyun * Number of channels in list is specified by channel_count. 2374*4882a593Smuzhiyun * Each channel in list is of type: 2375*4882a593Smuzhiyun * 2376*4882a593Smuzhiyun * struct iwl_scan_channel channels[0]; 2377*4882a593Smuzhiyun * 2378*4882a593Smuzhiyun * NOTE: Only one band of channels can be scanned per pass. You 2379*4882a593Smuzhiyun * must not mix 2.4GHz channels and 5.2GHz channels, and you must wait 2380*4882a593Smuzhiyun * for one scan to complete (i.e. receive SCAN_COMPLETE_NOTIFICATION) 2381*4882a593Smuzhiyun * before requesting another scan. 2382*4882a593Smuzhiyun */ 2383*4882a593Smuzhiyun u8 data[]; 2384*4882a593Smuzhiyun } __packed; 2385*4882a593Smuzhiyun 2386*4882a593Smuzhiyun /* Can abort will notify by complete notification with abort status. */ 2387*4882a593Smuzhiyun #define CAN_ABORT_STATUS cpu_to_le32(0x1) 2388*4882a593Smuzhiyun /* complete notification statuses */ 2389*4882a593Smuzhiyun #define ABORT_STATUS 0x2 2390*4882a593Smuzhiyun 2391*4882a593Smuzhiyun /* 2392*4882a593Smuzhiyun * REPLY_SCAN_CMD = 0x80 (response) 2393*4882a593Smuzhiyun */ 2394*4882a593Smuzhiyun struct iwl_scanreq_notification { 2395*4882a593Smuzhiyun __le32 status; /* 1: okay, 2: cannot fulfill request */ 2396*4882a593Smuzhiyun } __packed; 2397*4882a593Smuzhiyun 2398*4882a593Smuzhiyun /* 2399*4882a593Smuzhiyun * SCAN_START_NOTIFICATION = 0x82 (notification only, not a command) 2400*4882a593Smuzhiyun */ 2401*4882a593Smuzhiyun struct iwl_scanstart_notification { 2402*4882a593Smuzhiyun __le32 tsf_low; 2403*4882a593Smuzhiyun __le32 tsf_high; 2404*4882a593Smuzhiyun __le32 beacon_timer; 2405*4882a593Smuzhiyun u8 channel; 2406*4882a593Smuzhiyun u8 band; 2407*4882a593Smuzhiyun u8 reserved[2]; 2408*4882a593Smuzhiyun __le32 status; 2409*4882a593Smuzhiyun } __packed; 2410*4882a593Smuzhiyun 2411*4882a593Smuzhiyun #define SCAN_OWNER_STATUS 0x1 2412*4882a593Smuzhiyun #define MEASURE_OWNER_STATUS 0x2 2413*4882a593Smuzhiyun 2414*4882a593Smuzhiyun #define IWL_PROBE_STATUS_OK 0 2415*4882a593Smuzhiyun #define IWL_PROBE_STATUS_TX_FAILED BIT(0) 2416*4882a593Smuzhiyun /* error statuses combined with TX_FAILED */ 2417*4882a593Smuzhiyun #define IWL_PROBE_STATUS_FAIL_TTL BIT(1) 2418*4882a593Smuzhiyun #define IWL_PROBE_STATUS_FAIL_BT BIT(2) 2419*4882a593Smuzhiyun 2420*4882a593Smuzhiyun #define NUMBER_OF_STATISTICS 1 /* first __le32 is good CRC */ 2421*4882a593Smuzhiyun /* 2422*4882a593Smuzhiyun * SCAN_RESULTS_NOTIFICATION = 0x83 (notification only, not a command) 2423*4882a593Smuzhiyun */ 2424*4882a593Smuzhiyun struct iwl_scanresults_notification { 2425*4882a593Smuzhiyun u8 channel; 2426*4882a593Smuzhiyun u8 band; 2427*4882a593Smuzhiyun u8 probe_status; 2428*4882a593Smuzhiyun u8 num_probe_not_sent; /* not enough time to send */ 2429*4882a593Smuzhiyun __le32 tsf_low; 2430*4882a593Smuzhiyun __le32 tsf_high; 2431*4882a593Smuzhiyun __le32 statistics[NUMBER_OF_STATISTICS]; 2432*4882a593Smuzhiyun } __packed; 2433*4882a593Smuzhiyun 2434*4882a593Smuzhiyun /* 2435*4882a593Smuzhiyun * SCAN_COMPLETE_NOTIFICATION = 0x84 (notification only, not a command) 2436*4882a593Smuzhiyun */ 2437*4882a593Smuzhiyun struct iwl_scancomplete_notification { 2438*4882a593Smuzhiyun u8 scanned_channels; 2439*4882a593Smuzhiyun u8 status; 2440*4882a593Smuzhiyun u8 bt_status; /* BT On/Off status */ 2441*4882a593Smuzhiyun u8 last_channel; 2442*4882a593Smuzhiyun __le32 tsf_low; 2443*4882a593Smuzhiyun __le32 tsf_high; 2444*4882a593Smuzhiyun } __packed; 2445*4882a593Smuzhiyun 2446*4882a593Smuzhiyun 2447*4882a593Smuzhiyun /****************************************************************************** 2448*4882a593Smuzhiyun * (9) 2449*4882a593Smuzhiyun * IBSS/AP Commands and Notifications: 2450*4882a593Smuzhiyun * 2451*4882a593Smuzhiyun *****************************************************************************/ 2452*4882a593Smuzhiyun 2453*4882a593Smuzhiyun enum iwl_ibss_manager { 2454*4882a593Smuzhiyun IWL_NOT_IBSS_MANAGER = 0, 2455*4882a593Smuzhiyun IWL_IBSS_MANAGER = 1, 2456*4882a593Smuzhiyun }; 2457*4882a593Smuzhiyun 2458*4882a593Smuzhiyun /* 2459*4882a593Smuzhiyun * BEACON_NOTIFICATION = 0x90 (notification only, not a command) 2460*4882a593Smuzhiyun */ 2461*4882a593Smuzhiyun 2462*4882a593Smuzhiyun struct iwlagn_beacon_notif { 2463*4882a593Smuzhiyun struct iwlagn_tx_resp beacon_notify_hdr; 2464*4882a593Smuzhiyun __le32 low_tsf; 2465*4882a593Smuzhiyun __le32 high_tsf; 2466*4882a593Smuzhiyun __le32 ibss_mgr_status; 2467*4882a593Smuzhiyun } __packed; 2468*4882a593Smuzhiyun 2469*4882a593Smuzhiyun /* 2470*4882a593Smuzhiyun * REPLY_TX_BEACON = 0x91 (command, has simple generic response) 2471*4882a593Smuzhiyun */ 2472*4882a593Smuzhiyun 2473*4882a593Smuzhiyun struct iwl_tx_beacon_cmd { 2474*4882a593Smuzhiyun struct iwl_tx_cmd tx; 2475*4882a593Smuzhiyun __le16 tim_idx; 2476*4882a593Smuzhiyun u8 tim_size; 2477*4882a593Smuzhiyun u8 reserved1; 2478*4882a593Smuzhiyun struct ieee80211_hdr frame[]; /* beacon frame */ 2479*4882a593Smuzhiyun } __packed; 2480*4882a593Smuzhiyun 2481*4882a593Smuzhiyun /****************************************************************************** 2482*4882a593Smuzhiyun * (10) 2483*4882a593Smuzhiyun * Statistics Commands and Notifications: 2484*4882a593Smuzhiyun * 2485*4882a593Smuzhiyun *****************************************************************************/ 2486*4882a593Smuzhiyun 2487*4882a593Smuzhiyun #define IWL_TEMP_CONVERT 260 2488*4882a593Smuzhiyun 2489*4882a593Smuzhiyun #define SUP_RATE_11A_MAX_NUM_CHANNELS 8 2490*4882a593Smuzhiyun #define SUP_RATE_11B_MAX_NUM_CHANNELS 4 2491*4882a593Smuzhiyun #define SUP_RATE_11G_MAX_NUM_CHANNELS 12 2492*4882a593Smuzhiyun 2493*4882a593Smuzhiyun /* Used for passing to driver number of successes and failures per rate */ 2494*4882a593Smuzhiyun struct rate_histogram { 2495*4882a593Smuzhiyun union { 2496*4882a593Smuzhiyun __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS]; 2497*4882a593Smuzhiyun __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS]; 2498*4882a593Smuzhiyun __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS]; 2499*4882a593Smuzhiyun } success; 2500*4882a593Smuzhiyun union { 2501*4882a593Smuzhiyun __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS]; 2502*4882a593Smuzhiyun __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS]; 2503*4882a593Smuzhiyun __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS]; 2504*4882a593Smuzhiyun } failed; 2505*4882a593Smuzhiyun } __packed; 2506*4882a593Smuzhiyun 2507*4882a593Smuzhiyun /* statistics command response */ 2508*4882a593Smuzhiyun 2509*4882a593Smuzhiyun struct statistics_dbg { 2510*4882a593Smuzhiyun __le32 burst_check; 2511*4882a593Smuzhiyun __le32 burst_count; 2512*4882a593Smuzhiyun __le32 wait_for_silence_timeout_cnt; 2513*4882a593Smuzhiyun __le32 reserved[3]; 2514*4882a593Smuzhiyun } __packed; 2515*4882a593Smuzhiyun 2516*4882a593Smuzhiyun struct statistics_rx_phy { 2517*4882a593Smuzhiyun __le32 ina_cnt; 2518*4882a593Smuzhiyun __le32 fina_cnt; 2519*4882a593Smuzhiyun __le32 plcp_err; 2520*4882a593Smuzhiyun __le32 crc32_err; 2521*4882a593Smuzhiyun __le32 overrun_err; 2522*4882a593Smuzhiyun __le32 early_overrun_err; 2523*4882a593Smuzhiyun __le32 crc32_good; 2524*4882a593Smuzhiyun __le32 false_alarm_cnt; 2525*4882a593Smuzhiyun __le32 fina_sync_err_cnt; 2526*4882a593Smuzhiyun __le32 sfd_timeout; 2527*4882a593Smuzhiyun __le32 fina_timeout; 2528*4882a593Smuzhiyun __le32 unresponded_rts; 2529*4882a593Smuzhiyun __le32 rxe_frame_limit_overrun; 2530*4882a593Smuzhiyun __le32 sent_ack_cnt; 2531*4882a593Smuzhiyun __le32 sent_cts_cnt; 2532*4882a593Smuzhiyun __le32 sent_ba_rsp_cnt; 2533*4882a593Smuzhiyun __le32 dsp_self_kill; 2534*4882a593Smuzhiyun __le32 mh_format_err; 2535*4882a593Smuzhiyun __le32 re_acq_main_rssi_sum; 2536*4882a593Smuzhiyun __le32 reserved3; 2537*4882a593Smuzhiyun } __packed; 2538*4882a593Smuzhiyun 2539*4882a593Smuzhiyun struct statistics_rx_ht_phy { 2540*4882a593Smuzhiyun __le32 plcp_err; 2541*4882a593Smuzhiyun __le32 overrun_err; 2542*4882a593Smuzhiyun __le32 early_overrun_err; 2543*4882a593Smuzhiyun __le32 crc32_good; 2544*4882a593Smuzhiyun __le32 crc32_err; 2545*4882a593Smuzhiyun __le32 mh_format_err; 2546*4882a593Smuzhiyun __le32 agg_crc32_good; 2547*4882a593Smuzhiyun __le32 agg_mpdu_cnt; 2548*4882a593Smuzhiyun __le32 agg_cnt; 2549*4882a593Smuzhiyun __le32 unsupport_mcs; 2550*4882a593Smuzhiyun } __packed; 2551*4882a593Smuzhiyun 2552*4882a593Smuzhiyun #define INTERFERENCE_DATA_AVAILABLE cpu_to_le32(1) 2553*4882a593Smuzhiyun 2554*4882a593Smuzhiyun struct statistics_rx_non_phy { 2555*4882a593Smuzhiyun __le32 bogus_cts; /* CTS received when not expecting CTS */ 2556*4882a593Smuzhiyun __le32 bogus_ack; /* ACK received when not expecting ACK */ 2557*4882a593Smuzhiyun __le32 non_bssid_frames; /* number of frames with BSSID that 2558*4882a593Smuzhiyun * doesn't belong to the STA BSSID */ 2559*4882a593Smuzhiyun __le32 filtered_frames; /* count frames that were dumped in the 2560*4882a593Smuzhiyun * filtering process */ 2561*4882a593Smuzhiyun __le32 non_channel_beacons; /* beacons with our bss id but not on 2562*4882a593Smuzhiyun * our serving channel */ 2563*4882a593Smuzhiyun __le32 channel_beacons; /* beacons with our bss id and in our 2564*4882a593Smuzhiyun * serving channel */ 2565*4882a593Smuzhiyun __le32 num_missed_bcon; /* number of missed beacons */ 2566*4882a593Smuzhiyun __le32 adc_rx_saturation_time; /* count in 0.8us units the time the 2567*4882a593Smuzhiyun * ADC was in saturation */ 2568*4882a593Smuzhiyun __le32 ina_detection_search_time;/* total time (in 0.8us) searched 2569*4882a593Smuzhiyun * for INA */ 2570*4882a593Smuzhiyun __le32 beacon_silence_rssi_a; /* RSSI silence after beacon frame */ 2571*4882a593Smuzhiyun __le32 beacon_silence_rssi_b; /* RSSI silence after beacon frame */ 2572*4882a593Smuzhiyun __le32 beacon_silence_rssi_c; /* RSSI silence after beacon frame */ 2573*4882a593Smuzhiyun __le32 interference_data_flag; /* flag for interference data 2574*4882a593Smuzhiyun * availability. 1 when data is 2575*4882a593Smuzhiyun * available. */ 2576*4882a593Smuzhiyun __le32 channel_load; /* counts RX Enable time in uSec */ 2577*4882a593Smuzhiyun __le32 dsp_false_alarms; /* DSP false alarm (both OFDM 2578*4882a593Smuzhiyun * and CCK) counter */ 2579*4882a593Smuzhiyun __le32 beacon_rssi_a; 2580*4882a593Smuzhiyun __le32 beacon_rssi_b; 2581*4882a593Smuzhiyun __le32 beacon_rssi_c; 2582*4882a593Smuzhiyun __le32 beacon_energy_a; 2583*4882a593Smuzhiyun __le32 beacon_energy_b; 2584*4882a593Smuzhiyun __le32 beacon_energy_c; 2585*4882a593Smuzhiyun } __packed; 2586*4882a593Smuzhiyun 2587*4882a593Smuzhiyun struct statistics_rx_non_phy_bt { 2588*4882a593Smuzhiyun struct statistics_rx_non_phy common; 2589*4882a593Smuzhiyun /* additional stats for bt */ 2590*4882a593Smuzhiyun __le32 num_bt_kills; 2591*4882a593Smuzhiyun __le32 reserved[2]; 2592*4882a593Smuzhiyun } __packed; 2593*4882a593Smuzhiyun 2594*4882a593Smuzhiyun struct statistics_rx { 2595*4882a593Smuzhiyun struct statistics_rx_phy ofdm; 2596*4882a593Smuzhiyun struct statistics_rx_phy cck; 2597*4882a593Smuzhiyun struct statistics_rx_non_phy general; 2598*4882a593Smuzhiyun struct statistics_rx_ht_phy ofdm_ht; 2599*4882a593Smuzhiyun } __packed; 2600*4882a593Smuzhiyun 2601*4882a593Smuzhiyun struct statistics_rx_bt { 2602*4882a593Smuzhiyun struct statistics_rx_phy ofdm; 2603*4882a593Smuzhiyun struct statistics_rx_phy cck; 2604*4882a593Smuzhiyun struct statistics_rx_non_phy_bt general; 2605*4882a593Smuzhiyun struct statistics_rx_ht_phy ofdm_ht; 2606*4882a593Smuzhiyun } __packed; 2607*4882a593Smuzhiyun 2608*4882a593Smuzhiyun /** 2609*4882a593Smuzhiyun * struct statistics_tx_power - current tx power 2610*4882a593Smuzhiyun * 2611*4882a593Smuzhiyun * @ant_a: current tx power on chain a in 1/2 dB step 2612*4882a593Smuzhiyun * @ant_b: current tx power on chain b in 1/2 dB step 2613*4882a593Smuzhiyun * @ant_c: current tx power on chain c in 1/2 dB step 2614*4882a593Smuzhiyun */ 2615*4882a593Smuzhiyun struct statistics_tx_power { 2616*4882a593Smuzhiyun u8 ant_a; 2617*4882a593Smuzhiyun u8 ant_b; 2618*4882a593Smuzhiyun u8 ant_c; 2619*4882a593Smuzhiyun u8 reserved; 2620*4882a593Smuzhiyun } __packed; 2621*4882a593Smuzhiyun 2622*4882a593Smuzhiyun struct statistics_tx_non_phy_agg { 2623*4882a593Smuzhiyun __le32 ba_timeout; 2624*4882a593Smuzhiyun __le32 ba_reschedule_frames; 2625*4882a593Smuzhiyun __le32 scd_query_agg_frame_cnt; 2626*4882a593Smuzhiyun __le32 scd_query_no_agg; 2627*4882a593Smuzhiyun __le32 scd_query_agg; 2628*4882a593Smuzhiyun __le32 scd_query_mismatch; 2629*4882a593Smuzhiyun __le32 frame_not_ready; 2630*4882a593Smuzhiyun __le32 underrun; 2631*4882a593Smuzhiyun __le32 bt_prio_kill; 2632*4882a593Smuzhiyun __le32 rx_ba_rsp_cnt; 2633*4882a593Smuzhiyun } __packed; 2634*4882a593Smuzhiyun 2635*4882a593Smuzhiyun struct statistics_tx { 2636*4882a593Smuzhiyun __le32 preamble_cnt; 2637*4882a593Smuzhiyun __le32 rx_detected_cnt; 2638*4882a593Smuzhiyun __le32 bt_prio_defer_cnt; 2639*4882a593Smuzhiyun __le32 bt_prio_kill_cnt; 2640*4882a593Smuzhiyun __le32 few_bytes_cnt; 2641*4882a593Smuzhiyun __le32 cts_timeout; 2642*4882a593Smuzhiyun __le32 ack_timeout; 2643*4882a593Smuzhiyun __le32 expected_ack_cnt; 2644*4882a593Smuzhiyun __le32 actual_ack_cnt; 2645*4882a593Smuzhiyun __le32 dump_msdu_cnt; 2646*4882a593Smuzhiyun __le32 burst_abort_next_frame_mismatch_cnt; 2647*4882a593Smuzhiyun __le32 burst_abort_missing_next_frame_cnt; 2648*4882a593Smuzhiyun __le32 cts_timeout_collision; 2649*4882a593Smuzhiyun __le32 ack_or_ba_timeout_collision; 2650*4882a593Smuzhiyun struct statistics_tx_non_phy_agg agg; 2651*4882a593Smuzhiyun /* 2652*4882a593Smuzhiyun * "tx_power" are optional parameters provided by uCode, 2653*4882a593Smuzhiyun * 6000 series is the only device provide the information, 2654*4882a593Smuzhiyun * Those are reserved fields for all the other devices 2655*4882a593Smuzhiyun */ 2656*4882a593Smuzhiyun struct statistics_tx_power tx_power; 2657*4882a593Smuzhiyun __le32 reserved1; 2658*4882a593Smuzhiyun } __packed; 2659*4882a593Smuzhiyun 2660*4882a593Smuzhiyun 2661*4882a593Smuzhiyun struct statistics_div { 2662*4882a593Smuzhiyun __le32 tx_on_a; 2663*4882a593Smuzhiyun __le32 tx_on_b; 2664*4882a593Smuzhiyun __le32 exec_time; 2665*4882a593Smuzhiyun __le32 probe_time; 2666*4882a593Smuzhiyun __le32 reserved1; 2667*4882a593Smuzhiyun __le32 reserved2; 2668*4882a593Smuzhiyun } __packed; 2669*4882a593Smuzhiyun 2670*4882a593Smuzhiyun struct statistics_general_common { 2671*4882a593Smuzhiyun __le32 temperature; /* radio temperature */ 2672*4882a593Smuzhiyun __le32 temperature_m; /* radio voltage */ 2673*4882a593Smuzhiyun struct statistics_dbg dbg; 2674*4882a593Smuzhiyun __le32 sleep_time; 2675*4882a593Smuzhiyun __le32 slots_out; 2676*4882a593Smuzhiyun __le32 slots_idle; 2677*4882a593Smuzhiyun __le32 ttl_timestamp; 2678*4882a593Smuzhiyun struct statistics_div div; 2679*4882a593Smuzhiyun __le32 rx_enable_counter; 2680*4882a593Smuzhiyun /* 2681*4882a593Smuzhiyun * num_of_sos_states: 2682*4882a593Smuzhiyun * count the number of times we have to re-tune 2683*4882a593Smuzhiyun * in order to get out of bad PHY status 2684*4882a593Smuzhiyun */ 2685*4882a593Smuzhiyun __le32 num_of_sos_states; 2686*4882a593Smuzhiyun } __packed; 2687*4882a593Smuzhiyun 2688*4882a593Smuzhiyun struct statistics_bt_activity { 2689*4882a593Smuzhiyun /* Tx statistics */ 2690*4882a593Smuzhiyun __le32 hi_priority_tx_req_cnt; 2691*4882a593Smuzhiyun __le32 hi_priority_tx_denied_cnt; 2692*4882a593Smuzhiyun __le32 lo_priority_tx_req_cnt; 2693*4882a593Smuzhiyun __le32 lo_priority_tx_denied_cnt; 2694*4882a593Smuzhiyun /* Rx statistics */ 2695*4882a593Smuzhiyun __le32 hi_priority_rx_req_cnt; 2696*4882a593Smuzhiyun __le32 hi_priority_rx_denied_cnt; 2697*4882a593Smuzhiyun __le32 lo_priority_rx_req_cnt; 2698*4882a593Smuzhiyun __le32 lo_priority_rx_denied_cnt; 2699*4882a593Smuzhiyun } __packed; 2700*4882a593Smuzhiyun 2701*4882a593Smuzhiyun struct statistics_general { 2702*4882a593Smuzhiyun struct statistics_general_common common; 2703*4882a593Smuzhiyun __le32 reserved2; 2704*4882a593Smuzhiyun __le32 reserved3; 2705*4882a593Smuzhiyun } __packed; 2706*4882a593Smuzhiyun 2707*4882a593Smuzhiyun struct statistics_general_bt { 2708*4882a593Smuzhiyun struct statistics_general_common common; 2709*4882a593Smuzhiyun struct statistics_bt_activity activity; 2710*4882a593Smuzhiyun __le32 reserved2; 2711*4882a593Smuzhiyun __le32 reserved3; 2712*4882a593Smuzhiyun } __packed; 2713*4882a593Smuzhiyun 2714*4882a593Smuzhiyun #define UCODE_STATISTICS_CLEAR_MSK (0x1 << 0) 2715*4882a593Smuzhiyun #define UCODE_STATISTICS_FREQUENCY_MSK (0x1 << 1) 2716*4882a593Smuzhiyun #define UCODE_STATISTICS_NARROW_BAND_MSK (0x1 << 2) 2717*4882a593Smuzhiyun 2718*4882a593Smuzhiyun /* 2719*4882a593Smuzhiyun * REPLY_STATISTICS_CMD = 0x9c, 2720*4882a593Smuzhiyun * all devices identical. 2721*4882a593Smuzhiyun * 2722*4882a593Smuzhiyun * This command triggers an immediate response containing uCode statistics. 2723*4882a593Smuzhiyun * The response is in the same format as STATISTICS_NOTIFICATION 0x9d, below. 2724*4882a593Smuzhiyun * 2725*4882a593Smuzhiyun * If the CLEAR_STATS configuration flag is set, uCode will clear its 2726*4882a593Smuzhiyun * internal copy of the statistics (counters) after issuing the response. 2727*4882a593Smuzhiyun * This flag does not affect STATISTICS_NOTIFICATIONs after beacons (see below). 2728*4882a593Smuzhiyun * 2729*4882a593Smuzhiyun * If the DISABLE_NOTIF configuration flag is set, uCode will not issue 2730*4882a593Smuzhiyun * STATISTICS_NOTIFICATIONs after received beacons (see below). This flag 2731*4882a593Smuzhiyun * does not affect the response to the REPLY_STATISTICS_CMD 0x9c itself. 2732*4882a593Smuzhiyun */ 2733*4882a593Smuzhiyun #define IWL_STATS_CONF_CLEAR_STATS cpu_to_le32(0x1) /* see above */ 2734*4882a593Smuzhiyun #define IWL_STATS_CONF_DISABLE_NOTIF cpu_to_le32(0x2)/* see above */ 2735*4882a593Smuzhiyun struct iwl_statistics_cmd { 2736*4882a593Smuzhiyun __le32 configuration_flags; /* IWL_STATS_CONF_* */ 2737*4882a593Smuzhiyun } __packed; 2738*4882a593Smuzhiyun 2739*4882a593Smuzhiyun /* 2740*4882a593Smuzhiyun * STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 2741*4882a593Smuzhiyun * 2742*4882a593Smuzhiyun * By default, uCode issues this notification after receiving a beacon 2743*4882a593Smuzhiyun * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 2744*4882a593Smuzhiyun * REPLY_STATISTICS_CMD 0x9c, above. 2745*4882a593Smuzhiyun * 2746*4882a593Smuzhiyun * Statistics counters continue to increment beacon after beacon, but are 2747*4882a593Smuzhiyun * cleared when changing channels or when driver issues REPLY_STATISTICS_CMD 2748*4882a593Smuzhiyun * 0x9c with CLEAR_STATS bit set (see above). 2749*4882a593Smuzhiyun * 2750*4882a593Smuzhiyun * uCode also issues this notification during scans. uCode clears statistics 2751*4882a593Smuzhiyun * appropriately so that each notification contains statistics for only the 2752*4882a593Smuzhiyun * one channel that has just been scanned. 2753*4882a593Smuzhiyun */ 2754*4882a593Smuzhiyun #define STATISTICS_REPLY_FLG_BAND_24G_MSK cpu_to_le32(0x2) 2755*4882a593Smuzhiyun #define STATISTICS_REPLY_FLG_HT40_MODE_MSK cpu_to_le32(0x8) 2756*4882a593Smuzhiyun 2757*4882a593Smuzhiyun struct iwl_notif_statistics { 2758*4882a593Smuzhiyun __le32 flag; 2759*4882a593Smuzhiyun struct statistics_rx rx; 2760*4882a593Smuzhiyun struct statistics_tx tx; 2761*4882a593Smuzhiyun struct statistics_general general; 2762*4882a593Smuzhiyun } __packed; 2763*4882a593Smuzhiyun 2764*4882a593Smuzhiyun struct iwl_bt_notif_statistics { 2765*4882a593Smuzhiyun __le32 flag; 2766*4882a593Smuzhiyun struct statistics_rx_bt rx; 2767*4882a593Smuzhiyun struct statistics_tx tx; 2768*4882a593Smuzhiyun struct statistics_general_bt general; 2769*4882a593Smuzhiyun } __packed; 2770*4882a593Smuzhiyun 2771*4882a593Smuzhiyun /* 2772*4882a593Smuzhiyun * MISSED_BEACONS_NOTIFICATION = 0xa2 (notification only, not a command) 2773*4882a593Smuzhiyun * 2774*4882a593Smuzhiyun * uCode send MISSED_BEACONS_NOTIFICATION to driver when detect beacon missed 2775*4882a593Smuzhiyun * in regardless of how many missed beacons, which mean when driver receive the 2776*4882a593Smuzhiyun * notification, inside the command, it can find all the beacons information 2777*4882a593Smuzhiyun * which include number of total missed beacons, number of consecutive missed 2778*4882a593Smuzhiyun * beacons, number of beacons received and number of beacons expected to 2779*4882a593Smuzhiyun * receive. 2780*4882a593Smuzhiyun * 2781*4882a593Smuzhiyun * If uCode detected consecutive_missed_beacons > 5, it will reset the radio 2782*4882a593Smuzhiyun * in order to bring the radio/PHY back to working state; which has no relation 2783*4882a593Smuzhiyun * to when driver will perform sensitivity calibration. 2784*4882a593Smuzhiyun * 2785*4882a593Smuzhiyun * Driver should set it own missed_beacon_threshold to decide when to perform 2786*4882a593Smuzhiyun * sensitivity calibration based on number of consecutive missed beacons in 2787*4882a593Smuzhiyun * order to improve overall performance, especially in noisy environment. 2788*4882a593Smuzhiyun * 2789*4882a593Smuzhiyun */ 2790*4882a593Smuzhiyun 2791*4882a593Smuzhiyun #define IWL_MISSED_BEACON_THRESHOLD_MIN (1) 2792*4882a593Smuzhiyun #define IWL_MISSED_BEACON_THRESHOLD_DEF (5) 2793*4882a593Smuzhiyun #define IWL_MISSED_BEACON_THRESHOLD_MAX IWL_MISSED_BEACON_THRESHOLD_DEF 2794*4882a593Smuzhiyun 2795*4882a593Smuzhiyun struct iwl_missed_beacon_notif { 2796*4882a593Smuzhiyun __le32 consecutive_missed_beacons; 2797*4882a593Smuzhiyun __le32 total_missed_becons; 2798*4882a593Smuzhiyun __le32 num_expected_beacons; 2799*4882a593Smuzhiyun __le32 num_recvd_beacons; 2800*4882a593Smuzhiyun } __packed; 2801*4882a593Smuzhiyun 2802*4882a593Smuzhiyun 2803*4882a593Smuzhiyun /****************************************************************************** 2804*4882a593Smuzhiyun * (11) 2805*4882a593Smuzhiyun * Rx Calibration Commands: 2806*4882a593Smuzhiyun * 2807*4882a593Smuzhiyun * With the uCode used for open source drivers, most Tx calibration (except 2808*4882a593Smuzhiyun * for Tx Power) and most Rx calibration is done by uCode during the 2809*4882a593Smuzhiyun * "initialize" phase of uCode boot. Driver must calibrate only: 2810*4882a593Smuzhiyun * 2811*4882a593Smuzhiyun * 1) Tx power (depends on temperature), described elsewhere 2812*4882a593Smuzhiyun * 2) Receiver gain balance (optimize MIMO, and detect disconnected antennas) 2813*4882a593Smuzhiyun * 3) Receiver sensitivity (to optimize signal detection) 2814*4882a593Smuzhiyun * 2815*4882a593Smuzhiyun *****************************************************************************/ 2816*4882a593Smuzhiyun 2817*4882a593Smuzhiyun /** 2818*4882a593Smuzhiyun * SENSITIVITY_CMD = 0xa8 (command, has simple generic response) 2819*4882a593Smuzhiyun * 2820*4882a593Smuzhiyun * This command sets up the Rx signal detector for a sensitivity level that 2821*4882a593Smuzhiyun * is high enough to lock onto all signals within the associated network, 2822*4882a593Smuzhiyun * but low enough to ignore signals that are below a certain threshold, so as 2823*4882a593Smuzhiyun * not to have too many "false alarms". False alarms are signals that the 2824*4882a593Smuzhiyun * Rx DSP tries to lock onto, but then discards after determining that they 2825*4882a593Smuzhiyun * are noise. 2826*4882a593Smuzhiyun * 2827*4882a593Smuzhiyun * The optimum number of false alarms is between 5 and 50 per 200 TUs 2828*4882a593Smuzhiyun * (200 * 1024 uSecs, i.e. 204.8 milliseconds) of actual Rx time (i.e. 2829*4882a593Smuzhiyun * time listening, not transmitting). Driver must adjust sensitivity so that 2830*4882a593Smuzhiyun * the ratio of actual false alarms to actual Rx time falls within this range. 2831*4882a593Smuzhiyun * 2832*4882a593Smuzhiyun * While associated, uCode delivers STATISTICS_NOTIFICATIONs after each 2833*4882a593Smuzhiyun * received beacon. These provide information to the driver to analyze the 2834*4882a593Smuzhiyun * sensitivity. Don't analyze statistics that come in from scanning, or any 2835*4882a593Smuzhiyun * other non-associated-network source. Pertinent statistics include: 2836*4882a593Smuzhiyun * 2837*4882a593Smuzhiyun * From "general" statistics (struct statistics_rx_non_phy): 2838*4882a593Smuzhiyun * 2839*4882a593Smuzhiyun * (beacon_energy_[abc] & 0x0FF00) >> 8 (unsigned, higher value is lower level) 2840*4882a593Smuzhiyun * Measure of energy of desired signal. Used for establishing a level 2841*4882a593Smuzhiyun * below which the device does not detect signals. 2842*4882a593Smuzhiyun * 2843*4882a593Smuzhiyun * (beacon_silence_rssi_[abc] & 0x0FF00) >> 8 (unsigned, units in dB) 2844*4882a593Smuzhiyun * Measure of background noise in silent period after beacon. 2845*4882a593Smuzhiyun * 2846*4882a593Smuzhiyun * channel_load 2847*4882a593Smuzhiyun * uSecs of actual Rx time during beacon period (varies according to 2848*4882a593Smuzhiyun * how much time was spent transmitting). 2849*4882a593Smuzhiyun * 2850*4882a593Smuzhiyun * From "cck" and "ofdm" statistics (struct statistics_rx_phy), separately: 2851*4882a593Smuzhiyun * 2852*4882a593Smuzhiyun * false_alarm_cnt 2853*4882a593Smuzhiyun * Signal locks abandoned early (before phy-level header). 2854*4882a593Smuzhiyun * 2855*4882a593Smuzhiyun * plcp_err 2856*4882a593Smuzhiyun * Signal locks abandoned late (during phy-level header). 2857*4882a593Smuzhiyun * 2858*4882a593Smuzhiyun * NOTE: Both false_alarm_cnt and plcp_err increment monotonically from 2859*4882a593Smuzhiyun * beacon to beacon, i.e. each value is an accumulation of all errors 2860*4882a593Smuzhiyun * before and including the latest beacon. Values will wrap around to 0 2861*4882a593Smuzhiyun * after counting up to 2^32 - 1. Driver must differentiate vs. 2862*4882a593Smuzhiyun * previous beacon's values to determine # false alarms in the current 2863*4882a593Smuzhiyun * beacon period. 2864*4882a593Smuzhiyun * 2865*4882a593Smuzhiyun * Total number of false alarms = false_alarms + plcp_errs 2866*4882a593Smuzhiyun * 2867*4882a593Smuzhiyun * For OFDM, adjust the following table entries in struct iwl_sensitivity_cmd 2868*4882a593Smuzhiyun * (notice that the start points for OFDM are at or close to settings for 2869*4882a593Smuzhiyun * maximum sensitivity): 2870*4882a593Smuzhiyun * 2871*4882a593Smuzhiyun * START / MIN / MAX 2872*4882a593Smuzhiyun * HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX 90 / 85 / 120 2873*4882a593Smuzhiyun * HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX 170 / 170 / 210 2874*4882a593Smuzhiyun * HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX 105 / 105 / 140 2875*4882a593Smuzhiyun * HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX 220 / 220 / 270 2876*4882a593Smuzhiyun * 2877*4882a593Smuzhiyun * If actual rate of OFDM false alarms (+ plcp_errors) is too high 2878*4882a593Smuzhiyun * (greater than 50 for each 204.8 msecs listening), reduce sensitivity 2879*4882a593Smuzhiyun * by *adding* 1 to all 4 of the table entries above, up to the max for 2880*4882a593Smuzhiyun * each entry. Conversely, if false alarm rate is too low (less than 5 2881*4882a593Smuzhiyun * for each 204.8 msecs listening), *subtract* 1 from each entry to 2882*4882a593Smuzhiyun * increase sensitivity. 2883*4882a593Smuzhiyun * 2884*4882a593Smuzhiyun * For CCK sensitivity, keep track of the following: 2885*4882a593Smuzhiyun * 2886*4882a593Smuzhiyun * 1). 20-beacon history of maximum background noise, indicated by 2887*4882a593Smuzhiyun * (beacon_silence_rssi_[abc] & 0x0FF00), units in dB, across the 2888*4882a593Smuzhiyun * 3 receivers. For any given beacon, the "silence reference" is 2889*4882a593Smuzhiyun * the maximum of last 60 samples (20 beacons * 3 receivers). 2890*4882a593Smuzhiyun * 2891*4882a593Smuzhiyun * 2). 10-beacon history of strongest signal level, as indicated 2892*4882a593Smuzhiyun * by (beacon_energy_[abc] & 0x0FF00) >> 8, across the 3 receivers, 2893*4882a593Smuzhiyun * i.e. the strength of the signal through the best receiver at the 2894*4882a593Smuzhiyun * moment. These measurements are "upside down", with lower values 2895*4882a593Smuzhiyun * for stronger signals, so max energy will be *minimum* value. 2896*4882a593Smuzhiyun * 2897*4882a593Smuzhiyun * Then for any given beacon, the driver must determine the *weakest* 2898*4882a593Smuzhiyun * of the strongest signals; this is the minimum level that needs to be 2899*4882a593Smuzhiyun * successfully detected, when using the best receiver at the moment. 2900*4882a593Smuzhiyun * "Max cck energy" is the maximum (higher value means lower energy!) 2901*4882a593Smuzhiyun * of the last 10 minima. Once this is determined, driver must add 2902*4882a593Smuzhiyun * a little margin by adding "6" to it. 2903*4882a593Smuzhiyun * 2904*4882a593Smuzhiyun * 3). Number of consecutive beacon periods with too few false alarms. 2905*4882a593Smuzhiyun * Reset this to 0 at the first beacon period that falls within the 2906*4882a593Smuzhiyun * "good" range (5 to 50 false alarms per 204.8 milliseconds rx). 2907*4882a593Smuzhiyun * 2908*4882a593Smuzhiyun * Then, adjust the following CCK table entries in struct iwl_sensitivity_cmd 2909*4882a593Smuzhiyun * (notice that the start points for CCK are at maximum sensitivity): 2910*4882a593Smuzhiyun * 2911*4882a593Smuzhiyun * START / MIN / MAX 2912*4882a593Smuzhiyun * HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX 125 / 125 / 200 2913*4882a593Smuzhiyun * HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX 200 / 200 / 400 2914*4882a593Smuzhiyun * HD_MIN_ENERGY_CCK_DET_INDEX 100 / 0 / 100 2915*4882a593Smuzhiyun * 2916*4882a593Smuzhiyun * If actual rate of CCK false alarms (+ plcp_errors) is too high 2917*4882a593Smuzhiyun * (greater than 50 for each 204.8 msecs listening), method for reducing 2918*4882a593Smuzhiyun * sensitivity is: 2919*4882a593Smuzhiyun * 2920*4882a593Smuzhiyun * 1) *Add* 3 to value in HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX, 2921*4882a593Smuzhiyun * up to max 400. 2922*4882a593Smuzhiyun * 2923*4882a593Smuzhiyun * 2) If current value in HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX is < 160, 2924*4882a593Smuzhiyun * sensitivity has been reduced a significant amount; bring it up to 2925*4882a593Smuzhiyun * a moderate 161. Otherwise, *add* 3, up to max 200. 2926*4882a593Smuzhiyun * 2927*4882a593Smuzhiyun * 3) a) If current value in HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX is > 160, 2928*4882a593Smuzhiyun * sensitivity has been reduced only a moderate or small amount; 2929*4882a593Smuzhiyun * *subtract* 2 from value in HD_MIN_ENERGY_CCK_DET_INDEX, 2930*4882a593Smuzhiyun * down to min 0. Otherwise (if gain has been significantly reduced), 2931*4882a593Smuzhiyun * don't change the HD_MIN_ENERGY_CCK_DET_INDEX value. 2932*4882a593Smuzhiyun * 2933*4882a593Smuzhiyun * b) Save a snapshot of the "silence reference". 2934*4882a593Smuzhiyun * 2935*4882a593Smuzhiyun * If actual rate of CCK false alarms (+ plcp_errors) is too low 2936*4882a593Smuzhiyun * (less than 5 for each 204.8 msecs listening), method for increasing 2937*4882a593Smuzhiyun * sensitivity is used only if: 2938*4882a593Smuzhiyun * 2939*4882a593Smuzhiyun * 1a) Previous beacon did not have too many false alarms 2940*4882a593Smuzhiyun * 1b) AND difference between previous "silence reference" and current 2941*4882a593Smuzhiyun * "silence reference" (prev - current) is 2 or more, 2942*4882a593Smuzhiyun * OR 2) 100 or more consecutive beacon periods have had rate of 2943*4882a593Smuzhiyun * less than 5 false alarms per 204.8 milliseconds rx time. 2944*4882a593Smuzhiyun * 2945*4882a593Smuzhiyun * Method for increasing sensitivity: 2946*4882a593Smuzhiyun * 2947*4882a593Smuzhiyun * 1) *Subtract* 3 from value in HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX, 2948*4882a593Smuzhiyun * down to min 125. 2949*4882a593Smuzhiyun * 2950*4882a593Smuzhiyun * 2) *Subtract* 3 from value in HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX, 2951*4882a593Smuzhiyun * down to min 200. 2952*4882a593Smuzhiyun * 2953*4882a593Smuzhiyun * 3) *Add* 2 to value in HD_MIN_ENERGY_CCK_DET_INDEX, up to max 100. 2954*4882a593Smuzhiyun * 2955*4882a593Smuzhiyun * If actual rate of CCK false alarms (+ plcp_errors) is within good range 2956*4882a593Smuzhiyun * (between 5 and 50 for each 204.8 msecs listening): 2957*4882a593Smuzhiyun * 2958*4882a593Smuzhiyun * 1) Save a snapshot of the silence reference. 2959*4882a593Smuzhiyun * 2960*4882a593Smuzhiyun * 2) If previous beacon had too many CCK false alarms (+ plcp_errors), 2961*4882a593Smuzhiyun * give some extra margin to energy threshold by *subtracting* 8 2962*4882a593Smuzhiyun * from value in HD_MIN_ENERGY_CCK_DET_INDEX. 2963*4882a593Smuzhiyun * 2964*4882a593Smuzhiyun * For all cases (too few, too many, good range), make sure that the CCK 2965*4882a593Smuzhiyun * detection threshold (energy) is below the energy level for robust 2966*4882a593Smuzhiyun * detection over the past 10 beacon periods, the "Max cck energy". 2967*4882a593Smuzhiyun * Lower values mean higher energy; this means making sure that the value 2968*4882a593Smuzhiyun * in HD_MIN_ENERGY_CCK_DET_INDEX is at or *above* "Max cck energy". 2969*4882a593Smuzhiyun * 2970*4882a593Smuzhiyun */ 2971*4882a593Smuzhiyun 2972*4882a593Smuzhiyun /* 2973*4882a593Smuzhiyun * Table entries in SENSITIVITY_CMD (struct iwl_sensitivity_cmd) 2974*4882a593Smuzhiyun */ 2975*4882a593Smuzhiyun #define HD_TABLE_SIZE (11) /* number of entries */ 2976*4882a593Smuzhiyun #define HD_MIN_ENERGY_CCK_DET_INDEX (0) /* table indexes */ 2977*4882a593Smuzhiyun #define HD_MIN_ENERGY_OFDM_DET_INDEX (1) 2978*4882a593Smuzhiyun #define HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX (2) 2979*4882a593Smuzhiyun #define HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX (3) 2980*4882a593Smuzhiyun #define HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX (4) 2981*4882a593Smuzhiyun #define HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX (5) 2982*4882a593Smuzhiyun #define HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX (6) 2983*4882a593Smuzhiyun #define HD_BARKER_CORR_TH_ADD_MIN_INDEX (7) 2984*4882a593Smuzhiyun #define HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX (8) 2985*4882a593Smuzhiyun #define HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX (9) 2986*4882a593Smuzhiyun #define HD_OFDM_ENERGY_TH_IN_INDEX (10) 2987*4882a593Smuzhiyun 2988*4882a593Smuzhiyun /* 2989*4882a593Smuzhiyun * Additional table entries in enhance SENSITIVITY_CMD 2990*4882a593Smuzhiyun */ 2991*4882a593Smuzhiyun #define HD_INA_NON_SQUARE_DET_OFDM_INDEX (11) 2992*4882a593Smuzhiyun #define HD_INA_NON_SQUARE_DET_CCK_INDEX (12) 2993*4882a593Smuzhiyun #define HD_CORR_11_INSTEAD_OF_CORR_9_EN_INDEX (13) 2994*4882a593Smuzhiyun #define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_INDEX (14) 2995*4882a593Smuzhiyun #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_INDEX (15) 2996*4882a593Smuzhiyun #define HD_OFDM_NON_SQUARE_DET_SLOPE_INDEX (16) 2997*4882a593Smuzhiyun #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_INDEX (17) 2998*4882a593Smuzhiyun #define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_INDEX (18) 2999*4882a593Smuzhiyun #define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_INDEX (19) 3000*4882a593Smuzhiyun #define HD_CCK_NON_SQUARE_DET_SLOPE_INDEX (20) 3001*4882a593Smuzhiyun #define HD_CCK_NON_SQUARE_DET_INTERCEPT_INDEX (21) 3002*4882a593Smuzhiyun #define HD_RESERVED (22) 3003*4882a593Smuzhiyun 3004*4882a593Smuzhiyun /* number of entries for enhanced tbl */ 3005*4882a593Smuzhiyun #define ENHANCE_HD_TABLE_SIZE (23) 3006*4882a593Smuzhiyun 3007*4882a593Smuzhiyun /* number of additional entries for enhanced tbl */ 3008*4882a593Smuzhiyun #define ENHANCE_HD_TABLE_ENTRIES (ENHANCE_HD_TABLE_SIZE - HD_TABLE_SIZE) 3009*4882a593Smuzhiyun 3010*4882a593Smuzhiyun #define HD_INA_NON_SQUARE_DET_OFDM_DATA_V1 cpu_to_le16(0) 3011*4882a593Smuzhiyun #define HD_INA_NON_SQUARE_DET_CCK_DATA_V1 cpu_to_le16(0) 3012*4882a593Smuzhiyun #define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V1 cpu_to_le16(0) 3013*4882a593Smuzhiyun #define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(668) 3014*4882a593Smuzhiyun #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4) 3015*4882a593Smuzhiyun #define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(486) 3016*4882a593Smuzhiyun #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(37) 3017*4882a593Smuzhiyun #define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(853) 3018*4882a593Smuzhiyun #define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4) 3019*4882a593Smuzhiyun #define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(476) 3020*4882a593Smuzhiyun #define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(99) 3021*4882a593Smuzhiyun 3022*4882a593Smuzhiyun #define HD_INA_NON_SQUARE_DET_OFDM_DATA_V2 cpu_to_le16(1) 3023*4882a593Smuzhiyun #define HD_INA_NON_SQUARE_DET_CCK_DATA_V2 cpu_to_le16(1) 3024*4882a593Smuzhiyun #define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V2 cpu_to_le16(1) 3025*4882a593Smuzhiyun #define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(600) 3026*4882a593Smuzhiyun #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(40) 3027*4882a593Smuzhiyun #define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(486) 3028*4882a593Smuzhiyun #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(45) 3029*4882a593Smuzhiyun #define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(853) 3030*4882a593Smuzhiyun #define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(60) 3031*4882a593Smuzhiyun #define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(476) 3032*4882a593Smuzhiyun #define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(99) 3033*4882a593Smuzhiyun 3034*4882a593Smuzhiyun 3035*4882a593Smuzhiyun /* Control field in struct iwl_sensitivity_cmd */ 3036*4882a593Smuzhiyun #define SENSITIVITY_CMD_CONTROL_DEFAULT_TABLE cpu_to_le16(0) 3037*4882a593Smuzhiyun #define SENSITIVITY_CMD_CONTROL_WORK_TABLE cpu_to_le16(1) 3038*4882a593Smuzhiyun 3039*4882a593Smuzhiyun /** 3040*4882a593Smuzhiyun * struct iwl_sensitivity_cmd 3041*4882a593Smuzhiyun * @control: (1) updates working table, (0) updates default table 3042*4882a593Smuzhiyun * @table: energy threshold values, use HD_* as index into table 3043*4882a593Smuzhiyun * 3044*4882a593Smuzhiyun * Always use "1" in "control" to update uCode's working table and DSP. 3045*4882a593Smuzhiyun */ 3046*4882a593Smuzhiyun struct iwl_sensitivity_cmd { 3047*4882a593Smuzhiyun __le16 control; /* always use "1" */ 3048*4882a593Smuzhiyun __le16 table[HD_TABLE_SIZE]; /* use HD_* as index */ 3049*4882a593Smuzhiyun } __packed; 3050*4882a593Smuzhiyun 3051*4882a593Smuzhiyun /* 3052*4882a593Smuzhiyun * 3053*4882a593Smuzhiyun */ 3054*4882a593Smuzhiyun struct iwl_enhance_sensitivity_cmd { 3055*4882a593Smuzhiyun __le16 control; /* always use "1" */ 3056*4882a593Smuzhiyun __le16 enhance_table[ENHANCE_HD_TABLE_SIZE]; /* use HD_* as index */ 3057*4882a593Smuzhiyun } __packed; 3058*4882a593Smuzhiyun 3059*4882a593Smuzhiyun 3060*4882a593Smuzhiyun /** 3061*4882a593Smuzhiyun * REPLY_PHY_CALIBRATION_CMD = 0xb0 (command, has simple generic response) 3062*4882a593Smuzhiyun * 3063*4882a593Smuzhiyun * This command sets the relative gains of agn device's 3 radio receiver chains. 3064*4882a593Smuzhiyun * 3065*4882a593Smuzhiyun * After the first association, driver should accumulate signal and noise 3066*4882a593Smuzhiyun * statistics from the STATISTICS_NOTIFICATIONs that follow the first 20 3067*4882a593Smuzhiyun * beacons from the associated network (don't collect statistics that come 3068*4882a593Smuzhiyun * in from scanning, or any other non-network source). 3069*4882a593Smuzhiyun * 3070*4882a593Smuzhiyun * DISCONNECTED ANTENNA: 3071*4882a593Smuzhiyun * 3072*4882a593Smuzhiyun * Driver should determine which antennas are actually connected, by comparing 3073*4882a593Smuzhiyun * average beacon signal levels for the 3 Rx chains. Accumulate (add) the 3074*4882a593Smuzhiyun * following values over 20 beacons, one accumulator for each of the chains 3075*4882a593Smuzhiyun * a/b/c, from struct statistics_rx_non_phy: 3076*4882a593Smuzhiyun * 3077*4882a593Smuzhiyun * beacon_rssi_[abc] & 0x0FF (unsigned, units in dB) 3078*4882a593Smuzhiyun * 3079*4882a593Smuzhiyun * Find the strongest signal from among a/b/c. Compare the other two to the 3080*4882a593Smuzhiyun * strongest. If any signal is more than 15 dB (times 20, unless you 3081*4882a593Smuzhiyun * divide the accumulated values by 20) below the strongest, the driver 3082*4882a593Smuzhiyun * considers that antenna to be disconnected, and should not try to use that 3083*4882a593Smuzhiyun * antenna/chain for Rx or Tx. If both A and B seem to be disconnected, 3084*4882a593Smuzhiyun * driver should declare the stronger one as connected, and attempt to use it 3085*4882a593Smuzhiyun * (A and B are the only 2 Tx chains!). 3086*4882a593Smuzhiyun * 3087*4882a593Smuzhiyun * 3088*4882a593Smuzhiyun * RX BALANCE: 3089*4882a593Smuzhiyun * 3090*4882a593Smuzhiyun * Driver should balance the 3 receivers (but just the ones that are connected 3091*4882a593Smuzhiyun * to antennas, see above) for gain, by comparing the average signal levels 3092*4882a593Smuzhiyun * detected during the silence after each beacon (background noise). 3093*4882a593Smuzhiyun * Accumulate (add) the following values over 20 beacons, one accumulator for 3094*4882a593Smuzhiyun * each of the chains a/b/c, from struct statistics_rx_non_phy: 3095*4882a593Smuzhiyun * 3096*4882a593Smuzhiyun * beacon_silence_rssi_[abc] & 0x0FF (unsigned, units in dB) 3097*4882a593Smuzhiyun * 3098*4882a593Smuzhiyun * Find the weakest background noise level from among a/b/c. This Rx chain 3099*4882a593Smuzhiyun * will be the reference, with 0 gain adjustment. Attenuate other channels by 3100*4882a593Smuzhiyun * finding noise difference: 3101*4882a593Smuzhiyun * 3102*4882a593Smuzhiyun * (accum_noise[i] - accum_noise[reference]) / 30 3103*4882a593Smuzhiyun * 3104*4882a593Smuzhiyun * The "30" adjusts the dB in the 20 accumulated samples to units of 1.5 dB. 3105*4882a593Smuzhiyun * For use in diff_gain_[abc] fields of struct iwl_calibration_cmd, the 3106*4882a593Smuzhiyun * driver should limit the difference results to a range of 0-3 (0-4.5 dB), 3107*4882a593Smuzhiyun * and set bit 2 to indicate "reduce gain". The value for the reference 3108*4882a593Smuzhiyun * (weakest) chain should be "0". 3109*4882a593Smuzhiyun * 3110*4882a593Smuzhiyun * diff_gain_[abc] bit fields: 3111*4882a593Smuzhiyun * 2: (1) reduce gain, (0) increase gain 3112*4882a593Smuzhiyun * 1-0: amount of gain, units of 1.5 dB 3113*4882a593Smuzhiyun */ 3114*4882a593Smuzhiyun 3115*4882a593Smuzhiyun /* Phy calibration command for series */ 3116*4882a593Smuzhiyun enum { 3117*4882a593Smuzhiyun IWL_PHY_CALIBRATE_DC_CMD = 8, 3118*4882a593Smuzhiyun IWL_PHY_CALIBRATE_LO_CMD = 9, 3119*4882a593Smuzhiyun IWL_PHY_CALIBRATE_TX_IQ_CMD = 11, 3120*4882a593Smuzhiyun IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD = 15, 3121*4882a593Smuzhiyun IWL_PHY_CALIBRATE_BASE_BAND_CMD = 16, 3122*4882a593Smuzhiyun IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD = 17, 3123*4882a593Smuzhiyun IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD = 18, 3124*4882a593Smuzhiyun }; 3125*4882a593Smuzhiyun 3126*4882a593Smuzhiyun /* This enum defines the bitmap of various calibrations to enable in both 3127*4882a593Smuzhiyun * init ucode and runtime ucode through CALIBRATION_CFG_CMD. 3128*4882a593Smuzhiyun */ 3129*4882a593Smuzhiyun enum iwl_ucode_calib_cfg { 3130*4882a593Smuzhiyun IWL_CALIB_CFG_RX_BB_IDX = BIT(0), 3131*4882a593Smuzhiyun IWL_CALIB_CFG_DC_IDX = BIT(1), 3132*4882a593Smuzhiyun IWL_CALIB_CFG_LO_IDX = BIT(2), 3133*4882a593Smuzhiyun IWL_CALIB_CFG_TX_IQ_IDX = BIT(3), 3134*4882a593Smuzhiyun IWL_CALIB_CFG_RX_IQ_IDX = BIT(4), 3135*4882a593Smuzhiyun IWL_CALIB_CFG_NOISE_IDX = BIT(5), 3136*4882a593Smuzhiyun IWL_CALIB_CFG_CRYSTAL_IDX = BIT(6), 3137*4882a593Smuzhiyun IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(7), 3138*4882a593Smuzhiyun IWL_CALIB_CFG_PAPD_IDX = BIT(8), 3139*4882a593Smuzhiyun IWL_CALIB_CFG_SENSITIVITY_IDX = BIT(9), 3140*4882a593Smuzhiyun IWL_CALIB_CFG_TX_PWR_IDX = BIT(10), 3141*4882a593Smuzhiyun }; 3142*4882a593Smuzhiyun 3143*4882a593Smuzhiyun #define IWL_CALIB_INIT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \ 3144*4882a593Smuzhiyun IWL_CALIB_CFG_DC_IDX | \ 3145*4882a593Smuzhiyun IWL_CALIB_CFG_LO_IDX | \ 3146*4882a593Smuzhiyun IWL_CALIB_CFG_TX_IQ_IDX | \ 3147*4882a593Smuzhiyun IWL_CALIB_CFG_RX_IQ_IDX | \ 3148*4882a593Smuzhiyun IWL_CALIB_CFG_CRYSTAL_IDX) 3149*4882a593Smuzhiyun 3150*4882a593Smuzhiyun #define IWL_CALIB_RT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \ 3151*4882a593Smuzhiyun IWL_CALIB_CFG_DC_IDX | \ 3152*4882a593Smuzhiyun IWL_CALIB_CFG_LO_IDX | \ 3153*4882a593Smuzhiyun IWL_CALIB_CFG_TX_IQ_IDX | \ 3154*4882a593Smuzhiyun IWL_CALIB_CFG_RX_IQ_IDX | \ 3155*4882a593Smuzhiyun IWL_CALIB_CFG_TEMPERATURE_IDX | \ 3156*4882a593Smuzhiyun IWL_CALIB_CFG_PAPD_IDX | \ 3157*4882a593Smuzhiyun IWL_CALIB_CFG_TX_PWR_IDX | \ 3158*4882a593Smuzhiyun IWL_CALIB_CFG_CRYSTAL_IDX) 3159*4882a593Smuzhiyun 3160*4882a593Smuzhiyun #define IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK cpu_to_le32(BIT(0)) 3161*4882a593Smuzhiyun 3162*4882a593Smuzhiyun struct iwl_calib_cfg_elmnt_s { 3163*4882a593Smuzhiyun __le32 is_enable; 3164*4882a593Smuzhiyun __le32 start; 3165*4882a593Smuzhiyun __le32 send_res; 3166*4882a593Smuzhiyun __le32 apply_res; 3167*4882a593Smuzhiyun __le32 reserved; 3168*4882a593Smuzhiyun } __packed; 3169*4882a593Smuzhiyun 3170*4882a593Smuzhiyun struct iwl_calib_cfg_status_s { 3171*4882a593Smuzhiyun struct iwl_calib_cfg_elmnt_s once; 3172*4882a593Smuzhiyun struct iwl_calib_cfg_elmnt_s perd; 3173*4882a593Smuzhiyun __le32 flags; 3174*4882a593Smuzhiyun } __packed; 3175*4882a593Smuzhiyun 3176*4882a593Smuzhiyun struct iwl_calib_cfg_cmd { 3177*4882a593Smuzhiyun struct iwl_calib_cfg_status_s ucd_calib_cfg; 3178*4882a593Smuzhiyun struct iwl_calib_cfg_status_s drv_calib_cfg; 3179*4882a593Smuzhiyun __le32 reserved1; 3180*4882a593Smuzhiyun } __packed; 3181*4882a593Smuzhiyun 3182*4882a593Smuzhiyun struct iwl_calib_hdr { 3183*4882a593Smuzhiyun u8 op_code; 3184*4882a593Smuzhiyun u8 first_group; 3185*4882a593Smuzhiyun u8 groups_num; 3186*4882a593Smuzhiyun u8 data_valid; 3187*4882a593Smuzhiyun } __packed; 3188*4882a593Smuzhiyun 3189*4882a593Smuzhiyun struct iwl_calib_cmd { 3190*4882a593Smuzhiyun struct iwl_calib_hdr hdr; 3191*4882a593Smuzhiyun u8 data[]; 3192*4882a593Smuzhiyun } __packed; 3193*4882a593Smuzhiyun 3194*4882a593Smuzhiyun struct iwl_calib_xtal_freq_cmd { 3195*4882a593Smuzhiyun struct iwl_calib_hdr hdr; 3196*4882a593Smuzhiyun u8 cap_pin1; 3197*4882a593Smuzhiyun u8 cap_pin2; 3198*4882a593Smuzhiyun u8 pad[2]; 3199*4882a593Smuzhiyun } __packed; 3200*4882a593Smuzhiyun 3201*4882a593Smuzhiyun #define DEFAULT_RADIO_SENSOR_OFFSET cpu_to_le16(2700) 3202*4882a593Smuzhiyun struct iwl_calib_temperature_offset_cmd { 3203*4882a593Smuzhiyun struct iwl_calib_hdr hdr; 3204*4882a593Smuzhiyun __le16 radio_sensor_offset; 3205*4882a593Smuzhiyun __le16 reserved; 3206*4882a593Smuzhiyun } __packed; 3207*4882a593Smuzhiyun 3208*4882a593Smuzhiyun struct iwl_calib_temperature_offset_v2_cmd { 3209*4882a593Smuzhiyun struct iwl_calib_hdr hdr; 3210*4882a593Smuzhiyun __le16 radio_sensor_offset_high; 3211*4882a593Smuzhiyun __le16 radio_sensor_offset_low; 3212*4882a593Smuzhiyun __le16 burntVoltageRef; 3213*4882a593Smuzhiyun __le16 reserved; 3214*4882a593Smuzhiyun } __packed; 3215*4882a593Smuzhiyun 3216*4882a593Smuzhiyun /* IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD */ 3217*4882a593Smuzhiyun struct iwl_calib_chain_noise_reset_cmd { 3218*4882a593Smuzhiyun struct iwl_calib_hdr hdr; 3219*4882a593Smuzhiyun u8 data[]; 3220*4882a593Smuzhiyun }; 3221*4882a593Smuzhiyun 3222*4882a593Smuzhiyun /* IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD */ 3223*4882a593Smuzhiyun struct iwl_calib_chain_noise_gain_cmd { 3224*4882a593Smuzhiyun struct iwl_calib_hdr hdr; 3225*4882a593Smuzhiyun u8 delta_gain_1; 3226*4882a593Smuzhiyun u8 delta_gain_2; 3227*4882a593Smuzhiyun u8 pad[2]; 3228*4882a593Smuzhiyun } __packed; 3229*4882a593Smuzhiyun 3230*4882a593Smuzhiyun /****************************************************************************** 3231*4882a593Smuzhiyun * (12) 3232*4882a593Smuzhiyun * Miscellaneous Commands: 3233*4882a593Smuzhiyun * 3234*4882a593Smuzhiyun *****************************************************************************/ 3235*4882a593Smuzhiyun 3236*4882a593Smuzhiyun /* 3237*4882a593Smuzhiyun * LEDs Command & Response 3238*4882a593Smuzhiyun * REPLY_LEDS_CMD = 0x48 (command, has simple generic response) 3239*4882a593Smuzhiyun * 3240*4882a593Smuzhiyun * For each of 3 possible LEDs (Activity/Link/Tech, selected by "id" field), 3241*4882a593Smuzhiyun * this command turns it on or off, or sets up a periodic blinking cycle. 3242*4882a593Smuzhiyun */ 3243*4882a593Smuzhiyun struct iwl_led_cmd { 3244*4882a593Smuzhiyun __le32 interval; /* "interval" in uSec */ 3245*4882a593Smuzhiyun u8 id; /* 1: Activity, 2: Link, 3: Tech */ 3246*4882a593Smuzhiyun u8 off; /* # intervals off while blinking; 3247*4882a593Smuzhiyun * "0", with >0 "on" value, turns LED on */ 3248*4882a593Smuzhiyun u8 on; /* # intervals on while blinking; 3249*4882a593Smuzhiyun * "0", regardless of "off", turns LED off */ 3250*4882a593Smuzhiyun u8 reserved; 3251*4882a593Smuzhiyun } __packed; 3252*4882a593Smuzhiyun 3253*4882a593Smuzhiyun /* 3254*4882a593Smuzhiyun * station priority table entries 3255*4882a593Smuzhiyun * also used as potential "events" value for both 3256*4882a593Smuzhiyun * COEX_MEDIUM_NOTIFICATION and COEX_EVENT_CMD 3257*4882a593Smuzhiyun */ 3258*4882a593Smuzhiyun 3259*4882a593Smuzhiyun /* 3260*4882a593Smuzhiyun * COEX events entry flag masks 3261*4882a593Smuzhiyun * RP - Requested Priority 3262*4882a593Smuzhiyun * WP - Win Medium Priority: priority assigned when the contention has been won 3263*4882a593Smuzhiyun */ 3264*4882a593Smuzhiyun #define COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG (0x1) 3265*4882a593Smuzhiyun #define COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG (0x2) 3266*4882a593Smuzhiyun #define COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG (0x4) 3267*4882a593Smuzhiyun 3268*4882a593Smuzhiyun #define COEX_CU_UNASSOC_IDLE_RP 4 3269*4882a593Smuzhiyun #define COEX_CU_UNASSOC_MANUAL_SCAN_RP 4 3270*4882a593Smuzhiyun #define COEX_CU_UNASSOC_AUTO_SCAN_RP 4 3271*4882a593Smuzhiyun #define COEX_CU_CALIBRATION_RP 4 3272*4882a593Smuzhiyun #define COEX_CU_PERIODIC_CALIBRATION_RP 4 3273*4882a593Smuzhiyun #define COEX_CU_CONNECTION_ESTAB_RP 4 3274*4882a593Smuzhiyun #define COEX_CU_ASSOCIATED_IDLE_RP 4 3275*4882a593Smuzhiyun #define COEX_CU_ASSOC_MANUAL_SCAN_RP 4 3276*4882a593Smuzhiyun #define COEX_CU_ASSOC_AUTO_SCAN_RP 4 3277*4882a593Smuzhiyun #define COEX_CU_ASSOC_ACTIVE_LEVEL_RP 4 3278*4882a593Smuzhiyun #define COEX_CU_RF_ON_RP 6 3279*4882a593Smuzhiyun #define COEX_CU_RF_OFF_RP 4 3280*4882a593Smuzhiyun #define COEX_CU_STAND_ALONE_DEBUG_RP 6 3281*4882a593Smuzhiyun #define COEX_CU_IPAN_ASSOC_LEVEL_RP 4 3282*4882a593Smuzhiyun #define COEX_CU_RSRVD1_RP 4 3283*4882a593Smuzhiyun #define COEX_CU_RSRVD2_RP 4 3284*4882a593Smuzhiyun 3285*4882a593Smuzhiyun #define COEX_CU_UNASSOC_IDLE_WP 3 3286*4882a593Smuzhiyun #define COEX_CU_UNASSOC_MANUAL_SCAN_WP 3 3287*4882a593Smuzhiyun #define COEX_CU_UNASSOC_AUTO_SCAN_WP 3 3288*4882a593Smuzhiyun #define COEX_CU_CALIBRATION_WP 3 3289*4882a593Smuzhiyun #define COEX_CU_PERIODIC_CALIBRATION_WP 3 3290*4882a593Smuzhiyun #define COEX_CU_CONNECTION_ESTAB_WP 3 3291*4882a593Smuzhiyun #define COEX_CU_ASSOCIATED_IDLE_WP 3 3292*4882a593Smuzhiyun #define COEX_CU_ASSOC_MANUAL_SCAN_WP 3 3293*4882a593Smuzhiyun #define COEX_CU_ASSOC_AUTO_SCAN_WP 3 3294*4882a593Smuzhiyun #define COEX_CU_ASSOC_ACTIVE_LEVEL_WP 3 3295*4882a593Smuzhiyun #define COEX_CU_RF_ON_WP 3 3296*4882a593Smuzhiyun #define COEX_CU_RF_OFF_WP 3 3297*4882a593Smuzhiyun #define COEX_CU_STAND_ALONE_DEBUG_WP 6 3298*4882a593Smuzhiyun #define COEX_CU_IPAN_ASSOC_LEVEL_WP 3 3299*4882a593Smuzhiyun #define COEX_CU_RSRVD1_WP 3 3300*4882a593Smuzhiyun #define COEX_CU_RSRVD2_WP 3 3301*4882a593Smuzhiyun 3302*4882a593Smuzhiyun #define COEX_UNASSOC_IDLE_FLAGS 0 3303*4882a593Smuzhiyun #define COEX_UNASSOC_MANUAL_SCAN_FLAGS \ 3304*4882a593Smuzhiyun (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \ 3305*4882a593Smuzhiyun COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG) 3306*4882a593Smuzhiyun #define COEX_UNASSOC_AUTO_SCAN_FLAGS \ 3307*4882a593Smuzhiyun (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \ 3308*4882a593Smuzhiyun COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG) 3309*4882a593Smuzhiyun #define COEX_CALIBRATION_FLAGS \ 3310*4882a593Smuzhiyun (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \ 3311*4882a593Smuzhiyun COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG) 3312*4882a593Smuzhiyun #define COEX_PERIODIC_CALIBRATION_FLAGS 0 3313*4882a593Smuzhiyun /* 3314*4882a593Smuzhiyun * COEX_CONNECTION_ESTAB: 3315*4882a593Smuzhiyun * we need DELAY_MEDIUM_FREE_NTFY to let WiMAX disconnect from network. 3316*4882a593Smuzhiyun */ 3317*4882a593Smuzhiyun #define COEX_CONNECTION_ESTAB_FLAGS \ 3318*4882a593Smuzhiyun (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \ 3319*4882a593Smuzhiyun COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \ 3320*4882a593Smuzhiyun COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG) 3321*4882a593Smuzhiyun #define COEX_ASSOCIATED_IDLE_FLAGS 0 3322*4882a593Smuzhiyun #define COEX_ASSOC_MANUAL_SCAN_FLAGS \ 3323*4882a593Smuzhiyun (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \ 3324*4882a593Smuzhiyun COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG) 3325*4882a593Smuzhiyun #define COEX_ASSOC_AUTO_SCAN_FLAGS \ 3326*4882a593Smuzhiyun (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \ 3327*4882a593Smuzhiyun COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG) 3328*4882a593Smuzhiyun #define COEX_ASSOC_ACTIVE_LEVEL_FLAGS 0 3329*4882a593Smuzhiyun #define COEX_RF_ON_FLAGS 0 3330*4882a593Smuzhiyun #define COEX_RF_OFF_FLAGS 0 3331*4882a593Smuzhiyun #define COEX_STAND_ALONE_DEBUG_FLAGS \ 3332*4882a593Smuzhiyun (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \ 3333*4882a593Smuzhiyun COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG) 3334*4882a593Smuzhiyun #define COEX_IPAN_ASSOC_LEVEL_FLAGS \ 3335*4882a593Smuzhiyun (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \ 3336*4882a593Smuzhiyun COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \ 3337*4882a593Smuzhiyun COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG) 3338*4882a593Smuzhiyun #define COEX_RSRVD1_FLAGS 0 3339*4882a593Smuzhiyun #define COEX_RSRVD2_FLAGS 0 3340*4882a593Smuzhiyun /* 3341*4882a593Smuzhiyun * COEX_CU_RF_ON is the event wrapping all radio ownership. 3342*4882a593Smuzhiyun * We need DELAY_MEDIUM_FREE_NTFY to let WiMAX disconnect from network. 3343*4882a593Smuzhiyun */ 3344*4882a593Smuzhiyun #define COEX_CU_RF_ON_FLAGS \ 3345*4882a593Smuzhiyun (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \ 3346*4882a593Smuzhiyun COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \ 3347*4882a593Smuzhiyun COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG) 3348*4882a593Smuzhiyun 3349*4882a593Smuzhiyun 3350*4882a593Smuzhiyun enum { 3351*4882a593Smuzhiyun /* un-association part */ 3352*4882a593Smuzhiyun COEX_UNASSOC_IDLE = 0, 3353*4882a593Smuzhiyun COEX_UNASSOC_MANUAL_SCAN = 1, 3354*4882a593Smuzhiyun COEX_UNASSOC_AUTO_SCAN = 2, 3355*4882a593Smuzhiyun /* calibration */ 3356*4882a593Smuzhiyun COEX_CALIBRATION = 3, 3357*4882a593Smuzhiyun COEX_PERIODIC_CALIBRATION = 4, 3358*4882a593Smuzhiyun /* connection */ 3359*4882a593Smuzhiyun COEX_CONNECTION_ESTAB = 5, 3360*4882a593Smuzhiyun /* association part */ 3361*4882a593Smuzhiyun COEX_ASSOCIATED_IDLE = 6, 3362*4882a593Smuzhiyun COEX_ASSOC_MANUAL_SCAN = 7, 3363*4882a593Smuzhiyun COEX_ASSOC_AUTO_SCAN = 8, 3364*4882a593Smuzhiyun COEX_ASSOC_ACTIVE_LEVEL = 9, 3365*4882a593Smuzhiyun /* RF ON/OFF */ 3366*4882a593Smuzhiyun COEX_RF_ON = 10, 3367*4882a593Smuzhiyun COEX_RF_OFF = 11, 3368*4882a593Smuzhiyun COEX_STAND_ALONE_DEBUG = 12, 3369*4882a593Smuzhiyun /* IPAN */ 3370*4882a593Smuzhiyun COEX_IPAN_ASSOC_LEVEL = 13, 3371*4882a593Smuzhiyun /* reserved */ 3372*4882a593Smuzhiyun COEX_RSRVD1 = 14, 3373*4882a593Smuzhiyun COEX_RSRVD2 = 15, 3374*4882a593Smuzhiyun COEX_NUM_OF_EVENTS = 16 3375*4882a593Smuzhiyun }; 3376*4882a593Smuzhiyun 3377*4882a593Smuzhiyun /* 3378*4882a593Smuzhiyun * Coexistence WIFI/WIMAX Command 3379*4882a593Smuzhiyun * COEX_PRIORITY_TABLE_CMD = 0x5a 3380*4882a593Smuzhiyun * 3381*4882a593Smuzhiyun */ 3382*4882a593Smuzhiyun struct iwl_wimax_coex_event_entry { 3383*4882a593Smuzhiyun u8 request_prio; 3384*4882a593Smuzhiyun u8 win_medium_prio; 3385*4882a593Smuzhiyun u8 reserved; 3386*4882a593Smuzhiyun u8 flags; 3387*4882a593Smuzhiyun } __packed; 3388*4882a593Smuzhiyun 3389*4882a593Smuzhiyun /* COEX flag masks */ 3390*4882a593Smuzhiyun 3391*4882a593Smuzhiyun /* Station table is valid */ 3392*4882a593Smuzhiyun #define COEX_FLAGS_STA_TABLE_VALID_MSK (0x1) 3393*4882a593Smuzhiyun /* UnMask wake up src at unassociated sleep */ 3394*4882a593Smuzhiyun #define COEX_FLAGS_UNASSOC_WA_UNMASK_MSK (0x4) 3395*4882a593Smuzhiyun /* UnMask wake up src at associated sleep */ 3396*4882a593Smuzhiyun #define COEX_FLAGS_ASSOC_WA_UNMASK_MSK (0x8) 3397*4882a593Smuzhiyun /* Enable CoEx feature. */ 3398*4882a593Smuzhiyun #define COEX_FLAGS_COEX_ENABLE_MSK (0x80) 3399*4882a593Smuzhiyun 3400*4882a593Smuzhiyun struct iwl_wimax_coex_cmd { 3401*4882a593Smuzhiyun u8 flags; 3402*4882a593Smuzhiyun u8 reserved[3]; 3403*4882a593Smuzhiyun struct iwl_wimax_coex_event_entry sta_prio[COEX_NUM_OF_EVENTS]; 3404*4882a593Smuzhiyun } __packed; 3405*4882a593Smuzhiyun 3406*4882a593Smuzhiyun /* 3407*4882a593Smuzhiyun * Coexistence MEDIUM NOTIFICATION 3408*4882a593Smuzhiyun * COEX_MEDIUM_NOTIFICATION = 0x5b 3409*4882a593Smuzhiyun * 3410*4882a593Smuzhiyun * notification from uCode to host to indicate medium changes 3411*4882a593Smuzhiyun * 3412*4882a593Smuzhiyun */ 3413*4882a593Smuzhiyun /* 3414*4882a593Smuzhiyun * status field 3415*4882a593Smuzhiyun * bit 0 - 2: medium status 3416*4882a593Smuzhiyun * bit 3: medium change indication 3417*4882a593Smuzhiyun * bit 4 - 31: reserved 3418*4882a593Smuzhiyun */ 3419*4882a593Smuzhiyun /* status option values, (0 - 2 bits) */ 3420*4882a593Smuzhiyun #define COEX_MEDIUM_BUSY (0x0) /* radio belongs to WiMAX */ 3421*4882a593Smuzhiyun #define COEX_MEDIUM_ACTIVE (0x1) /* radio belongs to WiFi */ 3422*4882a593Smuzhiyun #define COEX_MEDIUM_PRE_RELEASE (0x2) /* received radio release */ 3423*4882a593Smuzhiyun #define COEX_MEDIUM_MSK (0x7) 3424*4882a593Smuzhiyun 3425*4882a593Smuzhiyun /* send notification status (1 bit) */ 3426*4882a593Smuzhiyun #define COEX_MEDIUM_CHANGED (0x8) 3427*4882a593Smuzhiyun #define COEX_MEDIUM_CHANGED_MSK (0x8) 3428*4882a593Smuzhiyun #define COEX_MEDIUM_SHIFT (3) 3429*4882a593Smuzhiyun 3430*4882a593Smuzhiyun struct iwl_coex_medium_notification { 3431*4882a593Smuzhiyun __le32 status; 3432*4882a593Smuzhiyun __le32 events; 3433*4882a593Smuzhiyun } __packed; 3434*4882a593Smuzhiyun 3435*4882a593Smuzhiyun /* 3436*4882a593Smuzhiyun * Coexistence EVENT Command 3437*4882a593Smuzhiyun * COEX_EVENT_CMD = 0x5c 3438*4882a593Smuzhiyun * 3439*4882a593Smuzhiyun * send from host to uCode for coex event request. 3440*4882a593Smuzhiyun */ 3441*4882a593Smuzhiyun /* flags options */ 3442*4882a593Smuzhiyun #define COEX_EVENT_REQUEST_MSK (0x1) 3443*4882a593Smuzhiyun 3444*4882a593Smuzhiyun struct iwl_coex_event_cmd { 3445*4882a593Smuzhiyun u8 flags; 3446*4882a593Smuzhiyun u8 event; 3447*4882a593Smuzhiyun __le16 reserved; 3448*4882a593Smuzhiyun } __packed; 3449*4882a593Smuzhiyun 3450*4882a593Smuzhiyun struct iwl_coex_event_resp { 3451*4882a593Smuzhiyun __le32 status; 3452*4882a593Smuzhiyun } __packed; 3453*4882a593Smuzhiyun 3454*4882a593Smuzhiyun 3455*4882a593Smuzhiyun /****************************************************************************** 3456*4882a593Smuzhiyun * Bluetooth Coexistence commands 3457*4882a593Smuzhiyun * 3458*4882a593Smuzhiyun *****************************************************************************/ 3459*4882a593Smuzhiyun 3460*4882a593Smuzhiyun /* 3461*4882a593Smuzhiyun * BT Status notification 3462*4882a593Smuzhiyun * REPLY_BT_COEX_PROFILE_NOTIF = 0xce 3463*4882a593Smuzhiyun */ 3464*4882a593Smuzhiyun enum iwl_bt_coex_profile_traffic_load { 3465*4882a593Smuzhiyun IWL_BT_COEX_TRAFFIC_LOAD_NONE = 0, 3466*4882a593Smuzhiyun IWL_BT_COEX_TRAFFIC_LOAD_LOW = 1, 3467*4882a593Smuzhiyun IWL_BT_COEX_TRAFFIC_LOAD_HIGH = 2, 3468*4882a593Smuzhiyun IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS = 3, 3469*4882a593Smuzhiyun /* 3470*4882a593Smuzhiyun * There are no more even though below is a u8, the 3471*4882a593Smuzhiyun * indication from the BT device only has two bits. 3472*4882a593Smuzhiyun */ 3473*4882a593Smuzhiyun }; 3474*4882a593Smuzhiyun 3475*4882a593Smuzhiyun #define BT_SESSION_ACTIVITY_1_UART_MSG 0x1 3476*4882a593Smuzhiyun #define BT_SESSION_ACTIVITY_2_UART_MSG 0x2 3477*4882a593Smuzhiyun 3478*4882a593Smuzhiyun /* BT UART message - Share Part (BT -> WiFi) */ 3479*4882a593Smuzhiyun #define BT_UART_MSG_FRAME1MSGTYPE_POS (0) 3480*4882a593Smuzhiyun #define BT_UART_MSG_FRAME1MSGTYPE_MSK \ 3481*4882a593Smuzhiyun (0x7 << BT_UART_MSG_FRAME1MSGTYPE_POS) 3482*4882a593Smuzhiyun #define BT_UART_MSG_FRAME1SSN_POS (3) 3483*4882a593Smuzhiyun #define BT_UART_MSG_FRAME1SSN_MSK \ 3484*4882a593Smuzhiyun (0x3 << BT_UART_MSG_FRAME1SSN_POS) 3485*4882a593Smuzhiyun #define BT_UART_MSG_FRAME1UPDATEREQ_POS (5) 3486*4882a593Smuzhiyun #define BT_UART_MSG_FRAME1UPDATEREQ_MSK \ 3487*4882a593Smuzhiyun (0x1 << BT_UART_MSG_FRAME1UPDATEREQ_POS) 3488*4882a593Smuzhiyun #define BT_UART_MSG_FRAME1RESERVED_POS (6) 3489*4882a593Smuzhiyun #define BT_UART_MSG_FRAME1RESERVED_MSK \ 3490*4882a593Smuzhiyun (0x3 << BT_UART_MSG_FRAME1RESERVED_POS) 3491*4882a593Smuzhiyun 3492*4882a593Smuzhiyun #define BT_UART_MSG_FRAME2OPENCONNECTIONS_POS (0) 3493*4882a593Smuzhiyun #define BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK \ 3494*4882a593Smuzhiyun (0x3 << BT_UART_MSG_FRAME2OPENCONNECTIONS_POS) 3495*4882a593Smuzhiyun #define BT_UART_MSG_FRAME2TRAFFICLOAD_POS (2) 3496*4882a593Smuzhiyun #define BT_UART_MSG_FRAME2TRAFFICLOAD_MSK \ 3497*4882a593Smuzhiyun (0x3 << BT_UART_MSG_FRAME2TRAFFICLOAD_POS) 3498*4882a593Smuzhiyun #define BT_UART_MSG_FRAME2CHLSEQN_POS (4) 3499*4882a593Smuzhiyun #define BT_UART_MSG_FRAME2CHLSEQN_MSK \ 3500*4882a593Smuzhiyun (0x1 << BT_UART_MSG_FRAME2CHLSEQN_POS) 3501*4882a593Smuzhiyun #define BT_UART_MSG_FRAME2INBAND_POS (5) 3502*4882a593Smuzhiyun #define BT_UART_MSG_FRAME2INBAND_MSK \ 3503*4882a593Smuzhiyun (0x1 << BT_UART_MSG_FRAME2INBAND_POS) 3504*4882a593Smuzhiyun #define BT_UART_MSG_FRAME2RESERVED_POS (6) 3505*4882a593Smuzhiyun #define BT_UART_MSG_FRAME2RESERVED_MSK \ 3506*4882a593Smuzhiyun (0x3 << BT_UART_MSG_FRAME2RESERVED_POS) 3507*4882a593Smuzhiyun 3508*4882a593Smuzhiyun #define BT_UART_MSG_FRAME3SCOESCO_POS (0) 3509*4882a593Smuzhiyun #define BT_UART_MSG_FRAME3SCOESCO_MSK \ 3510*4882a593Smuzhiyun (0x1 << BT_UART_MSG_FRAME3SCOESCO_POS) 3511*4882a593Smuzhiyun #define BT_UART_MSG_FRAME3SNIFF_POS (1) 3512*4882a593Smuzhiyun #define BT_UART_MSG_FRAME3SNIFF_MSK \ 3513*4882a593Smuzhiyun (0x1 << BT_UART_MSG_FRAME3SNIFF_POS) 3514*4882a593Smuzhiyun #define BT_UART_MSG_FRAME3A2DP_POS (2) 3515*4882a593Smuzhiyun #define BT_UART_MSG_FRAME3A2DP_MSK \ 3516*4882a593Smuzhiyun (0x1 << BT_UART_MSG_FRAME3A2DP_POS) 3517*4882a593Smuzhiyun #define BT_UART_MSG_FRAME3ACL_POS (3) 3518*4882a593Smuzhiyun #define BT_UART_MSG_FRAME3ACL_MSK \ 3519*4882a593Smuzhiyun (0x1 << BT_UART_MSG_FRAME3ACL_POS) 3520*4882a593Smuzhiyun #define BT_UART_MSG_FRAME3MASTER_POS (4) 3521*4882a593Smuzhiyun #define BT_UART_MSG_FRAME3MASTER_MSK \ 3522*4882a593Smuzhiyun (0x1 << BT_UART_MSG_FRAME3MASTER_POS) 3523*4882a593Smuzhiyun #define BT_UART_MSG_FRAME3OBEX_POS (5) 3524*4882a593Smuzhiyun #define BT_UART_MSG_FRAME3OBEX_MSK \ 3525*4882a593Smuzhiyun (0x1 << BT_UART_MSG_FRAME3OBEX_POS) 3526*4882a593Smuzhiyun #define BT_UART_MSG_FRAME3RESERVED_POS (6) 3527*4882a593Smuzhiyun #define BT_UART_MSG_FRAME3RESERVED_MSK \ 3528*4882a593Smuzhiyun (0x3 << BT_UART_MSG_FRAME3RESERVED_POS) 3529*4882a593Smuzhiyun 3530*4882a593Smuzhiyun #define BT_UART_MSG_FRAME4IDLEDURATION_POS (0) 3531*4882a593Smuzhiyun #define BT_UART_MSG_FRAME4IDLEDURATION_MSK \ 3532*4882a593Smuzhiyun (0x3F << BT_UART_MSG_FRAME4IDLEDURATION_POS) 3533*4882a593Smuzhiyun #define BT_UART_MSG_FRAME4RESERVED_POS (6) 3534*4882a593Smuzhiyun #define BT_UART_MSG_FRAME4RESERVED_MSK \ 3535*4882a593Smuzhiyun (0x3 << BT_UART_MSG_FRAME4RESERVED_POS) 3536*4882a593Smuzhiyun 3537*4882a593Smuzhiyun #define BT_UART_MSG_FRAME5TXACTIVITY_POS (0) 3538*4882a593Smuzhiyun #define BT_UART_MSG_FRAME5TXACTIVITY_MSK \ 3539*4882a593Smuzhiyun (0x3 << BT_UART_MSG_FRAME5TXACTIVITY_POS) 3540*4882a593Smuzhiyun #define BT_UART_MSG_FRAME5RXACTIVITY_POS (2) 3541*4882a593Smuzhiyun #define BT_UART_MSG_FRAME5RXACTIVITY_MSK \ 3542*4882a593Smuzhiyun (0x3 << BT_UART_MSG_FRAME5RXACTIVITY_POS) 3543*4882a593Smuzhiyun #define BT_UART_MSG_FRAME5ESCORETRANSMIT_POS (4) 3544*4882a593Smuzhiyun #define BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK \ 3545*4882a593Smuzhiyun (0x3 << BT_UART_MSG_FRAME5ESCORETRANSMIT_POS) 3546*4882a593Smuzhiyun #define BT_UART_MSG_FRAME5RESERVED_POS (6) 3547*4882a593Smuzhiyun #define BT_UART_MSG_FRAME5RESERVED_MSK \ 3548*4882a593Smuzhiyun (0x3 << BT_UART_MSG_FRAME5RESERVED_POS) 3549*4882a593Smuzhiyun 3550*4882a593Smuzhiyun #define BT_UART_MSG_FRAME6SNIFFINTERVAL_POS (0) 3551*4882a593Smuzhiyun #define BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK \ 3552*4882a593Smuzhiyun (0x1F << BT_UART_MSG_FRAME6SNIFFINTERVAL_POS) 3553*4882a593Smuzhiyun #define BT_UART_MSG_FRAME6DISCOVERABLE_POS (5) 3554*4882a593Smuzhiyun #define BT_UART_MSG_FRAME6DISCOVERABLE_MSK \ 3555*4882a593Smuzhiyun (0x1 << BT_UART_MSG_FRAME6DISCOVERABLE_POS) 3556*4882a593Smuzhiyun #define BT_UART_MSG_FRAME6RESERVED_POS (6) 3557*4882a593Smuzhiyun #define BT_UART_MSG_FRAME6RESERVED_MSK \ 3558*4882a593Smuzhiyun (0x3 << BT_UART_MSG_FRAME6RESERVED_POS) 3559*4882a593Smuzhiyun 3560*4882a593Smuzhiyun #define BT_UART_MSG_FRAME7SNIFFACTIVITY_POS (0) 3561*4882a593Smuzhiyun #define BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK \ 3562*4882a593Smuzhiyun (0x7 << BT_UART_MSG_FRAME7SNIFFACTIVITY_POS) 3563*4882a593Smuzhiyun #define BT_UART_MSG_FRAME7PAGE_POS (3) 3564*4882a593Smuzhiyun #define BT_UART_MSG_FRAME7PAGE_MSK \ 3565*4882a593Smuzhiyun (0x1 << BT_UART_MSG_FRAME7PAGE_POS) 3566*4882a593Smuzhiyun #define BT_UART_MSG_FRAME7INQUIRY_POS (4) 3567*4882a593Smuzhiyun #define BT_UART_MSG_FRAME7INQUIRY_MSK \ 3568*4882a593Smuzhiyun (0x1 << BT_UART_MSG_FRAME7INQUIRY_POS) 3569*4882a593Smuzhiyun #define BT_UART_MSG_FRAME7CONNECTABLE_POS (5) 3570*4882a593Smuzhiyun #define BT_UART_MSG_FRAME7CONNECTABLE_MSK \ 3571*4882a593Smuzhiyun (0x1 << BT_UART_MSG_FRAME7CONNECTABLE_POS) 3572*4882a593Smuzhiyun #define BT_UART_MSG_FRAME7RESERVED_POS (6) 3573*4882a593Smuzhiyun #define BT_UART_MSG_FRAME7RESERVED_MSK \ 3574*4882a593Smuzhiyun (0x3 << BT_UART_MSG_FRAME7RESERVED_POS) 3575*4882a593Smuzhiyun 3576*4882a593Smuzhiyun /* BT Session Activity 2 UART message (BT -> WiFi) */ 3577*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME1RESERVED1_POS (5) 3578*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME1RESERVED1_MSK \ 3579*4882a593Smuzhiyun (0x1<<BT_UART_MSG_2_FRAME1RESERVED1_POS) 3580*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME1RESERVED2_POS (6) 3581*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME1RESERVED2_MSK \ 3582*4882a593Smuzhiyun (0x3<<BT_UART_MSG_2_FRAME1RESERVED2_POS) 3583*4882a593Smuzhiyun 3584*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS (0) 3585*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_MSK \ 3586*4882a593Smuzhiyun (0x3F<<BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS) 3587*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME2RESERVED_POS (6) 3588*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME2RESERVED_MSK \ 3589*4882a593Smuzhiyun (0x3<<BT_UART_MSG_2_FRAME2RESERVED_POS) 3590*4882a593Smuzhiyun 3591*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS (0) 3592*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_MSK \ 3593*4882a593Smuzhiyun (0xF<<BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS) 3594*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS (4) 3595*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME3INQPAGESRMODE_MSK \ 3596*4882a593Smuzhiyun (0x1<<BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS) 3597*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME3LEMASTER_POS (5) 3598*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME3LEMASTER_MSK \ 3599*4882a593Smuzhiyun (0x1<<BT_UART_MSG_2_FRAME3LEMASTER_POS) 3600*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME3RESERVED_POS (6) 3601*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME3RESERVED_MSK \ 3602*4882a593Smuzhiyun (0x3<<BT_UART_MSG_2_FRAME3RESERVED_POS) 3603*4882a593Smuzhiyun 3604*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS (0) 3605*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME4LELASTTXPOWER_MSK \ 3606*4882a593Smuzhiyun (0xF<<BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS) 3607*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME4NUMLECONN_POS (4) 3608*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME4NUMLECONN_MSK \ 3609*4882a593Smuzhiyun (0x3<<BT_UART_MSG_2_FRAME4NUMLECONN_POS) 3610*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME4RESERVED_POS (6) 3611*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME4RESERVED_MSK \ 3612*4882a593Smuzhiyun (0x3<<BT_UART_MSG_2_FRAME4RESERVED_POS) 3613*4882a593Smuzhiyun 3614*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME5BTMINRSSI_POS (0) 3615*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME5BTMINRSSI_MSK \ 3616*4882a593Smuzhiyun (0xF<<BT_UART_MSG_2_FRAME5BTMINRSSI_POS) 3617*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME5LESCANINITMODE_POS (4) 3618*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME5LESCANINITMODE_MSK \ 3619*4882a593Smuzhiyun (0x1<<BT_UART_MSG_2_FRAME5LESCANINITMODE_POS) 3620*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME5LEADVERMODE_POS (5) 3621*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME5LEADVERMODE_MSK \ 3622*4882a593Smuzhiyun (0x1<<BT_UART_MSG_2_FRAME5LEADVERMODE_POS) 3623*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME5RESERVED_POS (6) 3624*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME5RESERVED_MSK \ 3625*4882a593Smuzhiyun (0x3<<BT_UART_MSG_2_FRAME5RESERVED_POS) 3626*4882a593Smuzhiyun 3627*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS (0) 3628*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME6LECONNINTERVAL_MSK \ 3629*4882a593Smuzhiyun (0x1F<<BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS) 3630*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME6RFU_POS (5) 3631*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME6RFU_MSK \ 3632*4882a593Smuzhiyun (0x1<<BT_UART_MSG_2_FRAME6RFU_POS) 3633*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME6RESERVED_POS (6) 3634*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME6RESERVED_MSK \ 3635*4882a593Smuzhiyun (0x3<<BT_UART_MSG_2_FRAME6RESERVED_POS) 3636*4882a593Smuzhiyun 3637*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS (0) 3638*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_MSK \ 3639*4882a593Smuzhiyun (0x7<<BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS) 3640*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME7LEPROFILE1_POS (3) 3641*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME7LEPROFILE1_MSK \ 3642*4882a593Smuzhiyun (0x1<<BT_UART_MSG_2_FRAME7LEPROFILE1_POS) 3643*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME7LEPROFILE2_POS (4) 3644*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME7LEPROFILE2_MSK \ 3645*4882a593Smuzhiyun (0x1<<BT_UART_MSG_2_FRAME7LEPROFILE2_POS) 3646*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS (5) 3647*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_MSK \ 3648*4882a593Smuzhiyun (0x1<<BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS) 3649*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME7RESERVED_POS (6) 3650*4882a593Smuzhiyun #define BT_UART_MSG_2_FRAME7RESERVED_MSK \ 3651*4882a593Smuzhiyun (0x3<<BT_UART_MSG_2_FRAME7RESERVED_POS) 3652*4882a593Smuzhiyun 3653*4882a593Smuzhiyun 3654*4882a593Smuzhiyun #define BT_ENABLE_REDUCED_TXPOWER_THRESHOLD (-62) 3655*4882a593Smuzhiyun #define BT_DISABLE_REDUCED_TXPOWER_THRESHOLD (-65) 3656*4882a593Smuzhiyun 3657*4882a593Smuzhiyun struct iwl_bt_uart_msg { 3658*4882a593Smuzhiyun u8 header; 3659*4882a593Smuzhiyun u8 frame1; 3660*4882a593Smuzhiyun u8 frame2; 3661*4882a593Smuzhiyun u8 frame3; 3662*4882a593Smuzhiyun u8 frame4; 3663*4882a593Smuzhiyun u8 frame5; 3664*4882a593Smuzhiyun u8 frame6; 3665*4882a593Smuzhiyun u8 frame7; 3666*4882a593Smuzhiyun } __packed; 3667*4882a593Smuzhiyun 3668*4882a593Smuzhiyun struct iwl_bt_coex_profile_notif { 3669*4882a593Smuzhiyun struct iwl_bt_uart_msg last_bt_uart_msg; 3670*4882a593Smuzhiyun u8 bt_status; /* 0 - off, 1 - on */ 3671*4882a593Smuzhiyun u8 bt_traffic_load; /* 0 .. 3? */ 3672*4882a593Smuzhiyun u8 bt_ci_compliance; /* 0 - not complied, 1 - complied */ 3673*4882a593Smuzhiyun u8 reserved; 3674*4882a593Smuzhiyun } __packed; 3675*4882a593Smuzhiyun 3676*4882a593Smuzhiyun #define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS 0 3677*4882a593Smuzhiyun #define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_MSK 0x1 3678*4882a593Smuzhiyun #define IWL_BT_COEX_PRIO_TBL_PRIO_POS 1 3679*4882a593Smuzhiyun #define IWL_BT_COEX_PRIO_TBL_PRIO_MASK 0x0e 3680*4882a593Smuzhiyun #define IWL_BT_COEX_PRIO_TBL_RESERVED_POS 4 3681*4882a593Smuzhiyun #define IWL_BT_COEX_PRIO_TBL_RESERVED_MASK 0xf0 3682*4882a593Smuzhiyun #define IWL_BT_COEX_PRIO_TBL_PRIO_SHIFT 1 3683*4882a593Smuzhiyun 3684*4882a593Smuzhiyun /* 3685*4882a593Smuzhiyun * BT Coexistence Priority table 3686*4882a593Smuzhiyun * REPLY_BT_COEX_PRIO_TABLE = 0xcc 3687*4882a593Smuzhiyun */ 3688*4882a593Smuzhiyun enum bt_coex_prio_table_events { 3689*4882a593Smuzhiyun BT_COEX_PRIO_TBL_EVT_INIT_CALIB1 = 0, 3690*4882a593Smuzhiyun BT_COEX_PRIO_TBL_EVT_INIT_CALIB2 = 1, 3691*4882a593Smuzhiyun BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW1 = 2, 3692*4882a593Smuzhiyun BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW2 = 3, /* DC calib */ 3693*4882a593Smuzhiyun BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH1 = 4, 3694*4882a593Smuzhiyun BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH2 = 5, 3695*4882a593Smuzhiyun BT_COEX_PRIO_TBL_EVT_DTIM = 6, 3696*4882a593Smuzhiyun BT_COEX_PRIO_TBL_EVT_SCAN52 = 7, 3697*4882a593Smuzhiyun BT_COEX_PRIO_TBL_EVT_SCAN24 = 8, 3698*4882a593Smuzhiyun BT_COEX_PRIO_TBL_EVT_RESERVED0 = 9, 3699*4882a593Smuzhiyun BT_COEX_PRIO_TBL_EVT_RESERVED1 = 10, 3700*4882a593Smuzhiyun BT_COEX_PRIO_TBL_EVT_RESERVED2 = 11, 3701*4882a593Smuzhiyun BT_COEX_PRIO_TBL_EVT_RESERVED3 = 12, 3702*4882a593Smuzhiyun BT_COEX_PRIO_TBL_EVT_RESERVED4 = 13, 3703*4882a593Smuzhiyun BT_COEX_PRIO_TBL_EVT_RESERVED5 = 14, 3704*4882a593Smuzhiyun BT_COEX_PRIO_TBL_EVT_RESERVED6 = 15, 3705*4882a593Smuzhiyun /* BT_COEX_PRIO_TBL_EVT_MAX should always be last */ 3706*4882a593Smuzhiyun BT_COEX_PRIO_TBL_EVT_MAX, 3707*4882a593Smuzhiyun }; 3708*4882a593Smuzhiyun 3709*4882a593Smuzhiyun enum bt_coex_prio_table_priorities { 3710*4882a593Smuzhiyun BT_COEX_PRIO_TBL_DISABLED = 0, 3711*4882a593Smuzhiyun BT_COEX_PRIO_TBL_PRIO_LOW = 1, 3712*4882a593Smuzhiyun BT_COEX_PRIO_TBL_PRIO_HIGH = 2, 3713*4882a593Smuzhiyun BT_COEX_PRIO_TBL_PRIO_BYPASS = 3, 3714*4882a593Smuzhiyun BT_COEX_PRIO_TBL_PRIO_COEX_OFF = 4, 3715*4882a593Smuzhiyun BT_COEX_PRIO_TBL_PRIO_COEX_ON = 5, 3716*4882a593Smuzhiyun BT_COEX_PRIO_TBL_PRIO_RSRVD1 = 6, 3717*4882a593Smuzhiyun BT_COEX_PRIO_TBL_PRIO_RSRVD2 = 7, 3718*4882a593Smuzhiyun BT_COEX_PRIO_TBL_MAX, 3719*4882a593Smuzhiyun }; 3720*4882a593Smuzhiyun 3721*4882a593Smuzhiyun struct iwl_bt_coex_prio_table_cmd { 3722*4882a593Smuzhiyun u8 prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX]; 3723*4882a593Smuzhiyun } __packed; 3724*4882a593Smuzhiyun 3725*4882a593Smuzhiyun #define IWL_BT_COEX_ENV_CLOSE 0 3726*4882a593Smuzhiyun #define IWL_BT_COEX_ENV_OPEN 1 3727*4882a593Smuzhiyun /* 3728*4882a593Smuzhiyun * BT Protection Envelope 3729*4882a593Smuzhiyun * REPLY_BT_COEX_PROT_ENV = 0xcd 3730*4882a593Smuzhiyun */ 3731*4882a593Smuzhiyun struct iwl_bt_coex_prot_env_cmd { 3732*4882a593Smuzhiyun u8 action; /* 0 = closed, 1 = open */ 3733*4882a593Smuzhiyun u8 type; /* 0 .. 15 */ 3734*4882a593Smuzhiyun u8 reserved[2]; 3735*4882a593Smuzhiyun } __packed; 3736*4882a593Smuzhiyun 3737*4882a593Smuzhiyun /* 3738*4882a593Smuzhiyun * REPLY_D3_CONFIG 3739*4882a593Smuzhiyun */ 3740*4882a593Smuzhiyun enum iwlagn_d3_wakeup_filters { 3741*4882a593Smuzhiyun IWLAGN_D3_WAKEUP_RFKILL = BIT(0), 3742*4882a593Smuzhiyun IWLAGN_D3_WAKEUP_SYSASSERT = BIT(1), 3743*4882a593Smuzhiyun }; 3744*4882a593Smuzhiyun 3745*4882a593Smuzhiyun struct iwlagn_d3_config_cmd { 3746*4882a593Smuzhiyun __le32 min_sleep_time; 3747*4882a593Smuzhiyun __le32 wakeup_flags; 3748*4882a593Smuzhiyun } __packed; 3749*4882a593Smuzhiyun 3750*4882a593Smuzhiyun /* 3751*4882a593Smuzhiyun * REPLY_WOWLAN_PATTERNS 3752*4882a593Smuzhiyun */ 3753*4882a593Smuzhiyun #define IWLAGN_WOWLAN_MIN_PATTERN_LEN 16 3754*4882a593Smuzhiyun #define IWLAGN_WOWLAN_MAX_PATTERN_LEN 128 3755*4882a593Smuzhiyun 3756*4882a593Smuzhiyun struct iwlagn_wowlan_pattern { 3757*4882a593Smuzhiyun u8 mask[IWLAGN_WOWLAN_MAX_PATTERN_LEN / 8]; 3758*4882a593Smuzhiyun u8 pattern[IWLAGN_WOWLAN_MAX_PATTERN_LEN]; 3759*4882a593Smuzhiyun u8 mask_size; 3760*4882a593Smuzhiyun u8 pattern_size; 3761*4882a593Smuzhiyun __le16 reserved; 3762*4882a593Smuzhiyun } __packed; 3763*4882a593Smuzhiyun 3764*4882a593Smuzhiyun #define IWLAGN_WOWLAN_MAX_PATTERNS 20 3765*4882a593Smuzhiyun 3766*4882a593Smuzhiyun struct iwlagn_wowlan_patterns_cmd { 3767*4882a593Smuzhiyun __le32 n_patterns; 3768*4882a593Smuzhiyun struct iwlagn_wowlan_pattern patterns[]; 3769*4882a593Smuzhiyun } __packed; 3770*4882a593Smuzhiyun 3771*4882a593Smuzhiyun /* 3772*4882a593Smuzhiyun * REPLY_WOWLAN_WAKEUP_FILTER 3773*4882a593Smuzhiyun */ 3774*4882a593Smuzhiyun enum iwlagn_wowlan_wakeup_filters { 3775*4882a593Smuzhiyun IWLAGN_WOWLAN_WAKEUP_MAGIC_PACKET = BIT(0), 3776*4882a593Smuzhiyun IWLAGN_WOWLAN_WAKEUP_PATTERN_MATCH = BIT(1), 3777*4882a593Smuzhiyun IWLAGN_WOWLAN_WAKEUP_BEACON_MISS = BIT(2), 3778*4882a593Smuzhiyun IWLAGN_WOWLAN_WAKEUP_LINK_CHANGE = BIT(3), 3779*4882a593Smuzhiyun IWLAGN_WOWLAN_WAKEUP_GTK_REKEY_FAIL = BIT(4), 3780*4882a593Smuzhiyun IWLAGN_WOWLAN_WAKEUP_EAP_IDENT_REQ = BIT(5), 3781*4882a593Smuzhiyun IWLAGN_WOWLAN_WAKEUP_4WAY_HANDSHAKE = BIT(6), 3782*4882a593Smuzhiyun IWLAGN_WOWLAN_WAKEUP_ALWAYS = BIT(7), 3783*4882a593Smuzhiyun IWLAGN_WOWLAN_WAKEUP_ENABLE_NET_DETECT = BIT(8), 3784*4882a593Smuzhiyun }; 3785*4882a593Smuzhiyun 3786*4882a593Smuzhiyun struct iwlagn_wowlan_wakeup_filter_cmd { 3787*4882a593Smuzhiyun __le32 enabled; 3788*4882a593Smuzhiyun __le16 non_qos_seq; 3789*4882a593Smuzhiyun __le16 reserved; 3790*4882a593Smuzhiyun __le16 qos_seq[8]; 3791*4882a593Smuzhiyun }; 3792*4882a593Smuzhiyun 3793*4882a593Smuzhiyun /* 3794*4882a593Smuzhiyun * REPLY_WOWLAN_TSC_RSC_PARAMS 3795*4882a593Smuzhiyun */ 3796*4882a593Smuzhiyun #define IWLAGN_NUM_RSC 16 3797*4882a593Smuzhiyun 3798*4882a593Smuzhiyun struct tkip_sc { 3799*4882a593Smuzhiyun __le16 iv16; 3800*4882a593Smuzhiyun __le16 pad; 3801*4882a593Smuzhiyun __le32 iv32; 3802*4882a593Smuzhiyun } __packed; 3803*4882a593Smuzhiyun 3804*4882a593Smuzhiyun struct iwlagn_tkip_rsc_tsc { 3805*4882a593Smuzhiyun struct tkip_sc unicast_rsc[IWLAGN_NUM_RSC]; 3806*4882a593Smuzhiyun struct tkip_sc multicast_rsc[IWLAGN_NUM_RSC]; 3807*4882a593Smuzhiyun struct tkip_sc tsc; 3808*4882a593Smuzhiyun } __packed; 3809*4882a593Smuzhiyun 3810*4882a593Smuzhiyun struct aes_sc { 3811*4882a593Smuzhiyun __le64 pn; 3812*4882a593Smuzhiyun } __packed; 3813*4882a593Smuzhiyun 3814*4882a593Smuzhiyun struct iwlagn_aes_rsc_tsc { 3815*4882a593Smuzhiyun struct aes_sc unicast_rsc[IWLAGN_NUM_RSC]; 3816*4882a593Smuzhiyun struct aes_sc multicast_rsc[IWLAGN_NUM_RSC]; 3817*4882a593Smuzhiyun struct aes_sc tsc; 3818*4882a593Smuzhiyun } __packed; 3819*4882a593Smuzhiyun 3820*4882a593Smuzhiyun union iwlagn_all_tsc_rsc { 3821*4882a593Smuzhiyun struct iwlagn_tkip_rsc_tsc tkip; 3822*4882a593Smuzhiyun struct iwlagn_aes_rsc_tsc aes; 3823*4882a593Smuzhiyun }; 3824*4882a593Smuzhiyun 3825*4882a593Smuzhiyun struct iwlagn_wowlan_rsc_tsc_params_cmd { 3826*4882a593Smuzhiyun union iwlagn_all_tsc_rsc all_tsc_rsc; 3827*4882a593Smuzhiyun } __packed; 3828*4882a593Smuzhiyun 3829*4882a593Smuzhiyun /* 3830*4882a593Smuzhiyun * REPLY_WOWLAN_TKIP_PARAMS 3831*4882a593Smuzhiyun */ 3832*4882a593Smuzhiyun #define IWLAGN_MIC_KEY_SIZE 8 3833*4882a593Smuzhiyun #define IWLAGN_P1K_SIZE 5 3834*4882a593Smuzhiyun struct iwlagn_mic_keys { 3835*4882a593Smuzhiyun u8 tx[IWLAGN_MIC_KEY_SIZE]; 3836*4882a593Smuzhiyun u8 rx_unicast[IWLAGN_MIC_KEY_SIZE]; 3837*4882a593Smuzhiyun u8 rx_mcast[IWLAGN_MIC_KEY_SIZE]; 3838*4882a593Smuzhiyun } __packed; 3839*4882a593Smuzhiyun 3840*4882a593Smuzhiyun struct iwlagn_p1k_cache { 3841*4882a593Smuzhiyun __le16 p1k[IWLAGN_P1K_SIZE]; 3842*4882a593Smuzhiyun } __packed; 3843*4882a593Smuzhiyun 3844*4882a593Smuzhiyun #define IWLAGN_NUM_RX_P1K_CACHE 2 3845*4882a593Smuzhiyun 3846*4882a593Smuzhiyun struct iwlagn_wowlan_tkip_params_cmd { 3847*4882a593Smuzhiyun struct iwlagn_mic_keys mic_keys; 3848*4882a593Smuzhiyun struct iwlagn_p1k_cache tx; 3849*4882a593Smuzhiyun struct iwlagn_p1k_cache rx_uni[IWLAGN_NUM_RX_P1K_CACHE]; 3850*4882a593Smuzhiyun struct iwlagn_p1k_cache rx_multi[IWLAGN_NUM_RX_P1K_CACHE]; 3851*4882a593Smuzhiyun } __packed; 3852*4882a593Smuzhiyun 3853*4882a593Smuzhiyun /* 3854*4882a593Smuzhiyun * REPLY_WOWLAN_KEK_KCK_MATERIAL 3855*4882a593Smuzhiyun */ 3856*4882a593Smuzhiyun 3857*4882a593Smuzhiyun #define IWLAGN_KCK_MAX_SIZE 32 3858*4882a593Smuzhiyun #define IWLAGN_KEK_MAX_SIZE 32 3859*4882a593Smuzhiyun 3860*4882a593Smuzhiyun struct iwlagn_wowlan_kek_kck_material_cmd { 3861*4882a593Smuzhiyun u8 kck[IWLAGN_KCK_MAX_SIZE]; 3862*4882a593Smuzhiyun u8 kek[IWLAGN_KEK_MAX_SIZE]; 3863*4882a593Smuzhiyun __le16 kck_len; 3864*4882a593Smuzhiyun __le16 kek_len; 3865*4882a593Smuzhiyun __le64 replay_ctr; 3866*4882a593Smuzhiyun } __packed; 3867*4882a593Smuzhiyun 3868*4882a593Smuzhiyun #define RF_KILL_INDICATOR_FOR_WOWLAN 0x87 3869*4882a593Smuzhiyun 3870*4882a593Smuzhiyun /* 3871*4882a593Smuzhiyun * REPLY_WOWLAN_GET_STATUS = 0xe5 3872*4882a593Smuzhiyun */ 3873*4882a593Smuzhiyun struct iwlagn_wowlan_status { 3874*4882a593Smuzhiyun __le64 replay_ctr; 3875*4882a593Smuzhiyun __le32 rekey_status; 3876*4882a593Smuzhiyun __le32 wakeup_reason; 3877*4882a593Smuzhiyun u8 pattern_number; 3878*4882a593Smuzhiyun u8 reserved1; 3879*4882a593Smuzhiyun __le16 qos_seq_ctr[8]; 3880*4882a593Smuzhiyun __le16 non_qos_seq_ctr; 3881*4882a593Smuzhiyun __le16 reserved2; 3882*4882a593Smuzhiyun union iwlagn_all_tsc_rsc tsc_rsc; 3883*4882a593Smuzhiyun __le16 reserved3; 3884*4882a593Smuzhiyun } __packed; 3885*4882a593Smuzhiyun 3886*4882a593Smuzhiyun /* 3887*4882a593Smuzhiyun * REPLY_WIPAN_PARAMS = 0xb2 (Commands and Notification) 3888*4882a593Smuzhiyun */ 3889*4882a593Smuzhiyun 3890*4882a593Smuzhiyun /* 3891*4882a593Smuzhiyun * Minimum slot time in TU 3892*4882a593Smuzhiyun */ 3893*4882a593Smuzhiyun #define IWL_MIN_SLOT_TIME 20 3894*4882a593Smuzhiyun 3895*4882a593Smuzhiyun /** 3896*4882a593Smuzhiyun * struct iwl_wipan_slot 3897*4882a593Smuzhiyun * @width: Time in TU 3898*4882a593Smuzhiyun * @type: 3899*4882a593Smuzhiyun * 0 - BSS 3900*4882a593Smuzhiyun * 1 - PAN 3901*4882a593Smuzhiyun */ 3902*4882a593Smuzhiyun struct iwl_wipan_slot { 3903*4882a593Smuzhiyun __le16 width; 3904*4882a593Smuzhiyun u8 type; 3905*4882a593Smuzhiyun u8 reserved; 3906*4882a593Smuzhiyun } __packed; 3907*4882a593Smuzhiyun 3908*4882a593Smuzhiyun #define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_CTS BIT(1) /* reserved */ 3909*4882a593Smuzhiyun #define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_QUIET BIT(2) /* reserved */ 3910*4882a593Smuzhiyun #define IWL_WIPAN_PARAMS_FLG_SLOTTED_MODE BIT(3) /* reserved */ 3911*4882a593Smuzhiyun #define IWL_WIPAN_PARAMS_FLG_FILTER_BEACON_NOTIF BIT(4) 3912*4882a593Smuzhiyun #define IWL_WIPAN_PARAMS_FLG_FULL_SLOTTED_MODE BIT(5) 3913*4882a593Smuzhiyun 3914*4882a593Smuzhiyun /** 3915*4882a593Smuzhiyun * struct iwl_wipan_params_cmd 3916*4882a593Smuzhiyun * @flags: 3917*4882a593Smuzhiyun * bit0: reserved 3918*4882a593Smuzhiyun * bit1: CP leave channel with CTS 3919*4882a593Smuzhiyun * bit2: CP leave channel qith Quiet 3920*4882a593Smuzhiyun * bit3: slotted mode 3921*4882a593Smuzhiyun * 1 - work in slotted mode 3922*4882a593Smuzhiyun * 0 - work in non slotted mode 3923*4882a593Smuzhiyun * bit4: filter beacon notification 3924*4882a593Smuzhiyun * bit5: full tx slotted mode. if this flag is set, 3925*4882a593Smuzhiyun * uCode will perform leaving channel methods in context switch 3926*4882a593Smuzhiyun * also when working in same channel mode 3927*4882a593Smuzhiyun * @num_slots: 1 - 10 3928*4882a593Smuzhiyun */ 3929*4882a593Smuzhiyun struct iwl_wipan_params_cmd { 3930*4882a593Smuzhiyun __le16 flags; 3931*4882a593Smuzhiyun u8 reserved; 3932*4882a593Smuzhiyun u8 num_slots; 3933*4882a593Smuzhiyun struct iwl_wipan_slot slots[10]; 3934*4882a593Smuzhiyun } __packed; 3935*4882a593Smuzhiyun 3936*4882a593Smuzhiyun /* 3937*4882a593Smuzhiyun * REPLY_WIPAN_P2P_CHANNEL_SWITCH = 0xb9 3938*4882a593Smuzhiyun * 3939*4882a593Smuzhiyun * TODO: Figure out what this is used for, 3940*4882a593Smuzhiyun * it can only switch between 2.4 GHz 3941*4882a593Smuzhiyun * channels!! 3942*4882a593Smuzhiyun */ 3943*4882a593Smuzhiyun 3944*4882a593Smuzhiyun struct iwl_wipan_p2p_channel_switch_cmd { 3945*4882a593Smuzhiyun __le16 channel; 3946*4882a593Smuzhiyun __le16 reserved; 3947*4882a593Smuzhiyun }; 3948*4882a593Smuzhiyun 3949*4882a593Smuzhiyun /* 3950*4882a593Smuzhiyun * REPLY_WIPAN_NOA_NOTIFICATION = 0xbc 3951*4882a593Smuzhiyun * 3952*4882a593Smuzhiyun * This is used by the device to notify us of the 3953*4882a593Smuzhiyun * NoA schedule it determined so we can forward it 3954*4882a593Smuzhiyun * to userspace for inclusion in probe responses. 3955*4882a593Smuzhiyun * 3956*4882a593Smuzhiyun * In beacons, the NoA schedule is simply appended 3957*4882a593Smuzhiyun * to the frame we give the device. 3958*4882a593Smuzhiyun */ 3959*4882a593Smuzhiyun 3960*4882a593Smuzhiyun struct iwl_wipan_noa_descriptor { 3961*4882a593Smuzhiyun u8 count; 3962*4882a593Smuzhiyun __le32 duration; 3963*4882a593Smuzhiyun __le32 interval; 3964*4882a593Smuzhiyun __le32 starttime; 3965*4882a593Smuzhiyun } __packed; 3966*4882a593Smuzhiyun 3967*4882a593Smuzhiyun struct iwl_wipan_noa_attribute { 3968*4882a593Smuzhiyun u8 id; 3969*4882a593Smuzhiyun __le16 length; 3970*4882a593Smuzhiyun u8 index; 3971*4882a593Smuzhiyun u8 ct_window; 3972*4882a593Smuzhiyun struct iwl_wipan_noa_descriptor descr0, descr1; 3973*4882a593Smuzhiyun u8 reserved; 3974*4882a593Smuzhiyun } __packed; 3975*4882a593Smuzhiyun 3976*4882a593Smuzhiyun struct iwl_wipan_noa_notification { 3977*4882a593Smuzhiyun u32 noa_active; 3978*4882a593Smuzhiyun struct iwl_wipan_noa_attribute noa_attribute; 3979*4882a593Smuzhiyun } __packed; 3980*4882a593Smuzhiyun 3981*4882a593Smuzhiyun #endif /* __iwl_commands_h__ */ 3982