xref: /OK3568_Linux_fs/kernel/arch/arm/mach-orion5x/ts409-setup.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * QNAP TS-409 Board Setup
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright (C) 2008  Sylver Bruneau <sylver.bruneau@gmail.com>
8*4882a593Smuzhiyun  * Copyright (C) 2008  Martin Michlmayr <tbm@cyrius.com>
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun #include <linux/gpio.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/pci.h>
15*4882a593Smuzhiyun #include <linux/irq.h>
16*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
17*4882a593Smuzhiyun #include <linux/mv643xx_eth.h>
18*4882a593Smuzhiyun #include <linux/leds.h>
19*4882a593Smuzhiyun #include <linux/gpio_keys.h>
20*4882a593Smuzhiyun #include <linux/input.h>
21*4882a593Smuzhiyun #include <linux/i2c.h>
22*4882a593Smuzhiyun #include <linux/serial_reg.h>
23*4882a593Smuzhiyun #include <asm/mach-types.h>
24*4882a593Smuzhiyun #include <asm/mach/arch.h>
25*4882a593Smuzhiyun #include <asm/mach/pci.h>
26*4882a593Smuzhiyun #include "common.h"
27*4882a593Smuzhiyun #include "mpp.h"
28*4882a593Smuzhiyun #include "orion5x.h"
29*4882a593Smuzhiyun #include "tsx09-common.h"
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun /*****************************************************************************
32*4882a593Smuzhiyun  * QNAP TS-409 Info
33*4882a593Smuzhiyun  ****************************************************************************/
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun  * QNAP TS-409 hardware :
37*4882a593Smuzhiyun  * - Marvell 88F5281-D0
38*4882a593Smuzhiyun  * - Marvell 88SX7042 SATA controller (PCIe)
39*4882a593Smuzhiyun  * - Marvell 88E1118 Gigabit Ethernet PHY
40*4882a593Smuzhiyun  * - RTC S35390A (@0x30) on I2C bus
41*4882a593Smuzhiyun  * - 8MB NOR flash
42*4882a593Smuzhiyun  * - 256MB of DDR-2 RAM
43*4882a593Smuzhiyun  */
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /*
46*4882a593Smuzhiyun  * 8MB NOR flash Device bus boot chip select
47*4882a593Smuzhiyun  */
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #define QNAP_TS409_NOR_BOOT_BASE 0xff800000
50*4882a593Smuzhiyun #define QNAP_TS409_NOR_BOOT_SIZE SZ_8M
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun /****************************************************************************
53*4882a593Smuzhiyun  * 8MiB NOR flash. The struct mtd_partition is not in the same order as the
54*4882a593Smuzhiyun  *     partitions on the device because we want to keep compatibility with
55*4882a593Smuzhiyun  *     existing QNAP firmware.
56*4882a593Smuzhiyun  *
57*4882a593Smuzhiyun  * Layout as used by QNAP:
58*4882a593Smuzhiyun  *  [2] 0x00000000-0x00200000 : "Kernel"
59*4882a593Smuzhiyun  *  [3] 0x00200000-0x00600000 : "RootFS1"
60*4882a593Smuzhiyun  *  [4] 0x00600000-0x00700000 : "RootFS2"
61*4882a593Smuzhiyun  *  [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
62*4882a593Smuzhiyun  *  [5] 0x00760000-0x00780000 : "U-Boot Config"
63*4882a593Smuzhiyun  *  [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
64*4882a593Smuzhiyun  ***************************************************************************/
65*4882a593Smuzhiyun static struct mtd_partition qnap_ts409_partitions[] = {
66*4882a593Smuzhiyun 	{
67*4882a593Smuzhiyun 		.name		= "U-Boot",
68*4882a593Smuzhiyun 		.size		= 0x00080000,
69*4882a593Smuzhiyun 		.offset		= 0x00780000,
70*4882a593Smuzhiyun 		.mask_flags	= MTD_WRITEABLE,
71*4882a593Smuzhiyun 	}, {
72*4882a593Smuzhiyun 		.name		= "Kernel",
73*4882a593Smuzhiyun 		.size		= 0x00200000,
74*4882a593Smuzhiyun 		.offset		= 0,
75*4882a593Smuzhiyun 	}, {
76*4882a593Smuzhiyun 		.name		= "RootFS1",
77*4882a593Smuzhiyun 		.size		= 0x00400000,
78*4882a593Smuzhiyun 		.offset		= 0x00200000,
79*4882a593Smuzhiyun 	}, {
80*4882a593Smuzhiyun 		.name		= "RootFS2",
81*4882a593Smuzhiyun 		.size		= 0x00100000,
82*4882a593Smuzhiyun 		.offset		= 0x00600000,
83*4882a593Smuzhiyun 	}, {
84*4882a593Smuzhiyun 		.name		= "U-Boot Config",
85*4882a593Smuzhiyun 		.size		= 0x00020000,
86*4882a593Smuzhiyun 		.offset		= 0x00760000,
87*4882a593Smuzhiyun 	}, {
88*4882a593Smuzhiyun 		.name		= "NAS Config",
89*4882a593Smuzhiyun 		.size		= 0x00060000,
90*4882a593Smuzhiyun 		.offset		= 0x00700000,
91*4882a593Smuzhiyun 		.mask_flags	= MTD_WRITEABLE,
92*4882a593Smuzhiyun 	},
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun static struct physmap_flash_data qnap_ts409_nor_flash_data = {
96*4882a593Smuzhiyun 	.width		= 1,
97*4882a593Smuzhiyun 	.parts		= qnap_ts409_partitions,
98*4882a593Smuzhiyun 	.nr_parts	= ARRAY_SIZE(qnap_ts409_partitions)
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun static struct resource qnap_ts409_nor_flash_resource = {
102*4882a593Smuzhiyun 	.flags	= IORESOURCE_MEM,
103*4882a593Smuzhiyun 	.start	= QNAP_TS409_NOR_BOOT_BASE,
104*4882a593Smuzhiyun 	.end	= QNAP_TS409_NOR_BOOT_BASE + QNAP_TS409_NOR_BOOT_SIZE - 1,
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun static struct platform_device qnap_ts409_nor_flash = {
108*4882a593Smuzhiyun 	.name		= "physmap-flash",
109*4882a593Smuzhiyun 	.id		= 0,
110*4882a593Smuzhiyun 	.dev		= { .platform_data = &qnap_ts409_nor_flash_data, },
111*4882a593Smuzhiyun 	.num_resources	= 1,
112*4882a593Smuzhiyun 	.resource	= &qnap_ts409_nor_flash_resource,
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun /*****************************************************************************
116*4882a593Smuzhiyun  * PCI
117*4882a593Smuzhiyun  ****************************************************************************/
118*4882a593Smuzhiyun 
qnap_ts409_pci_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)119*4882a593Smuzhiyun static int __init qnap_ts409_pci_map_irq(const struct pci_dev *dev, u8 slot,
120*4882a593Smuzhiyun 	u8 pin)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	int irq;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	/*
125*4882a593Smuzhiyun 	 * Check for devices with hard-wired IRQs.
126*4882a593Smuzhiyun 	 */
127*4882a593Smuzhiyun 	irq = orion5x_pci_map_irq(dev, slot, pin);
128*4882a593Smuzhiyun 	if (irq != -1)
129*4882a593Smuzhiyun 		return irq;
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	/*
132*4882a593Smuzhiyun 	 * PCI isn't used on the TS-409
133*4882a593Smuzhiyun 	 */
134*4882a593Smuzhiyun 	return -1;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun static struct hw_pci qnap_ts409_pci __initdata = {
138*4882a593Smuzhiyun 	.nr_controllers	= 2,
139*4882a593Smuzhiyun 	.setup		= orion5x_pci_sys_setup,
140*4882a593Smuzhiyun 	.scan		= orion5x_pci_sys_scan_bus,
141*4882a593Smuzhiyun 	.map_irq	= qnap_ts409_pci_map_irq,
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun 
qnap_ts409_pci_init(void)144*4882a593Smuzhiyun static int __init qnap_ts409_pci_init(void)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun 	if (machine_is_ts409())
147*4882a593Smuzhiyun 		pci_common_init(&qnap_ts409_pci);
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	return 0;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun subsys_initcall(qnap_ts409_pci_init);
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun /*****************************************************************************
155*4882a593Smuzhiyun  * RTC S35390A on I2C bus
156*4882a593Smuzhiyun  ****************************************************************************/
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun #define TS409_RTC_GPIO	10
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun static struct i2c_board_info __initdata qnap_ts409_i2c_rtc = {
161*4882a593Smuzhiyun 	I2C_BOARD_INFO("s35390a", 0x30),
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun /*****************************************************************************
165*4882a593Smuzhiyun  * LEDs attached to GPIO
166*4882a593Smuzhiyun  ****************************************************************************/
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun static struct gpio_led ts409_led_pins[] = {
169*4882a593Smuzhiyun 	{
170*4882a593Smuzhiyun 		.name		= "ts409:red:sata1",
171*4882a593Smuzhiyun 		.gpio		= 4,
172*4882a593Smuzhiyun 		.active_low	= 1,
173*4882a593Smuzhiyun 	}, {
174*4882a593Smuzhiyun 		.name		= "ts409:red:sata2",
175*4882a593Smuzhiyun 		.gpio		= 5,
176*4882a593Smuzhiyun 		.active_low	= 1,
177*4882a593Smuzhiyun 	}, {
178*4882a593Smuzhiyun 		.name		= "ts409:red:sata3",
179*4882a593Smuzhiyun 		.gpio		= 6,
180*4882a593Smuzhiyun 		.active_low	= 1,
181*4882a593Smuzhiyun 	}, {
182*4882a593Smuzhiyun 		.name		= "ts409:red:sata4",
183*4882a593Smuzhiyun 		.gpio		= 7,
184*4882a593Smuzhiyun 		.active_low	= 1,
185*4882a593Smuzhiyun 	},
186*4882a593Smuzhiyun };
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun static struct gpio_led_platform_data ts409_led_data = {
189*4882a593Smuzhiyun 	.leds		= ts409_led_pins,
190*4882a593Smuzhiyun 	.num_leds	= ARRAY_SIZE(ts409_led_pins),
191*4882a593Smuzhiyun };
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun static struct platform_device ts409_leds = {
194*4882a593Smuzhiyun 	.name	= "leds-gpio",
195*4882a593Smuzhiyun 	.id	= -1,
196*4882a593Smuzhiyun 	.dev	= {
197*4882a593Smuzhiyun 		.platform_data	= &ts409_led_data,
198*4882a593Smuzhiyun 	},
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun /****************************************************************************
202*4882a593Smuzhiyun  * GPIO Attached Keys
203*4882a593Smuzhiyun  *     Power button is attached to the PIC microcontroller
204*4882a593Smuzhiyun  ****************************************************************************/
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun #define QNAP_TS409_GPIO_KEY_RESET	14
207*4882a593Smuzhiyun #define QNAP_TS409_GPIO_KEY_MEDIA	15
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun static struct gpio_keys_button qnap_ts409_buttons[] = {
210*4882a593Smuzhiyun 	{
211*4882a593Smuzhiyun 		.code		= KEY_RESTART,
212*4882a593Smuzhiyun 		.gpio		= QNAP_TS409_GPIO_KEY_RESET,
213*4882a593Smuzhiyun 		.desc		= "Reset Button",
214*4882a593Smuzhiyun 		.active_low	= 1,
215*4882a593Smuzhiyun 	}, {
216*4882a593Smuzhiyun 		.code		= KEY_COPY,
217*4882a593Smuzhiyun 		.gpio		= QNAP_TS409_GPIO_KEY_MEDIA,
218*4882a593Smuzhiyun 		.desc		= "USB Copy Button",
219*4882a593Smuzhiyun 		.active_low	= 1,
220*4882a593Smuzhiyun 	},
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun static struct gpio_keys_platform_data qnap_ts409_button_data = {
224*4882a593Smuzhiyun 	.buttons	= qnap_ts409_buttons,
225*4882a593Smuzhiyun 	.nbuttons	= ARRAY_SIZE(qnap_ts409_buttons),
226*4882a593Smuzhiyun };
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun static struct platform_device qnap_ts409_button_device = {
229*4882a593Smuzhiyun 	.name		= "gpio-keys",
230*4882a593Smuzhiyun 	.id		= -1,
231*4882a593Smuzhiyun 	.num_resources	= 0,
232*4882a593Smuzhiyun 	.dev		= {
233*4882a593Smuzhiyun 		.platform_data	= &qnap_ts409_button_data,
234*4882a593Smuzhiyun 	},
235*4882a593Smuzhiyun };
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun /*****************************************************************************
238*4882a593Smuzhiyun  * General Setup
239*4882a593Smuzhiyun  ****************************************************************************/
240*4882a593Smuzhiyun static unsigned int ts409_mpp_modes[] __initdata = {
241*4882a593Smuzhiyun 	MPP0_UNUSED,
242*4882a593Smuzhiyun 	MPP1_UNUSED,
243*4882a593Smuzhiyun 	MPP2_UNUSED,
244*4882a593Smuzhiyun 	MPP3_UNUSED,
245*4882a593Smuzhiyun 	MPP4_GPIO,		/* HDD 1 status */
246*4882a593Smuzhiyun 	MPP5_GPIO,		/* HDD 2 status */
247*4882a593Smuzhiyun 	MPP6_GPIO,		/* HDD 3 status */
248*4882a593Smuzhiyun 	MPP7_GPIO,		/* HDD 4 status */
249*4882a593Smuzhiyun 	MPP8_UNUSED,
250*4882a593Smuzhiyun 	MPP9_UNUSED,
251*4882a593Smuzhiyun 	MPP10_GPIO,		/* RTC int */
252*4882a593Smuzhiyun 	MPP11_UNUSED,
253*4882a593Smuzhiyun 	MPP12_UNUSED,
254*4882a593Smuzhiyun 	MPP13_UNUSED,
255*4882a593Smuzhiyun 	MPP14_GPIO,		/* SW_RST */
256*4882a593Smuzhiyun 	MPP15_GPIO,		/* USB copy button */
257*4882a593Smuzhiyun 	MPP16_UART,		/* UART1 RXD */
258*4882a593Smuzhiyun 	MPP17_UART,		/* UART1 TXD */
259*4882a593Smuzhiyun 	MPP18_UNUSED,
260*4882a593Smuzhiyun 	MPP19_UNUSED,
261*4882a593Smuzhiyun 	0,
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun 
qnap_ts409_init(void)264*4882a593Smuzhiyun static void __init qnap_ts409_init(void)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun 	/*
267*4882a593Smuzhiyun 	 * Setup basic Orion functions. Need to be called early.
268*4882a593Smuzhiyun 	 */
269*4882a593Smuzhiyun 	orion5x_init();
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	orion5x_mpp_conf(ts409_mpp_modes);
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	/*
274*4882a593Smuzhiyun 	 * Configure peripherals.
275*4882a593Smuzhiyun 	 */
276*4882a593Smuzhiyun 	mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
277*4882a593Smuzhiyun 				    ORION_MBUS_DEVBUS_BOOT_ATTR,
278*4882a593Smuzhiyun 				    QNAP_TS409_NOR_BOOT_BASE,
279*4882a593Smuzhiyun 				    QNAP_TS409_NOR_BOOT_SIZE);
280*4882a593Smuzhiyun 	platform_device_register(&qnap_ts409_nor_flash);
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	orion5x_ehci0_init();
283*4882a593Smuzhiyun 	qnap_tsx09_find_mac_addr(QNAP_TS409_NOR_BOOT_BASE +
284*4882a593Smuzhiyun 				 qnap_ts409_partitions[5].offset,
285*4882a593Smuzhiyun 				 qnap_ts409_partitions[5].size);
286*4882a593Smuzhiyun 	orion5x_eth_init(&qnap_tsx09_eth_data);
287*4882a593Smuzhiyun 	orion5x_i2c_init();
288*4882a593Smuzhiyun 	orion5x_uart0_init();
289*4882a593Smuzhiyun 	orion5x_uart1_init();
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	platform_device_register(&qnap_ts409_button_device);
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	/* Get RTC IRQ and register the chip */
294*4882a593Smuzhiyun 	if (gpio_request(TS409_RTC_GPIO, "rtc") == 0) {
295*4882a593Smuzhiyun 		if (gpio_direction_input(TS409_RTC_GPIO) == 0)
296*4882a593Smuzhiyun 			qnap_ts409_i2c_rtc.irq = gpio_to_irq(TS409_RTC_GPIO);
297*4882a593Smuzhiyun 		else
298*4882a593Smuzhiyun 			gpio_free(TS409_RTC_GPIO);
299*4882a593Smuzhiyun 	}
300*4882a593Smuzhiyun 	if (qnap_ts409_i2c_rtc.irq == 0)
301*4882a593Smuzhiyun 		pr_warn("qnap_ts409_init: failed to get RTC IRQ\n");
302*4882a593Smuzhiyun 	i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1);
303*4882a593Smuzhiyun 	platform_device_register(&ts409_leds);
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	/* register tsx09 specific power-off method */
306*4882a593Smuzhiyun 	pm_power_off = qnap_tsx09_power_off;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun MACHINE_START(TS409, "QNAP TS-409")
310*4882a593Smuzhiyun 	/* Maintainer:  Sylver Bruneau <sylver.bruneau@gmail.com> */
311*4882a593Smuzhiyun 	.atag_offset	= 0x100,
312*4882a593Smuzhiyun 	.nr_irqs	= ORION5X_NR_IRQS,
313*4882a593Smuzhiyun 	.init_machine	= qnap_ts409_init,
314*4882a593Smuzhiyun 	.map_io		= orion5x_map_io,
315*4882a593Smuzhiyun 	.init_early	= orion5x_init_early,
316*4882a593Smuzhiyun 	.init_irq	= orion5x_init_irq,
317*4882a593Smuzhiyun 	.init_time	= orion5x_timer_init,
318*4882a593Smuzhiyun 	.fixup		= tag_fixup_mem32,
319*4882a593Smuzhiyun 	.restart	= orion5x_restart,
320*4882a593Smuzhiyun MACHINE_END
321