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/OK3568_Linux_fs/kernel/drivers/clk/bcm/
H A Dclk-kona.h99 #define POLICY(_offset, _bit) \ argument
159 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
171 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
182 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
193 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ argument
203 #define HW_ONLY_GATE(_offset, _status_bit) \ argument
219 #define HYST(_offset, _en_bit, _val_bit) \ argument
299 #define DIVIDER(_offset, _shift, _width) \ argument
309 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument
350 #define SELECTOR(_offset, _shift, _width) \ argument
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/mellanox/mlxsw/
H A Ditem.h266 #define MLXSW_ITEM8(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
282 #define MLXSW_ITEM8_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
307 #define MLXSW_ITEM16(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
323 #define MLXSW_ITEM16_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
348 #define MLXSW_ITEM32(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
364 #define MLXSW_ITEM32_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
389 #define MLXSW_ITEM64(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
405 #define MLXSW_ITEM64_INDEXED(_type, _cname, _iname, _offset, _shift, \ argument
430 #define MLXSW_ITEM_BUF(_type, _cname, _iname, _offset, _sizebytes) \ argument
454 #define MLXSW_ITEM_BUF_INDEXED(_type, _cname, _iname, _offset, _sizebytes, \ argument
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H A Dcore_acl_flex_keys.h52 #define MLXSW_AFK_ELEMENT_INFO(_type, _element, _offset, _shift, _size) \ argument
64 #define MLXSW_AFK_ELEMENT_INFO_U32(_element, _offset, _shift, _size) \ argument
68 #define MLXSW_AFK_ELEMENT_INFO_BUF(_element, _offset, _size) \ argument
84 #define MLXSW_AFK_ELEMENT_INST(_type, _element, _offset, \ argument
99 #define MLXSW_AFK_ELEMENT_INST_U32(_element, _offset, _shift, _size) \ argument
103 #define MLXSW_AFK_ELEMENT_INST_EXT_U32(_element, _offset, \ argument
110 #define MLXSW_AFK_ELEMENT_INST_BUF(_element, _offset, _size) \ argument
H A Dspectrum_acl.c527 #define MLXSW_SP_ACL_MANGLE_ACTION(_htype, _offset, _mask, _shift, _field) \ argument
536 #define MLXSW_SP_ACL_MANGLE_ACTION_IP4(_offset, _mask, _shift, _field) \ argument
540 #define MLXSW_SP_ACL_MANGLE_ACTION_IP6(_offset, _mask, _shift, _field) \ argument
544 #define MLXSW_SP_ACL_MANGLE_ACTION_TCP(_offset, _mask, _shift, _field) \ argument
547 #define MLXSW_SP_ACL_MANGLE_ACTION_UDP(_offset, _mask, _shift, _field) \ argument
/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk-tegra-periph.c132 #define MUX(_name, _parents, _offset, \ argument
139 #define MUX_FLAGS(_name, _parents, _offset,\ argument
146 #define MUX8(_name, _parents, _offset, \ argument
153 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
159 #define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \ argument
165 #define INT(_name, _parents, _offset, \ argument
172 #define INT_FLAGS(_name, _parents, _offset,\ argument
179 #define INT8(_name, _parents, _offset,\ argument
186 #define UART(_name, _parents, _offset,\ argument
193 #define UART8(_name, _parents, _offset,\ argument
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H A Dclk-tegra30.c155 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
161 #define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \ argument
167 #define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \ argument
174 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
H A Dclk-tegra-audio.c52 #define AUDIO(_name, _offset) \ argument
71 #define AUDIO2X(_name, _num, _offset) \ argument
H A Dclk-tegra20.c133 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
140 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \ argument
147 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
/OK3568_Linux_fs/u-boot/include/fsl-mc/
H A Dfsl_mc_cmd.h71 #define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \ argument
74 #define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \ argument
77 #define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ argument
80 #define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \ argument
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.h175 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
187 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
198 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
209 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ argument
219 #define HW_ONLY_GATE(_offset, _status_bit) \ argument
299 #define DIVIDER(_offset, _shift, _width) \ argument
309 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument
350 #define SELECTOR(_offset, _shift, _width) \ argument
383 #define TRIGGER(_offset, _bit) \ argument
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.h175 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
187 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
198 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
209 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ argument
219 #define HW_ONLY_GATE(_offset, _status_bit) \ argument
299 #define DIVIDER(_offset, _shift, _width) \ argument
309 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument
350 #define SELECTOR(_offset, _shift, _width) \ argument
383 #define TRIGGER(_offset, _bit) \ argument
/OK3568_Linux_fs/kernel/drivers/bcma/
H A Dsprom.c185 #define SPEX(_field, _offset, _mask, _shift) \ argument
188 #define SPEX32(_field, _offset, _mask, _shift) \ argument
192 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A Dccu_mult.h17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument
/OK3568_Linux_fs/kernel/drivers/ssb/
H A Dpci.c171 #define SPEX16(_outvar, _offset, _mask, _shift) \ argument
173 #define SPEX32(_outvar, _offset, _mask, _shift) \ argument
176 #define SPEX(_outvar, _offset, _mask, _shift) \ argument
179 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
/OK3568_Linux_fs/u-boot/drivers/usb/musb-new/
H A Dmusb_regs.h269 #define MUSB_INDEXED_OFFSET(_epnum, _offset) \ argument
273 #define MUSB_FLAT_OFFSET(_epnum, _offset) \ argument
279 #define MUSB_TUSB_OFFSET(_epnum, _offset) \ argument
295 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) \ argument
359 #define MUSB_INDEXED_OFFSET(_epnum, _offset) (_offset) argument
373 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) (_offset) argument
/OK3568_Linux_fs/kernel/drivers/clk/renesas/
H A Drcar-gen3-cpg.h34 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
54 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument
H A Drenesas-cpg-mssr.h53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
55 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
/OK3568_Linux_fs/kernel/drivers/video/rockchip/vehicle/
H A Dvehicle_cif_regs.h17 #define CIF_REG_NAME(_offset, _name) { .offset = (_offset), .name = (_name), } argument
/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dreset_manager.h30 #define RSTMGR_DEFINE(_bank, _offset) \ argument
/OK3568_Linux_fs/kernel/drivers/clk/st/
H A Dclkgen.h38 #define CLKGEN_FIELD(_offset, _mask, _shift) { \ argument
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-stm32mp1.c1092 #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
1119 #define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\ argument
1136 #define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\ argument
1140 #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\ argument
1156 #define PLL(_id, _name, _parent, _flags, _offset)\ argument
1221 #define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
1246 #define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\ argument
1259 #define _MUX(_offset, _shift, _width, _mux_flags)\ argument
1597 #define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\ argument
1610 #define K_MUX(_id, _offset, _shift, _width, _mux_flags)\ argument
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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/
H A Dphl_twt.h148 #define SET_TWT_NOMINAL_MINIMUM_TWT_WAKE_DURATION(_ele_start, _offset, _val) \ argument
150 #define SET_TWT_TWT_WAKE_INTERVAL_MANTISSA(_ele_start, _offset, _val) \ argument
152 #define SET_TWT_TWT_CHANNEL(_ele_start, _offset, _val) \ argument
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/
H A Dphl_twt.h148 #define SET_TWT_NOMINAL_MINIMUM_TWT_WAKE_DURATION(_ele_start, _offset, _val) \ argument
150 #define SET_TWT_TWT_WAKE_INTERVAL_MANTISSA(_ele_start, _offset, _val) \ argument
152 #define SET_TWT_TWT_CHANNEL(_ele_start, _offset, _val) \ argument
/OK3568_Linux_fs/kernel/drivers/staging/rtl8723bs/hal/
H A DHalPhyRf.c12 #define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \ argument
/OK3568_Linux_fs/kernel/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-common.h109 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ argument
134 #define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \ argument
157 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ argument

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