1 /*
2 * MUSB OTG driver register defines
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * SPDX-License-Identifier: GPL-2.0
9 */
10
11 #ifndef __MUSB_REGS_H__
12 #define __MUSB_REGS_H__
13
14 #define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
15
16 /*
17 * MUSB Register bits
18 */
19
20 /* POWER */
21 #define MUSB_POWER_ISOUPDATE 0x80
22 #define MUSB_POWER_SOFTCONN 0x40
23 #define MUSB_POWER_HSENAB 0x20
24 #define MUSB_POWER_HSMODE 0x10
25 #define MUSB_POWER_RESET 0x08
26 #define MUSB_POWER_RESUME 0x04
27 #define MUSB_POWER_SUSPENDM 0x02
28 #define MUSB_POWER_ENSUSPEND 0x01
29
30 /* INTRUSB */
31 #define MUSB_INTR_SUSPEND 0x01
32 #define MUSB_INTR_RESUME 0x02
33 #define MUSB_INTR_RESET 0x04
34 #define MUSB_INTR_BABBLE 0x04
35 #define MUSB_INTR_SOF 0x08
36 #define MUSB_INTR_CONNECT 0x10
37 #define MUSB_INTR_DISCONNECT 0x20
38 #define MUSB_INTR_SESSREQ 0x40
39 #define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */
40
41 /* DEVCTL */
42 #define MUSB_DEVCTL_BDEVICE 0x80
43 #define MUSB_DEVCTL_FSDEV 0x40
44 #define MUSB_DEVCTL_LSDEV 0x20
45 #define MUSB_DEVCTL_VBUS 0x18
46 #define MUSB_DEVCTL_VBUS_SHIFT 3
47 #define MUSB_DEVCTL_HM 0x04
48 #define MUSB_DEVCTL_HR 0x02
49 #define MUSB_DEVCTL_SESSION 0x01
50
51 /* MUSB ULPI VBUSCONTROL */
52 #define MUSB_ULPI_USE_EXTVBUS 0x01
53 #define MUSB_ULPI_USE_EXTVBUSIND 0x02
54 /* ULPI_REG_CONTROL */
55 #define MUSB_ULPI_REG_REQ (1 << 0)
56 #define MUSB_ULPI_REG_CMPLT (1 << 1)
57 #define MUSB_ULPI_RDN_WR (1 << 2)
58
59 /* TESTMODE */
60 #define MUSB_TEST_FORCE_HOST 0x80
61 #define MUSB_TEST_FIFO_ACCESS 0x40
62 #define MUSB_TEST_FORCE_FS 0x20
63 #define MUSB_TEST_FORCE_HS 0x10
64 #define MUSB_TEST_PACKET 0x08
65 #define MUSB_TEST_K 0x04
66 #define MUSB_TEST_J 0x02
67 #define MUSB_TEST_SE0_NAK 0x01
68
69 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
70 #define MUSB_FIFOSZ_DPB 0x10
71 /* Allocation size (8, 16, 32, ... 4096) */
72 #define MUSB_FIFOSZ_SIZE 0x0f
73
74 /* CSR0 */
75 #define MUSB_CSR0_FLUSHFIFO 0x0100
76 #define MUSB_CSR0_TXPKTRDY 0x0002
77 #define MUSB_CSR0_RXPKTRDY 0x0001
78
79 /* CSR0 in Peripheral mode */
80 #define MUSB_CSR0_P_SVDSETUPEND 0x0080
81 #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
82 #define MUSB_CSR0_P_SENDSTALL 0x0020
83 #define MUSB_CSR0_P_SETUPEND 0x0010
84 #define MUSB_CSR0_P_DATAEND 0x0008
85 #define MUSB_CSR0_P_SENTSTALL 0x0004
86
87 /* CSR0 in Host mode */
88 #define MUSB_CSR0_H_DIS_PING 0x0800
89 #define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */
90 #define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */
91 #define MUSB_CSR0_H_NAKTIMEOUT 0x0080
92 #define MUSB_CSR0_H_STATUSPKT 0x0040
93 #define MUSB_CSR0_H_REQPKT 0x0020
94 #define MUSB_CSR0_H_ERROR 0x0010
95 #define MUSB_CSR0_H_SETUPPKT 0x0008
96 #define MUSB_CSR0_H_RXSTALL 0x0004
97
98 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
99 #define MUSB_CSR0_P_WZC_BITS \
100 (MUSB_CSR0_P_SENTSTALL)
101 #define MUSB_CSR0_H_WZC_BITS \
102 (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
103 | MUSB_CSR0_RXPKTRDY)
104
105 /* TxType/RxType */
106 #define MUSB_TYPE_SPEED 0xc0
107 #define MUSB_TYPE_SPEED_SHIFT 6
108 #define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */
109 #define MUSB_TYPE_PROTO_SHIFT 4
110 #define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */
111
112 /* CONFIGDATA */
113 #define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */
114 #define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */
115 #define MUSB_CONFIGDATA_BIGENDIAN 0x20
116 #define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
117 #define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
118 #define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */
119 #define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
120 #define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */
121
122 /* TXCSR in Peripheral and Host mode */
123 #define MUSB_TXCSR_AUTOSET 0x8000
124 #define MUSB_TXCSR_DMAENAB 0x1000
125 #define MUSB_TXCSR_FRCDATATOG 0x0800
126 #define MUSB_TXCSR_DMAMODE 0x0400
127 #define MUSB_TXCSR_CLRDATATOG 0x0040
128 #define MUSB_TXCSR_FLUSHFIFO 0x0008
129 #define MUSB_TXCSR_FIFONOTEMPTY 0x0002
130 #define MUSB_TXCSR_TXPKTRDY 0x0001
131
132 /* TXCSR in Peripheral mode */
133 #define MUSB_TXCSR_P_ISO 0x4000
134 #define MUSB_TXCSR_P_INCOMPTX 0x0080
135 #define MUSB_TXCSR_P_SENTSTALL 0x0020
136 #define MUSB_TXCSR_P_SENDSTALL 0x0010
137 #define MUSB_TXCSR_P_UNDERRUN 0x0004
138
139 /* TXCSR in Host mode */
140 #define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200
141 #define MUSB_TXCSR_H_DATATOGGLE 0x0100
142 #define MUSB_TXCSR_H_NAKTIMEOUT 0x0080
143 #define MUSB_TXCSR_H_RXSTALL 0x0020
144 #define MUSB_TXCSR_H_ERROR 0x0004
145
146 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
147 #define MUSB_TXCSR_P_WZC_BITS \
148 (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
149 | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
150 #define MUSB_TXCSR_H_WZC_BITS \
151 (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
152 | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
153
154 /* RXCSR in Peripheral and Host mode */
155 #define MUSB_RXCSR_AUTOCLEAR 0x8000
156 #define MUSB_RXCSR_DMAENAB 0x2000
157 #define MUSB_RXCSR_DISNYET 0x1000
158 #define MUSB_RXCSR_PID_ERR 0x1000
159 #define MUSB_RXCSR_DMAMODE 0x0800
160 #define MUSB_RXCSR_INCOMPRX 0x0100
161 #define MUSB_RXCSR_CLRDATATOG 0x0080
162 #define MUSB_RXCSR_FLUSHFIFO 0x0010
163 #define MUSB_RXCSR_DATAERROR 0x0008
164 #define MUSB_RXCSR_FIFOFULL 0x0002
165 #define MUSB_RXCSR_RXPKTRDY 0x0001
166
167 /* RXCSR in Peripheral mode */
168 #define MUSB_RXCSR_P_ISO 0x4000
169 #define MUSB_RXCSR_P_SENTSTALL 0x0040
170 #define MUSB_RXCSR_P_SENDSTALL 0x0020
171 #define MUSB_RXCSR_P_OVERRUN 0x0004
172
173 /* RXCSR in Host mode */
174 #define MUSB_RXCSR_H_AUTOREQ 0x4000
175 #define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400
176 #define MUSB_RXCSR_H_DATATOGGLE 0x0200
177 #define MUSB_RXCSR_H_RXSTALL 0x0040
178 #define MUSB_RXCSR_H_REQPKT 0x0020
179 #define MUSB_RXCSR_H_ERROR 0x0004
180
181 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
182 #define MUSB_RXCSR_P_WZC_BITS \
183 (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
184 | MUSB_RXCSR_RXPKTRDY)
185 #define MUSB_RXCSR_H_WZC_BITS \
186 (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
187 | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
188
189 /* HUBADDR */
190 #define MUSB_HUBADDR_MULTI_TT 0x80
191
192
193 /* SUNXI has different reg addresses, but identical r/w functions */
194 #ifndef CONFIG_ARCH_SUNXI
195
196 /*
197 * Common USB registers
198 */
199
200 #define MUSB_FADDR 0x00 /* 8-bit */
201 #define MUSB_POWER 0x01 /* 8-bit */
202
203 #define MUSB_INTRTX 0x02 /* 16-bit */
204 #define MUSB_INTRRX 0x04
205 #define MUSB_INTRTXE 0x06
206 #define MUSB_INTRRXE 0x08
207 #define MUSB_INTRUSB 0x0A /* 8 bit */
208 #define MUSB_INTRUSBE 0x0B /* 8 bit */
209 #define MUSB_FRAME 0x0C
210 #define MUSB_INDEX 0x0E /* 8 bit */
211 #define MUSB_TESTMODE 0x0F /* 8 bit */
212
213 /* Get offset for a given FIFO from musb->mregs */
214 #if defined(CONFIG_USB_MUSB_TUSB6010) || \
215 defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
216 #define MUSB_FIFO_OFFSET(epnum) (0x200 + ((epnum) * 0x20))
217 #else
218 #define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4))
219 #endif
220
221 /*
222 * Additional Control Registers
223 */
224
225 #define MUSB_DEVCTL 0x60 /* 8 bit */
226
227 /* These are always controlled through the INDEX register */
228 #define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */
229 #define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */
230 #define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */
231 #define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */
232
233 /* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
234 #define MUSB_HWVERS 0x6C /* 8 bit */
235 #define MUSB_ULPI_BUSCONTROL 0x70 /* 8 bit */
236 #define MUSB_ULPI_INT_MASK 0x72 /* 8 bit */
237 #define MUSB_ULPI_INT_SRC 0x73 /* 8 bit */
238 #define MUSB_ULPI_REG_DATA 0x74 /* 8 bit */
239 #define MUSB_ULPI_REG_ADDR 0x75 /* 8 bit */
240 #define MUSB_ULPI_REG_CONTROL 0x76 /* 8 bit */
241 #define MUSB_ULPI_RAW_DATA 0x77 /* 8 bit */
242
243 #define MUSB_EPINFO 0x78 /* 8 bit */
244 #define MUSB_RAMINFO 0x79 /* 8 bit */
245 #define MUSB_LINKINFO 0x7a /* 8 bit */
246 #define MUSB_VPLEN 0x7b /* 8 bit */
247 #define MUSB_HS_EOF1 0x7c /* 8 bit */
248 #define MUSB_FS_EOF1 0x7d /* 8 bit */
249 #define MUSB_LS_EOF1 0x7e /* 8 bit */
250
251 /* Offsets to endpoint registers */
252 #define MUSB_TXMAXP 0x00
253 #define MUSB_TXCSR 0x02
254 #define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
255 #define MUSB_RXMAXP 0x04
256 #define MUSB_RXCSR 0x06
257 #define MUSB_RXCOUNT 0x08
258 #define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
259 #define MUSB_TXTYPE 0x0A
260 #define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
261 #define MUSB_TXINTERVAL 0x0B
262 #define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
263 #define MUSB_RXTYPE 0x0C
264 #define MUSB_RXINTERVAL 0x0D
265 #define MUSB_FIFOSIZE 0x0F
266 #define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */
267
268 /* Offsets to endpoint registers in indexed model (using INDEX register) */
269 #define MUSB_INDEXED_OFFSET(_epnum, _offset) \
270 (0x10 + (_offset))
271
272 /* Offsets to endpoint registers in flat models */
273 #define MUSB_FLAT_OFFSET(_epnum, _offset) \
274 (0x100 + (0x10*(_epnum)) + (_offset))
275
276 #if defined(CONFIG_USB_MUSB_TUSB6010) || \
277 defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
278 /* TUSB6010 EP0 configuration register is special */
279 #define MUSB_TUSB_OFFSET(_epnum, _offset) \
280 (0x10 + _offset)
281 #include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */
282 #endif
283
284 #define MUSB_TXCSR_MODE 0x2000
285
286 /* "bus control"/target registers, for host side multipoint (external hubs) */
287 #define MUSB_TXFUNCADDR 0x00
288 #define MUSB_TXHUBADDR 0x02
289 #define MUSB_TXHUBPORT 0x03
290
291 #define MUSB_RXFUNCADDR 0x04
292 #define MUSB_RXHUBADDR 0x06
293 #define MUSB_RXHUBPORT 0x07
294
295 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
296 (0x80 + (8*(_epnum)) + (_offset))
297
298 #else /* CONFIG_ARCH_SUNXI */
299
300 /*
301 * Common USB registers
302 */
303
304 #define MUSB_FADDR 0x0098
305 #define MUSB_POWER 0x0040
306
307 #define MUSB_INTRTX 0x0044
308 #define MUSB_INTRRX 0x0046
309 #define MUSB_INTRTXE 0x0048
310 #define MUSB_INTRRXE 0x004A
311 #define MUSB_INTRUSB 0x004C
312 #define MUSB_INTRUSBE 0x0050
313 #define MUSB_FRAME 0x0054
314 #define MUSB_INDEX 0x0042
315 #define MUSB_TESTMODE 0x007C
316
317 /* Get offset for a given FIFO from musb->mregs */
318 #define MUSB_FIFO_OFFSET(epnum) (0x00 + ((epnum) * 4))
319
320 /*
321 * Additional Control Registers
322 */
323
324 #define MUSB_DEVCTL 0x0041
325
326 /* These are always controlled through the INDEX register */
327 #define MUSB_TXFIFOSZ 0x0090
328 #define MUSB_RXFIFOSZ 0x0094
329 #define MUSB_TXFIFOADD 0x0092
330 #define MUSB_RXFIFOADD 0x0096
331
332 #define MUSB_EPINFO 0x0078
333 #define MUSB_RAMINFO 0x0079
334 #define MUSB_LINKINFO 0x007A
335 #define MUSB_VPLEN 0x007B
336 #define MUSB_HS_EOF1 0x007C
337 #define MUSB_FS_EOF1 0x007D
338 #define MUSB_LS_EOF1 0x007E
339
340 /* Offsets to endpoint registers */
341 #define MUSB_TXMAXP 0x0080
342 #define MUSB_TXCSR 0x0082
343 #define MUSB_CSR0 0x0082
344 #define MUSB_RXMAXP 0x0084
345 #define MUSB_RXCSR 0x0086
346 #define MUSB_RXCOUNT 0x0088
347 #define MUSB_COUNT0 0x0088
348 #define MUSB_TXTYPE 0x008C
349 #define MUSB_TYPE0 0x008C
350 #define MUSB_TXINTERVAL 0x008D
351 #define MUSB_NAKLIMIT0 0x008D
352 #define MUSB_RXTYPE 0x008E
353 #define MUSB_RXINTERVAL 0x008F
354
355 #define MUSB_CONFIGDATA 0x00b0 /* musb_read_configdata adds 0x10 ! */
356 #define MUSB_FIFOSIZE 0x0090
357
358 /* Offsets to endpoint registers in indexed model (using INDEX register) */
359 #define MUSB_INDEXED_OFFSET(_epnum, _offset) (_offset)
360
361 #define MUSB_TXCSR_MODE 0x2000
362
363 /* "bus control"/target registers, for host side multipoint (external hubs) */
364 #define MUSB_TXFUNCADDR 0x0098
365 #define MUSB_TXHUBADDR 0x009A
366 #define MUSB_TXHUBPORT 0x009B
367
368 #define MUSB_RXFUNCADDR 0x009C
369 #define MUSB_RXHUBADDR 0x009E
370 #define MUSB_RXHUBPORT 0x009F
371
372 /* Endpoint is selected with MUSB_INDEX. */
373 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) (_offset)
374
375 #endif /* CONFIG_ARCH_SUNXI */
376
musb_write_txfifosz(void __iomem * mbase,u8 c_size)377 static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
378 {
379 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
380 }
381
musb_write_txfifoadd(void __iomem * mbase,u16 c_off)382 static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
383 {
384 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
385 }
386
musb_write_rxfifosz(void __iomem * mbase,u8 c_size)387 static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
388 {
389 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
390 }
391
musb_write_rxfifoadd(void __iomem * mbase,u16 c_off)392 static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
393 {
394 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
395 }
396
musb_write_ulpi_buscontrol(void __iomem * mbase,u8 val)397 static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
398 {
399 #ifndef CONFIG_ARCH_SUNXI /* No ulpi on sunxi */
400 musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val);
401 #endif
402 }
403
musb_read_txfifosz(void __iomem * mbase)404 static inline u8 musb_read_txfifosz(void __iomem *mbase)
405 {
406 return musb_readb(mbase, MUSB_TXFIFOSZ);
407 }
408
musb_read_txfifoadd(void __iomem * mbase)409 static inline u16 musb_read_txfifoadd(void __iomem *mbase)
410 {
411 return musb_readw(mbase, MUSB_TXFIFOADD);
412 }
413
musb_read_rxfifosz(void __iomem * mbase)414 static inline u8 musb_read_rxfifosz(void __iomem *mbase)
415 {
416 return musb_readb(mbase, MUSB_RXFIFOSZ);
417 }
418
musb_read_rxfifoadd(void __iomem * mbase)419 static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
420 {
421 return musb_readw(mbase, MUSB_RXFIFOADD);
422 }
423
musb_read_ulpi_buscontrol(void __iomem * mbase)424 static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
425 {
426 #ifdef CONFIG_ARCH_SUNXI /* No ulpi on sunxi */
427 return 0;
428 #else
429 return musb_readb(mbase, MUSB_ULPI_BUSCONTROL);
430 #endif
431 }
432
musb_read_configdata(void __iomem * mbase)433 static inline u8 musb_read_configdata(void __iomem *mbase)
434 {
435 #if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T
436 /* <Sigh> allwinner saves a reg, and we need to hardcode this */
437 return 0xde;
438 #else
439 musb_writeb(mbase, MUSB_INDEX, 0);
440 return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
441 #endif
442 }
443
musb_read_hwvers(void __iomem * mbase)444 static inline u16 musb_read_hwvers(void __iomem *mbase)
445 {
446 #ifdef CONFIG_ARCH_SUNXI
447 return 0; /* Unknown version */
448 #else
449 return musb_readw(mbase, MUSB_HWVERS);
450 #endif
451 }
452
musb_read_target_reg_base(u8 i,void __iomem * mbase)453 static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
454 {
455 return (MUSB_BUSCTL_OFFSET(i, 0) + mbase);
456 }
457
musb_write_rxfunaddr(void __iomem * ep_target_regs,u8 qh_addr_reg)458 static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
459 u8 qh_addr_reg)
460 {
461 musb_writeb(ep_target_regs, MUSB_RXFUNCADDR, qh_addr_reg);
462 }
463
musb_write_rxhubaddr(void __iomem * ep_target_regs,u8 qh_h_addr_reg)464 static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
465 u8 qh_h_addr_reg)
466 {
467 musb_writeb(ep_target_regs, MUSB_RXHUBADDR, qh_h_addr_reg);
468 }
469
musb_write_rxhubport(void __iomem * ep_target_regs,u8 qh_h_port_reg)470 static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
471 u8 qh_h_port_reg)
472 {
473 musb_writeb(ep_target_regs, MUSB_RXHUBPORT, qh_h_port_reg);
474 }
475
musb_write_txfunaddr(void __iomem * mbase,u8 epnum,u8 qh_addr_reg)476 static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
477 u8 qh_addr_reg)
478 {
479 musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR),
480 qh_addr_reg);
481 }
482
musb_write_txhubaddr(void __iomem * mbase,u8 epnum,u8 qh_addr_reg)483 static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
484 u8 qh_addr_reg)
485 {
486 musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR),
487 qh_addr_reg);
488 }
489
musb_write_txhubport(void __iomem * mbase,u8 epnum,u8 qh_h_port_reg)490 static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
491 u8 qh_h_port_reg)
492 {
493 musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT),
494 qh_h_port_reg);
495 }
496
musb_read_rxfunaddr(void __iomem * mbase,u8 epnum)497 static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
498 {
499 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXFUNCADDR));
500 }
501
musb_read_rxhubaddr(void __iomem * mbase,u8 epnum)502 static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
503 {
504 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBADDR));
505 }
506
musb_read_rxhubport(void __iomem * mbase,u8 epnum)507 static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
508 {
509 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBPORT));
510 }
511
musb_read_txfunaddr(void __iomem * mbase,u8 epnum)512 static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
513 {
514 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR));
515 }
516
musb_read_txhubaddr(void __iomem * mbase,u8 epnum)517 static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
518 {
519 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR));
520 }
521
musb_read_txhubport(void __iomem * mbase,u8 epnum)522 static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
523 {
524 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT));
525 }
526
527 #endif /* __MUSB_REGS_H__ */
528