1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _RESET_MANAGER_H_ 8*4882a593Smuzhiyun #define _RESET_MANAGER_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun void reset_cpu(ulong addr); 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun void socfpga_per_reset(u32 reset, int set); 13*4882a593Smuzhiyun void socfpga_per_reset_all(void); 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 16*4882a593Smuzhiyun #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 17*4882a593Smuzhiyun #else 18*4882a593Smuzhiyun #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 19*4882a593Smuzhiyun #endif 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * Define a reset identifier, from which a permodrst bank ID 23*4882a593Smuzhiyun * and reset ID can be extracted using the subsequent macros 24*4882a593Smuzhiyun * RSTMGR_RESET() and RSTMGR_BANK(). 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define RSTMGR_BANK_OFFSET 8 27*4882a593Smuzhiyun #define RSTMGR_BANK_MASK 0x7 28*4882a593Smuzhiyun #define RSTMGR_RESET_OFFSET 0 29*4882a593Smuzhiyun #define RSTMGR_RESET_MASK 0x1f 30*4882a593Smuzhiyun #define RSTMGR_DEFINE(_bank, _offset) \ 31*4882a593Smuzhiyun ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Extract reset ID from the reset identifier. */ 34*4882a593Smuzhiyun #define RSTMGR_RESET(_reset) \ 35*4882a593Smuzhiyun (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Extract bank ID from the reset identifier. */ 38*4882a593Smuzhiyun #define RSTMGR_BANK(_reset) \ 39*4882a593Smuzhiyun (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Create a human-readable reference to SoCFPGA reset. */ 42*4882a593Smuzhiyun #define SOCFPGA_RESET(_name) RSTMGR_##_name 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 45*4882a593Smuzhiyun #include <asm/arch/reset_manager_gen5.h> 46*4882a593Smuzhiyun #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 47*4882a593Smuzhiyun #include <asm/arch/reset_manager_arria10.h> 48*4882a593Smuzhiyun #endif 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif /* _RESET_MANAGER_H_ */ 51