1*4882a593Smuzhiyun /* Copyright 2013-2015 Freescale Semiconductor Inc.
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun #ifndef __FSL_MC_CMD_H
6*4882a593Smuzhiyun #define __FSL_MC_CMD_H
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #define MC_CMD_NUM_OF_PARAMS 7
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #define MAKE_UMASK64(_width) \
11*4882a593Smuzhiyun ((uint64_t)((_width) < 64 ? ((uint64_t)1 << (_width)) - 1 : -1))
12*4882a593Smuzhiyun
mc_enc(int lsoffset,int width,uint64_t val)13*4882a593Smuzhiyun static inline uint64_t mc_enc(int lsoffset, int width, uint64_t val)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun return (uint64_t)(((uint64_t)val & MAKE_UMASK64(width)) << lsoffset);
16*4882a593Smuzhiyun }
mc_dec(uint64_t val,int lsoffset,int width)17*4882a593Smuzhiyun static inline uint64_t mc_dec(uint64_t val, int lsoffset, int width)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun return (uint64_t)((val >> lsoffset) & MAKE_UMASK64(width));
20*4882a593Smuzhiyun }
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun struct mc_command {
23*4882a593Smuzhiyun uint64_t header;
24*4882a593Smuzhiyun uint64_t params[MC_CMD_NUM_OF_PARAMS];
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun enum mc_cmd_status {
28*4882a593Smuzhiyun MC_CMD_STATUS_OK = 0x0, /*!< Completed successfully */
29*4882a593Smuzhiyun MC_CMD_STATUS_READY = 0x1, /*!< Ready to be processed */
30*4882a593Smuzhiyun MC_CMD_STATUS_AUTH_ERR = 0x3, /*!< Authentication error */
31*4882a593Smuzhiyun MC_CMD_STATUS_NO_PRIVILEGE = 0x4, /*!< No privilege */
32*4882a593Smuzhiyun MC_CMD_STATUS_DMA_ERR = 0x5, /*!< DMA or I/O error */
33*4882a593Smuzhiyun MC_CMD_STATUS_CONFIG_ERR = 0x6, /*!< Configuration error */
34*4882a593Smuzhiyun MC_CMD_STATUS_TIMEOUT = 0x7, /*!< Operation timed out */
35*4882a593Smuzhiyun MC_CMD_STATUS_NO_RESOURCE = 0x8, /*!< No resources */
36*4882a593Smuzhiyun MC_CMD_STATUS_NO_MEMORY = 0x9, /*!< No memory available */
37*4882a593Smuzhiyun MC_CMD_STATUS_BUSY = 0xA, /*!< Device is busy */
38*4882a593Smuzhiyun MC_CMD_STATUS_UNSUPPORTED_OP = 0xB, /*!< Unsupported operation */
39*4882a593Smuzhiyun MC_CMD_STATUS_INVALID_STATE = 0xC /*!< Invalid state */
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /*
43*4882a593Smuzhiyun * MC command flags
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* High priority flag */
47*4882a593Smuzhiyun #define MC_CMD_FLAG_PRI 0x00008000
48*4882a593Smuzhiyun /* No flags */
49*4882a593Smuzhiyun #define MC_CMD_NO_FLAGS 0x00000000
50*4882a593Smuzhiyun /* Command completion flag */
51*4882a593Smuzhiyun #define MC_CMD_FLAG_INTR_DIS 0x01000000
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define MC_CMD_HDR_CMDID_O 52 /* Command ID field offset */
55*4882a593Smuzhiyun #define MC_CMD_HDR_CMDID_S 12 /* Command ID field size */
56*4882a593Smuzhiyun #define MC_CMD_HDR_STATUS_O 16 /* Status field offset */
57*4882a593Smuzhiyun #define MC_CMD_HDR_TOKEN_O 38 /* Token field offset */
58*4882a593Smuzhiyun #define MC_CMD_HDR_TOKEN_S 10 /* Token field size */
59*4882a593Smuzhiyun #define MC_CMD_HDR_STATUS_S 8 /* Status field size*/
60*4882a593Smuzhiyun #define MC_CMD_HDR_FLAGS_O 0 /* Flags field offset */
61*4882a593Smuzhiyun #define MC_CMD_HDR_FLAGS_S 32 /* Flags field size*/
62*4882a593Smuzhiyun #define MC_CMD_HDR_FLAGS_MASK 0xFF00FF00 /* Command flags mask */
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define MC_CMD_HDR_READ_STATUS(_hdr) \
65*4882a593Smuzhiyun ((enum mc_cmd_status)mc_dec((_hdr), \
66*4882a593Smuzhiyun MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S))
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun #define MC_CMD_HDR_READ_TOKEN(_hdr) \
69*4882a593Smuzhiyun ((uint16_t)mc_dec((_hdr), MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S))
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \
72*4882a593Smuzhiyun ((_ext)[_param] |= cpu_to_le64(mc_enc((_offset), (_width), _arg)))
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \
75*4882a593Smuzhiyun (_arg = (_type)mc_dec(cpu_to_le64(_ext[_param]), (_offset), (_width)))
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \
78*4882a593Smuzhiyun ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg))
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun #define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \
81*4882a593Smuzhiyun (_arg = (_type)mc_dec(_cmd.params[_param], (_offset), (_width)))
82*4882a593Smuzhiyun
mc_encode_cmd_header(uint16_t cmd_id,uint32_t cmd_flags,uint16_t token)83*4882a593Smuzhiyun static inline uint64_t mc_encode_cmd_header(uint16_t cmd_id,
84*4882a593Smuzhiyun uint32_t cmd_flags,
85*4882a593Smuzhiyun uint16_t token)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun uint64_t hdr;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun hdr = mc_enc(MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S, cmd_id);
90*4882a593Smuzhiyun hdr |= mc_enc(MC_CMD_HDR_FLAGS_O, MC_CMD_HDR_FLAGS_S,
91*4882a593Smuzhiyun (cmd_flags & MC_CMD_HDR_FLAGS_MASK));
92*4882a593Smuzhiyun hdr |= mc_enc(MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S, token);
93*4882a593Smuzhiyun hdr |= mc_enc(MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S,
94*4882a593Smuzhiyun MC_CMD_STATUS_READY);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return hdr;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /**
100*4882a593Smuzhiyun * mc_write_command - writes a command to a Management Complex (MC) portal
101*4882a593Smuzhiyun *
102*4882a593Smuzhiyun * @portal: pointer to an MC portal
103*4882a593Smuzhiyun * @cmd: pointer to a filled command
104*4882a593Smuzhiyun */
mc_write_command(struct mc_command __iomem * portal,struct mc_command * cmd)105*4882a593Smuzhiyun static inline void mc_write_command(struct mc_command __iomem *portal,
106*4882a593Smuzhiyun struct mc_command *cmd)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun int i;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* copy command parameters into the portal */
111*4882a593Smuzhiyun for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++)
112*4882a593Smuzhiyun writeq(cmd->params[i], &portal->params[i]);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* submit the command by writing the header */
115*4882a593Smuzhiyun writeq(cmd->header, &portal->header);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /**
119*4882a593Smuzhiyun * mc_read_response - reads the response for the last MC command from a
120*4882a593Smuzhiyun * Management Complex (MC) portal
121*4882a593Smuzhiyun *
122*4882a593Smuzhiyun * @portal: pointer to an MC portal
123*4882a593Smuzhiyun * @resp: pointer to command response buffer
124*4882a593Smuzhiyun *
125*4882a593Smuzhiyun * Returns MC_CMD_STATUS_OK on Success; Error code otherwise.
126*4882a593Smuzhiyun */
mc_read_response(struct mc_command __iomem * portal,struct mc_command * resp)127*4882a593Smuzhiyun static inline enum mc_cmd_status mc_read_response(
128*4882a593Smuzhiyun struct mc_command __iomem *portal,
129*4882a593Smuzhiyun struct mc_command *resp)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun int i;
132*4882a593Smuzhiyun enum mc_cmd_status status;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /* Copy command response header from MC portal: */
135*4882a593Smuzhiyun resp->header = readq(&portal->header);
136*4882a593Smuzhiyun status = MC_CMD_HDR_READ_STATUS(resp->header);
137*4882a593Smuzhiyun if (status != MC_CMD_STATUS_OK)
138*4882a593Smuzhiyun return status;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /* Copy command response data from MC portal: */
141*4882a593Smuzhiyun for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++)
142*4882a593Smuzhiyun resp->params[i] = readq(&portal->params[i]);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun return status;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun #endif /* __FSL_MC_CMD_H */
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