| /rk3399_ARM-atf/plat/renesas/common/include/ |
| H A D | platform_def.h | 115 #define BL2_BASE U(0xE6304000) macro
118 #define BL2_BASE U(0xE6344000) macro
121 #define BL2_BASE U(0xE6304000) macro
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| /rk3399_ARM-atf/plat/brcm/board/stingray/include/ |
| H A D | platform_def.h | 112 #define BL2_BASE QSPI_BASE_ADDR macro
118 #define BL2_BASE NAND_BASE_ADDR macro
124 #define BL2_BASE (BL1_RW_LIMIT + PAGE_SIZE) macro
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| /rk3399_ARM-atf/plat/qti/kodiak/rb3gen2/inc/ |
| H A D | platform_def.h | 15 #define BL2_BASE 0x1c00e000 macro
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| /rk3399_ARM-atf/plat/hisilicon/poplar/include/ |
| H A D | poplar_layout.h | 125 #define BL2_BASE (LLOADER_TEXT_BASE + BL2_OFFSET) macro
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| /rk3399_ARM-atf/plat/socionext/uniphier/include/ |
| H A D | platform_def.h | 53 #define BL2_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL2_OFFSET) macro
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| /rk3399_ARM-atf/plat/hisilicon/hikey/include/ |
| H A D | hikey_layout.h | 63 #define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */ macro
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| /rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/include/ |
| H A D | platform_def.h | 36 #define BL2_BASE UL(0x34078000) macro
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| /rk3399_ARM-atf/plat/hisilicon/hikey960/include/ |
| H A D | platform_def.h | 61 #define BL2_BASE (0x1AC00000) macro
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| /rk3399_ARM-atf/include/plat/marvell/armada/a3k/common/ |
| H A D | marvell_def.h | 160 #define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE) macro
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| /rk3399_ARM-atf/plat/st/stm32mp1/include/ |
| H A D | platform_def.h | 50 #define BL2_BASE STM32MP_BL2_BASE macro
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| /rk3399_ARM-atf/plat/st/stm32mp2/include/ |
| H A D | platform_def.h | 61 #define BL2_BASE STM32MP_BL2_BASE macro
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| /rk3399_ARM-atf/plat/intel/soc/stratix10/include/ |
| H A D | socfpga_plat_def.h | 79 #define BL2_BASE (0xffe00000) macro
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| /rk3399_ARM-atf/include/plat/marvell/armada/a8k/common/ |
| H A D | marvell_def.h | 196 #define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE) macro
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| /rk3399_ARM-atf/include/plat/nuvoton/common/ |
| H A D | npcm845x_arm_def.h | 443 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ macro
450 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) macro
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| /rk3399_ARM-atf/plat/intel/soc/n5x/include/ |
| H A D | socfpga_plat_def.h | 79 #define BL2_BASE (0xffe00000) macro
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| /rk3399_ARM-atf/plat/imx/imx7/picopi/include/ |
| H A D | platform_def.h | 118 #define BL2_BASE BL2_RAM_BASE macro
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| /rk3399_ARM-atf/plat/intel/soc/agilex/include/ |
| H A D | socfpga_plat_def.h | 95 #define BL2_BASE (0xffe00000) macro
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| /rk3399_ARM-atf/plat/imx/imx7/warp7/include/ |
| H A D | platform_def.h | 121 #define BL2_BASE BL2_RAM_BASE macro
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| /rk3399_ARM-atf/plat/intel/soc/agilex5/include/ |
| H A D | socfpga_plat_def.h | 146 #define BL2_BASE (0x00000000) macro
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| /rk3399_ARM-atf/plat/socionext/synquacer/include/ |
| H A D | platform_def.h | 64 #define BL2_BASE 0x04000000 macro
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| /rk3399_ARM-atf/plat/rpi/rpi3/include/ |
| H A D | platform_def.h | 190 #define BL2_BASE (BL2_LIMIT - PLAT_MAX_BL2_SIZE) macro
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| /rk3399_ARM-atf/include/plat/arm/common/ |
| H A D | arm_def.h | 602 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ macro
611 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) macro
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| /rk3399_ARM-atf/plat/arm/board/fvp_ve/include/ |
| H A D | platform_def.h | 221 #define BL2_BASE (BL1_RW_BASE - FVP_VE_MAX_BL2_SIZE) macro
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| /rk3399_ARM-atf/plat/arm/board/a5ds/include/ |
| H A D | platform_def.h | 236 #define BL2_BASE (BL1_RW_BASE - A5DS_MAX_BL2_SIZE) macro
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| /rk3399_ARM-atf/plat/arm/board/corstone1000/common/include/ |
| H A D | platform_def.h | 133 #define BL2_BASE (BL2_LIMIT - \ macro
|