Merge changes Ic735cd1c,Iba4cdbf5,I0dd74152,I3a051ca2,Ie413233d, ... into integration

* changes:
feat(stm32mp2): add RIFSC/RISAB protection for USB3DR
feat(st-drivers): add RIFSC driver
feat(s

Merge changes Ic735cd1c,Iba4cdbf5,I0dd74152,I3a051ca2,Ie413233d, ... into integration

* changes:
feat(stm32mp2): add RIFSC/RISAB protection for USB3DR
feat(st-drivers): add RIFSC driver
feat(stm32mp2): add STM32MP_USB_PROGRAMMER support
feat(stm32mp2): generate FIP for DDR initialization
feat(stm32mp2): add support for minimal FIP with only DDR FW
fix(st): allow several call of stm32cubeprog_uart_load
feat(st): update stm32cubeprogrammer API
feat(stm32mp1): add stm32_get_uid_otp
feat(st-usb): add USB DWC3 driver
fix(st): replace down counter by a timeout upon dfu detach

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feat(stm32mp2): add support for minimal FIP with only DDR FW

Load a minimal FIP used for DDR initialization for serial boot
when STM32MP_DDR_FIP_IO_STORAGE is activated.

This DDR FIP is loaded at t

feat(stm32mp2): add support for minimal FIP with only DDR FW

Load a minimal FIP used for DDR initialization for serial boot
when STM32MP_DDR_FIP_IO_STORAGE is activated.

This DDR FIP is loaded at the beginning of SYSRAM and used with
support of memmap features.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie413233de0e4d785b2d669087da34110df557ad3

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Merge changes Ie8c83c92,I9cca19fd into integration

* changes:
feat(stm32mp2): disable PIE by default on STM32MP2 platform
refactor(stm32mp2): remove useless STM32MP_SEC_SYSRAM_SIZE

feat(stm32mp2): disable PIE by default on STM32MP2 platform

Allow to disable ENABLE_PIE on STM32MP2. BL31 is loaded at the beginning
of SYSRAM whatever the options set. Set ENABLE_PIE to 0 by defaul

feat(stm32mp2): disable PIE by default on STM32MP2 platform

Allow to disable ENABLE_PIE on STM32MP2. BL31 is loaded at the beginning
of SYSRAM whatever the options set. Set ENABLE_PIE to 0 by default.
This should allow us to reduce BL31 and BL2 size.

Change-Id: Ie8c83c9205e81301eb1fdcf24b94216172586630
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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refactor(stm32mp2): remove useless STM32MP_SEC_SYSRAM_SIZE

The macro STM32MP_SEC_SYSRAM_SIZE only redefine STM32MP_SYSRAM_SIZE.
Directly use the latter one and remove the STM32MP_SEC_SYSRAM_SIZE.

S

refactor(stm32mp2): remove useless STM32MP_SEC_SYSRAM_SIZE

The macro STM32MP_SEC_SYSRAM_SIZE only redefine STM32MP_SYSRAM_SIZE.
Directly use the latter one and remove the STM32MP_SEC_SYSRAM_SIZE.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I9cca19fda7294be3f31ec74293ce122037541d12

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Merge changes I26cefbb5,I6a8b3528,I323fb741 into integration

* changes:
fix(stm32mp2): set PLAT_MAX_PWR_LVL to one
feat(stm32mp2): boot BL33 at EL1 or EL2
feat(stm32mp2): disable unsupported f

Merge changes I26cefbb5,I6a8b3528,I323fb741 into integration

* changes:
fix(stm32mp2): set PLAT_MAX_PWR_LVL to one
feat(stm32mp2): boot BL33 at EL1 or EL2
feat(stm32mp2): disable unsupported features

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fix(stm32mp2): set PLAT_MAX_PWR_LVL to one

Set maximum power level to 1 as power management isn't implemented yet.

Change-Id: I26cefbb5e199944d371bf06a76b2c41f73d38585
Signed-off-by: Maxime Méré <m

fix(stm32mp2): set PLAT_MAX_PWR_LVL to one

Set maximum power level to 1 as power management isn't implemented yet.

Change-Id: I26cefbb5e199944d371bf06a76b2c41f73d38585
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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Merge "feat(stm32mp2): improve BL31 size management" into integration

feat(stm32mp2): improve BL31 size management

Change the size of BL31 limit allocation to be half the sysram size.
Defining BL31_PROGBITS_LIMIT to detect overflows.

Signed-off-by: Maxime Méré <maxim

feat(stm32mp2): improve BL31 size management

Change the size of BL31 limit allocation to be half the sysram size.
Defining BL31_PROGBITS_LIMIT to detect overflows.

Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iccc1cc0826b8113a3c2fd6ffa77ca419795854d3

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Merge changes I09ab0a5c,I87d0a492,I613a52ae,I2fcd8d32,Ie91527a7, ... into integration

* changes:
feat(stm32mp2): manage DDR FW via FIP
feat(stm32mp2): introduce DDR type compilation flags
feat

Merge changes I09ab0a5c,I87d0a492,I613a52ae,I2fcd8d32,Ie91527a7, ... into integration

* changes:
feat(stm32mp2): manage DDR FW via FIP
feat(stm32mp2): introduce DDR type compilation flags
feat(stm32mp2): add RISAB registers description
feat(stm32mp2-fdts): add BL31 info in fw-config
feat(stm32mp2): add minimal support for BL31
feat(st): manage BL31 FCONF load_info struct

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feat(stm32mp2): add minimal support for BL31

Add the required files to compile BL31 on STM32MP2.
Update BL2 configuration to load BL31. The platform boots until BL31,
but stops here as no other bina

feat(stm32mp2): add minimal support for BL31

Add the required files to compile BL31 on STM32MP2.
Update BL2 configuration to load BL31. The platform boots until BL31,
but stops here as no other binaries are loaded as DDR is not
initialized.
At runtime, BL31 will use only the first half of the SYSRAM, the upper
half will be used for non-secure DMA LLIs. To be sure nothing from this
area is still in the cache, invalidate the upper SYSRAM before enabling
BL31 cache. BL31 should then map only first half of the SYSRAM. But it
must temporarily map the upper half read-only, as this is where we will
retrieve BL2 parameters, used to fill registers for next boot stages.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Ie91527a7a26625624b4b3c65fb6a0ca9dd355dbd

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Merge "fix(stm32mp2): remove mapping of BL2 DT area" into integration

fix(stm32mp2): remove mapping of BL2 DT area

To prevent from coding issues that could overwrite DT area, we were
mapping this area as read-only on STM32MP1. But on STM32MP2, we need
this area to put

fix(stm32mp2): remove mapping of BL2 DT area

To prevent from coding issues that could overwrite DT area, we were
mapping this area as read-only on STM32MP1. But on STM32MP2, we need
this area to put BL31 binary. We were then using dynamic mapping. But
the area is included in the whole SYSRAM memory mapping. This is not
allowed with dynamic mapping. As no other code is running at this step,
and we know what code is running in BL2, just remove this extra
read-only protection for STM32MP2. A message is added after the post
load process of FW-CONFIG file, as BL2 DT area will be overwritten
after that.
And remove the now useless macros DTB_BASE & DTB_LIMIT.
This corrects Coverity issue: CID 443168.

Change-Id: Ic01d6a443ecf7721380ef39dc570e2d1627008d0
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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Merge changes from topic "stm32mp2_bl2_updates" into integration

* changes:
feat(stm32mp2): load fw-config file
feat(stm32mp2): add fw-config compilation
feat(stm32mp2-fdts): add fw-config fil

Merge changes from topic "stm32mp2_bl2_updates" into integration

* changes:
feat(stm32mp2): load fw-config file
feat(stm32mp2): add fw-config compilation
feat(stm32mp2-fdts): add fw-config files for STM32MP257F-EV1
feat(stm32mp2-fdts): add fw-config file
feat(stm32mp2-fdts): add clock tree for STM32MP257F-EV1
feat(stm32mp2): enable DDR sub-system clock
feat(stm32mp2): add fixed regulators support
feat(stm32mp2): print board info
feat(stm32mp2): display CPU info
feat(stm32mp2): get chip ID
feat(stm32mp2): add BL2 boot first steps
feat(stm32mp2): add defines for the PWR peripheral
feat(stm32mp2-fdts): add SD-card and eMMC support on STM32MP257F-EV1
feat(stm32mp2-fdts): add sdmmc pins definition
feat(stm32mp2-fdts): add sdmmc nodes in SoC DT file
feat(stm32mp2-fdts): add io_policies
feat(stm32mp2-fdts): remove pins-are-numbered

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feat(stm32mp2): add BL2 boot first steps

Configure the first steps for STM32MP2 BL2 platform boot:
- Save boot context address for later use
- Configure BL2 MMU
- Load and use BL2 DT
- Reset backup

feat(stm32mp2): add BL2 boot first steps

Configure the first steps for STM32MP2 BL2 platform boot:
- Save boot context address for later use
- Configure BL2 MMU
- Load and use BL2 DT
- Reset backup domain
- Initialize clocks
- Configure UART for console
- Print some info about board and reset reason
- Setup storage (only SD-card for the moment)

The platform boot stops at BL2 image load, as bl2_mem_params_descs[]
is still empty.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: If6127cfbf77825a03afe8d65ba47c8c0661de496

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Merge changes from topic "stm32mp2" into integration

* changes:
feat(stm32mp2): generate stm32 file
feat(stm32mp2-fdts): add stm32mp257f-ev1 board
feat(stm32mp2-fdts): introduce stm32mp25 pinc

Merge changes from topic "stm32mp2" into integration

* changes:
feat(stm32mp2): generate stm32 file
feat(stm32mp2-fdts): add stm32mp257f-ev1 board
feat(stm32mp2-fdts): introduce stm32mp25 pinctrl files
feat(stm32mp2-fdts): introduce stm32mp25 SoCs family
feat(stm32mp2): add console configuration
feat(st): add RCC registers list
feat(st-uart): add AARCH64 stm32_console driver
feat(st): introduce new platform STM32MP2
feat(dt-bindings): add the STM32MP2 clock and reset bindings
docs(changelog): add scopes for STM32MP2
feat(docs): introduce STM32MP2 doc
refactor(docs): add a sub-menu for ST platforms
refactor(st): move plat_image_load.c
refactor(st): rename PLAT_NB_FIXED_REGS
refactor(st): move some storage definitions to common part
refactor(st): move SDMMC definitions to driver
feat(st-clock): stub fdt_get_rcc_secure_state
feat(st-clock): allow aarch64 compilation of STGEN functions
feat(st): allow AARCH64 compilation for common code
refactor(st): rename QSPI macros

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feat(st): introduce new platform STM32MP2

This new STMicroelectronics SoC is based on a dual Cortex-A35.
For the moment, only BL2 is compiled with the common parts for ST
platforms.

Change-Id: I1bc

feat(st): introduce new platform STM32MP2

This new STMicroelectronics SoC is based on a dual Cortex-A35.
For the moment, only BL2 is compiled with the common parts for ST
platforms.

Change-Id: I1bc4e6835dba4230359ea9b26d736791e27258aa
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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