| 0ea8881e | 24-Jan-2017 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: add support for multiple SMMU devices
This patch adds support for all three SMMU devices present on the SoC.
The following changes have been done:
Add SMMU devices to the memory map
Tegra194: add support for multiple SMMU devices
This patch adds support for all three SMMU devices present on the SoC.
The following changes have been done:
Add SMMU devices to the memory map
Update register read and write functions
Change-Id: I0007b496d2ae7264f4fa9f605d4b0a15fa747a0f
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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| 2ac8cb7e | 02-Jan-2017 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: add SMMU and mc_sid support
Define mc sid and txn override regs and sec cfgs.
Create array for mc sid override regs and sec config that is
used to initialize mc.
Add smmu ctx regs array to
Tegra194: add SMMU and mc_sid support
Define mc sid and txn override regs and sec cfgs.
Create array for mc sid override regs and sec config that is
used to initialize mc.
Add smmu ctx regs array to hold register values during suspend.
Change-Id: I7b265710a9ec2be7dea050058bce65c614772c78
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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| d11c793b | 23-Dec-2016 |
Steven Kao <skao@nvidia.com> |
Tegra194: psci: support for 64-bit TZDRAM base
This patch fixes the variable width to store the TZDRAM base
address used to resume from System Suspend.
Change-Id: I3c18eb844963f39f91b5ac45e3709f335
Tegra194: psci: support for 64-bit TZDRAM base
This patch fixes the variable width to store the TZDRAM base
address used to resume from System Suspend.
Change-Id: I3c18eb844963f39f91b5ac45e3709f3354bcda0c
Signed-off-by: Steven Kao <skao@nvidia.com>
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| 41612559 | 10-Apr-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: base commit for the platform
This patch creates the base commit for the Tegra194 platform, from
Tegra186 code base.
Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede
Signed-off-by: Var
Tegra194: base commit for the platform
This patch creates the base commit for the Tegra194 platform, from
Tegra186 code base.
Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| cf489bf1 | 25-May-2017 |
Vignesh Radhakrishnan <vigneshr@nvidia.com> |
Revert "Tegra: Add support for fake system suspend"
This reverts commit c41df8fda84b9bc56bbb2347fb902f64b1bb557e
Fake system suspend relies on software running on EL3
to trigger a warm reset.
Reve
Revert "Tegra: Add support for fake system suspend"
This reverts commit c41df8fda84b9bc56bbb2347fb902f64b1bb557e
Fake system suspend relies on software running on EL3
to trigger a warm reset.
Revert enabling fake system suspend, as the software
running on El3 is not allowed to trigger a warm reset.
Change-Id: I6035f2a7bcb0a4ad50a62c5bc5239226c625ee5e
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
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| b30646a8 | 18-Oct-2019 |
Manish Pandey <manish.pandey2@arm.com> |
plat/arm: use Aff3 bits also to validate mpidr
There are some platforms which uses MPIDR Affinity level 3 for storing
extra affinity information e.g. N1SDP uses it for keeping chip id in a
multichip
plat/arm: use Aff3 bits also to validate mpidr
There are some platforms which uses MPIDR Affinity level 3 for storing
extra affinity information e.g. N1SDP uses it for keeping chip id in a
multichip setup, for such platforms MPIDR validation should not fail.
This patch adds Aff3 bits also as part of mpidr validation mask, for
platforms which does not uses Aff3 will not have any impact as these
bits will be all zeros.
Change-Id: Ia8273972fa7948fdb11708308d0239d2dc4dfa85
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
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| 0711ee5c | 24-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
delay: timeout detection support
Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT.
timeout_init_us(some_timeout_us); returns a reference to detect
timeout for the provided mic
delay: timeout detection support
Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT.
timeout_init_us(some_timeout_us); returns a reference to detect
timeout for the provided microsecond delay value from current time.
timeout_elapsed(reference) return true/false whether the reference
timeout is elapsed.
Cherry picked from OP-TEE implementation [1].
[1] commit 33d30a74502b ("core: timeout detection support")
Minor:
- Remove stm32mp platform duplicated implementation.
- Add new include in marvell ble.mk
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Iaef6d43c11a2e6992fb48efdc674a0552755ad9c
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| 78f02ae2 | 22-Jul-2019 |
Imre Kis <imre.kis@arm.com> |
Introducing support for Cortex-A65AE
Change-Id: I1ea2bf088f1e001cdbd377cbfb7c6a2866af0422
Signed-off-by: Imre Kis <imre.kis@arm.com> |
| efcf951f | 03-Oct-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "qemu_sbsa" into integration
* changes:
qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1
qemu/qemu_sbsa: Adding Qemu SBSA platform |
| 82d8d4ab | 03-Oct-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes I0355e084,I6a6dd1c0 into integration
* changes:
mediatek: mt8183: add EMI MPU driver for DRAM protection
mediatek: mt8183: add DEVAPC driver to control protection |
| 251b2643 | 03-Oct-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "a5ds: Add handler for when user tries to switch off secondary cores" into integration |
| 59ffec15 | 26-Sep-2019 |
Usama Arif <usama.arif@arm.com> |
a5ds: Add handler for when user tries to switch off secondary cores
a5ds only has always-on power domain and there is no power control
present. However, without the pwr_domain_off handler, the kerne
a5ds: Add handler for when user tries to switch off secondary cores
a5ds only has always-on power domain and there is no power control
present. However, without the pwr_domain_off handler, the kernel
panics when the user will try to switch off secondary cores. The
a5ds_pwr_domain_off handler will prevent kernel from crashing,
i.e. the kernel will attempt but fail to shut down the secondary CPUs
if the user tries to switch them offline.
Change-Id: I3c2239a1b6f035113ddbdda063c8495000cbe30c
Signed-off-by: Usama Arif <usama.arif@arm.com>
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| f25ea7e3 | 23-Aug-2019 |
kenny liang <kenny.liang@mediatek.com> |
mediatek: mt8183: add EMI MPU driver for DRAM protection
Add EMI MPU driver for DRAM protection.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I0355e084184b5396ad8ac99fff6ef9d050
mediatek: mt8183: add EMI MPU driver for DRAM protection
Add EMI MPU driver for DRAM protection.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I0355e084184b5396ad8ac99fff6ef9d050fb5e96
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| 1b0174ef | 23-Aug-2019 |
kenny liang <kenny.liang@mediatek.com> |
mediatek: mt8183: add DEVAPC driver to control protection
Add DEVAPC driver to control protection.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I6a6dd1c0bffa372b6df2cb604ca5e02e
mediatek: mt8183: add DEVAPC driver to control protection
Add DEVAPC driver to control protection.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I6a6dd1c0bffa372b6df2cb604ca5e02eabbb9d26
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| 6ad216dc | 18-Jul-2019 |
Imre Kis <imre.kis@arm.com> |
Introducing support for Cortex-A65
Change-Id: I645442d52a295706948e2cac88c36c1a3cb0bc47
Signed-off-by: Imre Kis <imre.kis@arm.com> |
| fa405e3b | 07-Jun-2018 |
Radoslaw Biernacki <radoslaw.biernacki@linaro.org> |
qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1
This patch adds mapping for secure FLASH0 for qemu/virt and
qemu/qemu_sbsa platforms. This change is targeted for sbsa but since both
pla
qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1
This patch adds mapping for secure FLASH0 for qemu/virt and
qemu/qemu_sbsa platforms. This change is targeted for sbsa but since both
platforms share common code, changes in common defines was necessary.
For qemu_sbsa, this patch adds necessary mapping in order to boot without
semi-hosting from secure FLASH0. EFI need to stay in FLASH1 (share it with
variables) since it need to "run in place" in non secure domain. Changes
for this are under RFC at edk2-platforms mailing list:
https://patches.linaro.org/patch/171327/
(edk2-platforms/Platform/Qemu/SbsaQemu/SbsaQemu.dsc).
In docs qemu/virt is described as using semi-hosting, therefore this change
should be orthogonal to existing assumptions while giving possibility to
store both bl1 and fip in FLASH0 at some point (additional changes required
for that).
Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: I782bc3637c91c01eaee680b3c5c408e24b4b6e28
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| 558a6f44 | 17-May-2018 |
Radoslaw Biernacki <radoslaw.biernacki@linaro.org> |
qemu/qemu_sbsa: Adding Qemu SBSA platform
This patch introduces Qemu SBSA platform.
Both platform specific files where copied from qemu/qemu with changes for
DRAM base above 32bit and removal of ARM
qemu/qemu_sbsa: Adding Qemu SBSA platform
This patch introduces Qemu SBSA platform.
Both platform specific files where copied from qemu/qemu with changes for
DRAM base above 32bit and removal of ARMv7 conditional defines/code.
Documentation is aligned to rest of SBSA patches along the series and
planed changes in edk2-platform repo.
Fixes ARM-software/tf-issues#602
Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: I8ebc34eedb2268365e479ef05654b2df1b99128c
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| a4668c36 | 16-Sep-2019 |
Artsem Artsemenka <artsem.artsemenka@arm.com> |
Cortex_hercules: Add support for Hercules-AE
Not tested on FVP Model.
Change-Id: Iedebc5c1fbc7ea577e94142b7feafa5546f1f4f9
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> |
| ace23683 | 27-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "ld/stm32-authentication" into integration
* changes:
stm32mp1: add authentication support for stm32image
bsec: move bsec_mode_is_closed_device() service to platform
c
Merge changes from topic "ld/stm32-authentication" into integration
* changes:
stm32mp1: add authentication support for stm32image
bsec: move bsec_mode_is_closed_device() service to platform
crypto: stm32_hash: Add HASH driver
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| f7fa5289 | 27-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "amlogic-g12a" into integration
* changes:
amlogic: g12a: Add support for the S905X2 (G12A) platform
amlogic: makefile: Use PLAT variable when possible
amlogic: sha_dm
Merge changes from topic "amlogic-g12a" into integration
* changes:
amlogic: g12a: Add support for the S905X2 (G12A) platform
amlogic: makefile: Use PLAT variable when possible
amlogic: sha_dma: Move register mappings to platform header
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|
| 757d904b | 27-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "a5ds-multicore" into integration
* changes:
a5ds: add multicore support
a5ds: Hold the secondary cpus in pen rather than panic |
| 17b0bb6c | 27-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "raspberry-pi-4-support" into integration
* changes:
rpi4: Add initial documentation file
rpi4: Add stdout-path to device tree
rpi4: Add GIC maintenance interrupt to G
Merge changes from topic "raspberry-pi-4-support" into integration
* changes:
rpi4: Add initial documentation file
rpi4: Add stdout-path to device tree
rpi4: Add GIC maintenance interrupt to GIC DT node
rpi4: Cleanup memory regions, move pens to first page
rpi4: Reserve resident BL31 region from non-secure world
rpi4: Amend DTB to advertise PSCI
rpi4: Determine BL33 entry point at runtime
rpi4: Accommodate "armstub8.bin" header at the beginning of BL31 image
Add basic support for Raspberry Pi 4
rpi3: Allow runtime determination of UART base clock rate
FDT helper functions: Respect architecture in PSCI function IDs
FDT helper functions: Add function documentation
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| 41bda863 | 27-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "mp/giv3-discovery" into integration
* changes:
Migrate ARM platforms to use the new GICv3 API
Adding new optional PSCI hook pwr_domain_on_finish_late
GICv3: Enable mu
Merge changes from topic "mp/giv3-discovery" into integration
* changes:
Migrate ARM platforms to use the new GICv3 API
Adding new optional PSCI hook pwr_domain_on_finish_late
GICv3: Enable multi socket GIC redistributor frame discovery
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| 69ef7b7f | 26-Sep-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge changes I0283fc2e,Ib476d024,Iada05f7c into integration
* changes:
hikey: fix to load FIP by partition table.
hikey960: fix to load FIP by partition table
drivers: partition: support diff
Merge changes I0283fc2e,Ib476d024,Iada05f7c into integration
* changes:
hikey: fix to load FIP by partition table.
hikey960: fix to load FIP by partition table
drivers: partition: support different block size
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| cdb8c52f | 18-Sep-2019 |
Carlo Caione <ccaione@baylibre.com> |
amlogic: g12a: Add support for the S905X2 (G12A) platform
Introduce the preliminary support for the Amlogic S905X2 (G12A) SoC.
This port is a minimal implementation of BL31 capable of booting
mainl
amlogic: g12a: Add support for the S905X2 (G12A) platform
Introduce the preliminary support for the Amlogic S905X2 (G12A) SoC.
This port is a minimal implementation of BL31 capable of booting
mainline U-Boot and Linux. Tested on a SEI510 board.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ife958f10e815a4530292c45446adb71239f3367f
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