1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl31/bl31.h> 10 #include <common/bl_common.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/console.h> 13 #include <context.h> 14 #include <lib/el3_runtime/context_mgmt.h> 15 #include <cortex_a57.h> 16 #include <common/debug.h> 17 #include <denver.h> 18 #include <drivers/arm/gic_common.h> 19 #include <drivers/arm/gicv2.h> 20 #include <bl31/interrupt_mgmt.h> 21 #include <mce.h> 22 #include <plat/common/platform.h> 23 #include <tegra_def.h> 24 #include <tegra_platform.h> 25 #include <tegra_private.h> 26 #include <lib/xlat_tables/xlat_tables_v2.h> 27 28 /******************************************************************************* 29 * The Tegra power domain tree has a single system level power domain i.e. a 30 * single root node. The first entry in the power domain descriptor specifies 31 * the number of power domains at the highest power level. 32 ******************************************************************************* 33 */ 34 const unsigned char tegra_power_domain_tree_desc[] = { 35 /* No of root nodes */ 36 1, 37 /* No of clusters */ 38 PLATFORM_CLUSTER_COUNT, 39 /* No of CPU cores - cluster0 */ 40 PLATFORM_MAX_CPUS_PER_CLUSTER, 41 /* No of CPU cores - cluster1 */ 42 PLATFORM_MAX_CPUS_PER_CLUSTER, 43 /* No of CPU cores - cluster2 */ 44 PLATFORM_MAX_CPUS_PER_CLUSTER, 45 /* No of CPU cores - cluster3 */ 46 PLATFORM_MAX_CPUS_PER_CLUSTER 47 }; 48 49 /******************************************************************************* 50 * This function returns the Tegra default topology tree information. 51 ******************************************************************************/ 52 const unsigned char *plat_get_power_domain_tree_desc(void) 53 { 54 return tegra_power_domain_tree_desc; 55 } 56 57 /* 58 * Table of regions to map using the MMU. 59 */ 60 static const mmap_region_t tegra_mmap[] = { 61 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 62 MT_DEVICE | MT_RW | MT_SECURE), 63 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 64 MT_DEVICE | MT_RW | MT_SECURE), 65 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 66 MT_DEVICE | MT_RW | MT_SECURE), 67 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 68 MT_DEVICE | MT_RW | MT_SECURE), 69 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ 70 MT_DEVICE | MT_RW | MT_SECURE), 71 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ 72 MT_DEVICE | MT_RW | MT_SECURE), 73 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ 74 MT_DEVICE | MT_RW | MT_SECURE), 75 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 76 MT_DEVICE | MT_RW | MT_SECURE), 77 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 78 MT_DEVICE | MT_RW | MT_SECURE), 79 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 80 MT_DEVICE | MT_RW | MT_SECURE), 81 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 82 MT_DEVICE | MT_RW | MT_SECURE), 83 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 84 MT_DEVICE | MT_RW | MT_SECURE), 85 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 86 MT_DEVICE | MT_RW | MT_SECURE), 87 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 88 MT_DEVICE | MT_RW | MT_SECURE), 89 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 90 MT_DEVICE | MT_RW | MT_SECURE), 91 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 92 MT_DEVICE | MT_RW | MT_SECURE), 93 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */ 94 MT_DEVICE | MT_RW | MT_SECURE), 95 MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000, /* 64KB */ 96 MT_DEVICE | MT_RW | MT_SECURE), 97 MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000, /* 64KB */ 98 MT_DEVICE | MT_RW | MT_SECURE), 99 MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000, /* 64KB */ 100 MT_DEVICE | MT_RW | MT_SECURE), 101 {0} 102 }; 103 104 /******************************************************************************* 105 * Set up the pagetables as per the platform memory map & initialize the MMU 106 ******************************************************************************/ 107 const mmap_region_t *plat_get_mmio_map(void) 108 { 109 /* MMIO space */ 110 return tegra_mmap; 111 } 112 113 /******************************************************************************* 114 * Handler to get the System Counter Frequency 115 ******************************************************************************/ 116 unsigned int plat_get_syscnt_freq2(void) 117 { 118 return 31250000; 119 } 120 121 /******************************************************************************* 122 * Maximum supported UART controllers 123 ******************************************************************************/ 124 #define TEGRA186_MAX_UART_PORTS 7 125 126 /******************************************************************************* 127 * This variable holds the UART port base addresses 128 ******************************************************************************/ 129 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 130 0, /* undefined - treated as an error case */ 131 TEGRA_UARTA_BASE, 132 TEGRA_UARTB_BASE, 133 TEGRA_UARTC_BASE, 134 TEGRA_UARTD_BASE, 135 TEGRA_UARTE_BASE, 136 TEGRA_UARTF_BASE, 137 TEGRA_UARTG_BASE, 138 }; 139 140 /******************************************************************************* 141 * Retrieve the UART controller base to be used as the console 142 ******************************************************************************/ 143 uint32_t plat_get_console_from_id(int id) 144 { 145 if (id > TEGRA186_MAX_UART_PORTS) 146 return 0; 147 148 return tegra186_uart_addresses[id]; 149 } 150 151 /******************************************************************************* 152 * Handler for early platform setup 153 ******************************************************************************/ 154 void plat_early_platform_setup(void) 155 { 156 157 /* sanity check MCE firmware compatibility */ 158 mce_verify_firmware_version(); 159 160 /* Program XUSB STREAMIDs 161 * Xavier XUSB has support for XUSB virtualization. It will have one 162 * physical function (PF) and four Virtual function (VF) 163 * 164 * There were below two SIDs for XUSB until T186. 165 * 1) #define TEGRA_SID_XUSB_HOST 0x1bU 166 * 2) #define TEGRA_SID_XUSB_DEV 0x1cU 167 * 168 * We have below four new SIDs added for VF(s) 169 * 3) #define TEGRA_SID_XUSB_VF0 0x5dU 170 * 4) #define TEGRA_SID_XUSB_VF1 0x5eU 171 * 5) #define TEGRA_SID_XUSB_VF2 0x5fU 172 * 6) #define TEGRA_SID_XUSB_VF3 0x60U 173 * 174 * When virtualization is enabled then we have to disable SID override 175 * and program above SIDs in below newly added SID registers in XUSB 176 * PADCTL MMIO space. These registers are TZ protected and so need to 177 * be done in ATF. 178 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) 179 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) 180 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) 181 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) 182 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) 183 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) 184 * 185 * This change disables SID override and programs XUSB SIDs in 186 * above registers to support both virtualization and non-virtualization 187 * 188 * Known Limitations: 189 * If xusb interface disables SMMU in XUSB DT in non-virtualization 190 * setup then there will be SMMU fault. We need to use WAR at 191 * https://git-master.nvidia.com/r/1529227/ to the issue. 192 * 193 * More details can be found in the bug 1971161 194 */ 195 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 196 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); 197 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 198 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); 199 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 200 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); 201 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 202 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); 203 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 204 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); 205 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 206 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); 207 } 208 209 /* Secure IRQs for Tegra186 */ 210 static const irq_sec_cfg_t tegra186_sec_irqs[] = { 211 [0] = { 212 TEGRA186_BPMP_WDT_IRQ, 213 TEGRA186_SEC_IRQ_TARGET_MASK, 214 INTR_TYPE_EL3, 215 }, 216 [1] = { 217 TEGRA186_BPMP_WDT_IRQ, 218 TEGRA186_SEC_IRQ_TARGET_MASK, 219 INTR_TYPE_EL3, 220 }, 221 [2] = { 222 TEGRA186_SPE_WDT_IRQ, 223 TEGRA186_SEC_IRQ_TARGET_MASK, 224 INTR_TYPE_EL3, 225 }, 226 [3] = { 227 TEGRA186_SCE_WDT_IRQ, 228 TEGRA186_SEC_IRQ_TARGET_MASK, 229 INTR_TYPE_EL3, 230 }, 231 [4] = { 232 TEGRA186_TOP_WDT_IRQ, 233 TEGRA186_SEC_IRQ_TARGET_MASK, 234 INTR_TYPE_EL3, 235 }, 236 [5] = { 237 TEGRA186_AON_WDT_IRQ, 238 TEGRA186_SEC_IRQ_TARGET_MASK, 239 INTR_TYPE_EL3, 240 }, 241 }; 242 243 /******************************************************************************* 244 * Initialize the GIC and SGIs 245 ******************************************************************************/ 246 void plat_gic_setup(void) 247 { 248 tegra_gic_setup(tegra186_sec_irqs, 249 sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 250 251 /* 252 * Initialize the FIQ handler only if the platform supports any 253 * FIQ interrupt sources. 254 */ 255 if (sizeof(tegra186_sec_irqs) > 0) 256 tegra_fiq_handler_setup(); 257 } 258 259 /******************************************************************************* 260 * Return pointer to the BL31 params from previous bootloader 261 ******************************************************************************/ 262 struct tegra_bl31_params *plat_get_bl31_params(void) 263 { 264 uint32_t val; 265 266 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 267 268 return (struct tegra_bl31_params *)(uintptr_t)val; 269 } 270 271 /******************************************************************************* 272 * Return pointer to the BL31 platform params from previous bootloader 273 ******************************************************************************/ 274 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 275 { 276 uint32_t val; 277 278 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 279 280 return (plat_params_from_bl2_t *)(uintptr_t)val; 281 } 282