1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl31/bl31.h> 10 #include <common/bl_common.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/console.h> 13 #include <context.h> 14 #include <lib/el3_runtime/context_mgmt.h> 15 #include <cortex_a57.h> 16 #include <common/debug.h> 17 #include <denver.h> 18 #include <drivers/arm/gic_common.h> 19 #include <drivers/arm/gicv2.h> 20 #include <bl31/interrupt_mgmt.h> 21 #include <mce.h> 22 #include <plat/common/platform.h> 23 #include <tegra_def.h> 24 #include <tegra_mc_def.h> 25 #include <tegra_platform.h> 26 #include <tegra_private.h> 27 #include <lib/xlat_tables/xlat_tables_v2.h> 28 29 /******************************************************************************* 30 * The Tegra power domain tree has a single system level power domain i.e. a 31 * single root node. The first entry in the power domain descriptor specifies 32 * the number of power domains at the highest power level. 33 ******************************************************************************* 34 */ 35 static const uint8_t tegra_power_domain_tree_desc[] = { 36 /* No of root nodes */ 37 1, 38 /* No of clusters */ 39 PLATFORM_CLUSTER_COUNT, 40 /* No of CPU cores - cluster0 */ 41 PLATFORM_MAX_CPUS_PER_CLUSTER, 42 /* No of CPU cores - cluster1 */ 43 PLATFORM_MAX_CPUS_PER_CLUSTER, 44 /* No of CPU cores - cluster2 */ 45 PLATFORM_MAX_CPUS_PER_CLUSTER, 46 /* No of CPU cores - cluster3 */ 47 PLATFORM_MAX_CPUS_PER_CLUSTER 48 }; 49 50 /******************************************************************************* 51 * This function returns the Tegra default topology tree information. 52 ******************************************************************************/ 53 const uint8_t *plat_get_power_domain_tree_desc(void) 54 { 55 return tegra_power_domain_tree_desc; 56 } 57 58 /* 59 * Table of regions to map using the MMU. 60 */ 61 static const mmap_region_t tegra_mmap[] = { 62 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */ 63 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 64 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */ 65 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 66 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */ 67 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 68 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */ 69 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 70 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/ 71 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 72 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */ 73 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 74 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */ 75 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 76 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */ 77 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 78 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */ 79 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 80 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */ 81 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 82 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */ 83 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 84 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */ 85 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 86 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ 87 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 88 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */ 89 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 90 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */ 91 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 92 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */ 93 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 94 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */ 95 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 96 MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000U, /* 64KB */ 97 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 98 MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000U, /* 64KB */ 99 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 100 MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000U, /* 64KB */ 101 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 102 {0} 103 }; 104 105 /******************************************************************************* 106 * Set up the pagetables as per the platform memory map & initialize the MMU 107 ******************************************************************************/ 108 const mmap_region_t *plat_get_mmio_map(void) 109 { 110 /* MMIO space */ 111 return tegra_mmap; 112 } 113 114 /******************************************************************************* 115 * Handler to get the System Counter Frequency 116 ******************************************************************************/ 117 uint32_t plat_get_syscnt_freq2(void) 118 { 119 return 31250000; 120 } 121 122 /******************************************************************************* 123 * Maximum supported UART controllers 124 ******************************************************************************/ 125 #define TEGRA186_MAX_UART_PORTS 7 126 127 /******************************************************************************* 128 * This variable holds the UART port base addresses 129 ******************************************************************************/ 130 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 131 0, /* undefined - treated as an error case */ 132 TEGRA_UARTA_BASE, 133 TEGRA_UARTB_BASE, 134 TEGRA_UARTC_BASE, 135 TEGRA_UARTD_BASE, 136 TEGRA_UARTE_BASE, 137 TEGRA_UARTF_BASE, 138 TEGRA_UARTG_BASE 139 }; 140 141 /******************************************************************************* 142 * Retrieve the UART controller base to be used as the console 143 ******************************************************************************/ 144 uint32_t plat_get_console_from_id(int32_t id) 145 { 146 uint32_t ret; 147 148 if (id > TEGRA186_MAX_UART_PORTS) { 149 ret = 0; 150 } else { 151 ret = tegra186_uart_addresses[id]; 152 } 153 154 return ret; 155 } 156 157 /******************************************************************************* 158 * Handler for early platform setup 159 ******************************************************************************/ 160 void plat_early_platform_setup(void) 161 { 162 163 /* sanity check MCE firmware compatibility */ 164 mce_verify_firmware_version(); 165 166 /* Program XUSB STREAMIDs 167 * Xavier XUSB has support for XUSB virtualization. It will have one 168 * physical function (PF) and four Virtual function (VF) 169 * 170 * There were below two SIDs for XUSB until T186. 171 * 1) #define TEGRA_SID_XUSB_HOST 0x1bU 172 * 2) #define TEGRA_SID_XUSB_DEV 0x1cU 173 * 174 * We have below four new SIDs added for VF(s) 175 * 3) #define TEGRA_SID_XUSB_VF0 0x5dU 176 * 4) #define TEGRA_SID_XUSB_VF1 0x5eU 177 * 5) #define TEGRA_SID_XUSB_VF2 0x5fU 178 * 6) #define TEGRA_SID_XUSB_VF3 0x60U 179 * 180 * When virtualization is enabled then we have to disable SID override 181 * and program above SIDs in below newly added SID registers in XUSB 182 * PADCTL MMIO space. These registers are TZ protected and so need to 183 * be done in ATF. 184 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) 185 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) 186 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) 187 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) 188 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) 189 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) 190 * 191 * This change disables SID override and programs XUSB SIDs in 192 * above registers to support both virtualization and non-virtualization 193 * 194 * Known Limitations: 195 * If xusb interface disables SMMU in XUSB DT in non-virtualization 196 * setup then there will be SMMU fault. We need to use WAR at 197 * https:\\git-master.nvidia.com/r/1529227/ to the issue. 198 * 199 * More details can be found in the bug 1971161 200 */ 201 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 202 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); 203 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 204 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); 205 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 206 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); 207 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 208 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); 209 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 210 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); 211 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 212 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); 213 } 214 215 /* Secure IRQs for Tegra186 */ 216 static const irq_sec_cfg_t tegra186_sec_irqs[] = { 217 [0] = { 218 TEGRA186_BPMP_WDT_IRQ, 219 TEGRA186_SEC_IRQ_TARGET_MASK, 220 INTR_TYPE_EL3, 221 }, 222 [1] = { 223 TEGRA186_BPMP_WDT_IRQ, 224 TEGRA186_SEC_IRQ_TARGET_MASK, 225 INTR_TYPE_EL3, 226 }, 227 [2] = { 228 TEGRA186_SPE_WDT_IRQ, 229 TEGRA186_SEC_IRQ_TARGET_MASK, 230 INTR_TYPE_EL3, 231 }, 232 [3] = { 233 TEGRA186_SCE_WDT_IRQ, 234 TEGRA186_SEC_IRQ_TARGET_MASK, 235 INTR_TYPE_EL3, 236 }, 237 [4] = { 238 TEGRA186_TOP_WDT_IRQ, 239 TEGRA186_SEC_IRQ_TARGET_MASK, 240 INTR_TYPE_EL3, 241 }, 242 [5] = { 243 TEGRA186_AON_WDT_IRQ, 244 TEGRA186_SEC_IRQ_TARGET_MASK, 245 INTR_TYPE_EL3, 246 }, 247 }; 248 249 /******************************************************************************* 250 * Initialize the GIC and SGIs 251 ******************************************************************************/ 252 void plat_gic_setup(void) 253 { 254 tegra_gic_setup(tegra186_sec_irqs, (uint32_t)ARRAY_SIZE(tegra186_sec_irqs); 255 256 /* 257 * Initialize the FIQ handler only if the platform supports any 258 * FIQ interrupt sources. 259 */ 260 if (sizeof(tegra186_sec_irqs) > 0U) { 261 tegra_fiq_handler_setup(); 262 } 263 } 264 265 /******************************************************************************* 266 * Return pointer to the BL31 params from previous bootloader 267 ******************************************************************************/ 268 struct tegra_bl31_params *plat_get_bl31_params(void) 269 { 270 uint32_t val; 271 272 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR); 273 274 return (struct tegra_bl31_params *)(uintptr_t)val; 275 } 276 277 /******************************************************************************* 278 * Return pointer to the BL31 platform params from previous bootloader 279 ******************************************************************************/ 280 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 281 { 282 uint32_t val; 283 284 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR); 285 286 return (plat_params_from_bl2_t *)(uintptr_t)val; 287 } 288