1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <common/debug.h> 9 #include <lib/mmio.h> 10 #include <mce.h> 11 #include <string.h> 12 #include <tegra_def.h> 13 #include <tegra_private.h> 14 15 #define MISCREG_CPU_RESET_VECTOR 0x2000U 16 #define MISCREG_AA64_RST_LOW 0x2004U 17 #define MISCREG_AA64_RST_HIGH 0x2008U 18 19 #define CPU_RESET_MODE_AA64 1U 20 21 extern void tegra194_cpu_reset_handler(void); 22 extern uint64_t __tegra194_smmu_ctx_start; 23 24 /******************************************************************************* 25 * Setup secondary CPU vectors 26 ******************************************************************************/ 27 void plat_secondary_setup(void) 28 { 29 uint32_t addr_low, addr_high; 30 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 31 uint64_t cpu_reset_handler_base = params_from_bl2->tzdram_base; 32 33 INFO("Setting up secondary CPU boot\n"); 34 35 memcpy((void *)((uintptr_t)cpu_reset_handler_base), 36 (void *)(uintptr_t)tegra194_cpu_reset_handler, 37 (uintptr_t)&__tegra194_smmu_ctx_start - 38 (uintptr_t)&tegra194_cpu_reset_handler); 39 40 addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64; 41 addr_high = (uint32_t)((cpu_reset_handler_base >> 32U) & 0x7ffU); 42 43 /* write lower 32 bits first, then the upper 11 bits */ 44 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); 45 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); 46 47 /* save reset vector to be used during SYSTEM_SUSPEND exit */ 48 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO, 49 addr_low); 50 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI, 51 addr_high); 52 } 53