1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __TEGRA_DEF_H__ 8 #define __TEGRA_DEF_H__ 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * These values are used by the PSCI implementation during the `CPU_SUSPEND` 14 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 15 * parameter. 16 ******************************************************************************/ 17 #define PSTATE_ID_CORE_IDLE U(6) 18 #define PSTATE_ID_CORE_POWERDN U(7) 19 #define PSTATE_ID_SOC_POWERDN U(2) 20 21 /******************************************************************************* 22 * Platform power states (used by PSCI framework) 23 * 24 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 25 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 26 ******************************************************************************/ 27 #define PLAT_MAX_RET_STATE U(1) 28 #define PLAT_MAX_OFF_STATE U(8) 29 30 /******************************************************************************* 31 * Secure IRQ definitions 32 ******************************************************************************/ 33 #define TEGRA186_MAX_SEC_IRQS U(5) 34 #define TEGRA186_BPMP_WDT_IRQ U(46) 35 #define TEGRA186_SPE_WDT_IRQ U(47) 36 #define TEGRA186_SCE_WDT_IRQ U(48) 37 #define TEGRA186_TOP_WDT_IRQ U(49) 38 #define TEGRA186_AON_WDT_IRQ U(50) 39 40 #define TEGRA186_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */ 41 42 /******************************************************************************* 43 * Tegra Miscellanous register constants 44 ******************************************************************************/ 45 #define TEGRA_MISC_BASE U(0x00100000) 46 47 #define HARDWARE_REVISION_OFFSET U(0x4) 48 #define MISCREG_EMU_REVID U(0x3160) 49 #define BOARD_MASK_BITS U(0xFF) 50 #define BOARD_SHIFT_BITS U(24) 51 #define MISCREG_PFCFG U(0x200C) 52 53 /******************************************************************************* 54 * Tegra Memory Controller constants 55 ******************************************************************************/ 56 #define TEGRA_MC_STREAMID_BASE U(0x02C00000) 57 #define TEGRA_MC_BASE U(0x02C10000) 58 59 /* General Security Carveout register macros */ 60 #define MC_GSC_CONFIG_REGS_SIZE U(0x40) 61 #define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1) 62 #define MC_GSC_ENABLE_TZ_LOCK_BIT (U(1) << 0) 63 #define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27) 64 #define MC_GSC_BASE_LO_SHIFT U(12) 65 #define MC_GSC_BASE_LO_MASK U(0xFFFFF) 66 #define MC_GSC_BASE_HI_SHIFT U(0) 67 #define MC_GSC_BASE_HI_MASK U(3) 68 #define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31) 69 70 /* TZDRAM carveout configuration registers */ 71 #define MC_SECURITY_CFG0_0 U(0x70) 72 #define MC_SECURITY_CFG1_0 U(0x74) 73 #define MC_SECURITY_CFG3_0 U(0x9BC) 74 75 #define MC_SECURITY_BOM_MASK (U(0xFFF) << 20) 76 #define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0) 77 #define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0) 78 79 /* Video Memory carveout configuration registers */ 80 #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 81 #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 82 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 83 84 /* 85 * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the 86 * non-overlapping Video memory region 87 */ 88 #define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0) 89 #define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4) 90 #define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8) 91 #define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC) 92 #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0) 93 94 /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ 95 #define MC_TZRAM_CARVEOUT_CFG U(0x2190) 96 #define MC_TZRAM_BASE_LO U(0x2194) 97 #define MC_TZRAM_BASE_HI U(0x2198) 98 #define MC_TZRAM_SIZE U(0x219C) 99 #define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0) 100 #define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4) 101 #define TZRAM_ALLOW_MPCORER (U(1) << 7) 102 #define TZRAM_ALLOW_MPCOREW (U(1) << 25) 103 104 /* Memory Controller Reset Control registers */ 105 #define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (U(1) << 28) 106 #define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (U(1) << 29) 107 #define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (U(1) << 30) 108 #define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (U(1) << 31) 109 110 /******************************************************************************* 111 * Tegra UART Controller constants 112 ******************************************************************************/ 113 #define TEGRA_UARTA_BASE U(0x03100000) 114 #define TEGRA_UARTB_BASE U(0x03110000) 115 #define TEGRA_UARTC_BASE U(0x0C280000) 116 #define TEGRA_UARTD_BASE U(0x03130000) 117 #define TEGRA_UARTE_BASE U(0x03140000) 118 #define TEGRA_UARTF_BASE U(0x03150000) 119 #define TEGRA_UARTG_BASE U(0x0C290000) 120 121 /******************************************************************************* 122 * Tegra Fuse Controller related constants 123 ******************************************************************************/ 124 #define TEGRA_FUSE_BASE U(0x03820000) 125 #define OPT_SUBREVISION U(0x248) 126 #define SUBREVISION_MASK U(0xF) 127 128 /******************************************************************************* 129 * GICv2 & interrupt handling related constants 130 ******************************************************************************/ 131 #define TEGRA_GICD_BASE U(0x03881000) 132 #define TEGRA_GICC_BASE U(0x03882000) 133 134 /******************************************************************************* 135 * Security Engine related constants 136 ******************************************************************************/ 137 #define TEGRA_SE0_BASE U(0x03AC0000) 138 #define SE_MUTEX_WATCHDOG_NS_LIMIT U(0x6C) 139 #define TEGRA_PKA1_BASE U(0x03AD0000) 140 #define PKA_MUTEX_WATCHDOG_NS_LIMIT U(0x8144) 141 #define TEGRA_RNG1_BASE U(0x03AE0000) 142 #define RNG_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) 143 144 /******************************************************************************* 145 * Tegra micro-seconds timer constants 146 ******************************************************************************/ 147 #define TEGRA_TMRUS_BASE U(0x0C2E0000) 148 #define TEGRA_TMRUS_SIZE U(0x10000) 149 150 /******************************************************************************* 151 * Tegra Power Mgmt Controller constants 152 ******************************************************************************/ 153 #define TEGRA_PMC_BASE U(0x0C360000) 154 155 /******************************************************************************* 156 * Tegra scratch registers constants 157 ******************************************************************************/ 158 #define TEGRA_SCRATCH_BASE U(0x0C390000) 159 #define SECURE_SCRATCH_RSV1_LO U(0x06C) 160 #define SECURE_SCRATCH_RSV1_HI U(0x070) 161 #define SECURE_SCRATCH_RSV6 U(0x094) 162 #define SECURE_SCRATCH_RSV11_LO U(0x0BC) 163 #define SECURE_SCRATCH_RSV11_HI U(0x0C0) 164 #define SECURE_SCRATCH_RSV53_LO U(0x20C) 165 #define SECURE_SCRATCH_RSV53_HI U(0x210) 166 #define SECURE_SCRATCH_RSV54_HI U(0x218) 167 #define SECURE_SCRATCH_RSV55_LO U(0x21C) 168 #define SECURE_SCRATCH_RSV55_HI U(0x220) 169 170 /******************************************************************************* 171 * Tegra Memory Mapped Control Register Access Bus constants 172 ******************************************************************************/ 173 #define TEGRA_MMCRAB_BASE U(0x0E000000) 174 175 /******************************************************************************* 176 * Tegra SMMU Controller constants 177 ******************************************************************************/ 178 #define TEGRA_SMMU0_BASE U(0x12000000) 179 #define TEGRA_SMMU1_BASE U(0x11000000) 180 #define TEGRA_SMMU2_BASE U(0x10000000) 181 182 /******************************************************************************* 183 * Tegra TZRAM constants 184 ******************************************************************************/ 185 #define TEGRA_TZRAM_BASE U(0x40000000) 186 #define TEGRA_TZRAM_SIZE U(0x40000) 187 188 /******************************************************************************* 189 * Tegra Clock and Reset Controller constants 190 ******************************************************************************/ 191 #define TEGRA_CAR_RESET_BASE U(0x20000000) 192 193 /******************************************************************************* 194 * XUSB PADCTL 195 ******************************************************************************/ 196 #define TEGRA_XUSB_PADCTL_BASE U(0x3520000) 197 #define TEGRA_XUSB_PADCTL_SIZE U(0x10000) 198 #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 U(0x136c) 199 #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 U(0x1370) 200 #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 U(0x1374) 201 #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 U(0x1378) 202 #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 U(0x137c) 203 #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 U(0x139c) 204 205 /******************************************************************************* 206 * XUSB STREAMIDs 207 ******************************************************************************/ 208 #define TEGRA_SID_XUSB_HOST U(0x1b) 209 #define TEGRA_SID_XUSB_DEV U(0x1c) 210 #define TEGRA_SID_XUSB_VF0 U(0x5d) 211 #define TEGRA_SID_XUSB_VF1 U(0x5e) 212 #define TEGRA_SID_XUSB_VF2 U(0x5f) 213 #define TEGRA_SID_XUSB_VF3 U(0x60) 214 215 #endif /* __TEGRA_DEF_H__ */ 216