1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __MCE_PRIVATE_H__ 8 #define __MCE_PRIVATE_H__ 9 10 #include <mmio.h> 11 #include <tegra_def.h> 12 13 /******************************************************************************* 14 * Macros to prepare CSTATE info request 15 ******************************************************************************/ 16 /* Description of the parameters for UPDATE_CSTATE_INFO request */ 17 #define CLUSTER_CSTATE_MASK 0x7U 18 #define CLUSTER_CSTATE_SHIFT 0X0U 19 #define CLUSTER_CSTATE_UPDATE_BIT (1U << 7) 20 #define CCPLEX_CSTATE_MASK 0x3U 21 #define CCPLEX_CSTATE_SHIFT 8U 22 #define CCPLEX_CSTATE_UPDATE_BIT (1U << 15) 23 #define SYSTEM_CSTATE_MASK 0xFU 24 #define SYSTEM_CSTATE_SHIFT 16U 25 #define SYSTEM_CSTATE_UPDATE_BIT (1U << 23) 26 #define CSTATE_WAKE_MASK_UPDATE_BIT (1U << 31) 27 #define CSTATE_WAKE_MASK_SHIFT 32U 28 #define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFU 29 30 /******************************************************************************* 31 * Auto-CC3 control macros 32 ******************************************************************************/ 33 #define MCE_AUTO_CC3_FREQ_MASK 0xFFU 34 #define MCE_AUTO_CC3_FREQ_SHIFT 0U 35 #define MCE_AUTO_CC3_ENABLE_BIT (1U << 31) 36 37 /******************************************************************************* 38 * Core ID mask (bits 3:0 in the online request) 39 ******************************************************************************/ 40 #define MCE_CORE_ID_MASK 0xFU 41 42 /******************************************************************************* 43 * Cache control macros 44 ******************************************************************************/ 45 #define CACHE_CLEAN_SET (1U << 0) 46 #define CACHE_CLEAN_INVAL_SET (1U << 1) 47 #define CACHE_CLEAN_INVAL_TR_SET (1U << 2) 48 49 /******************************************************************************* 50 * C-state statistics macros 51 ******************************************************************************/ 52 #define MCE_STAT_ID_SHIFT 16U 53 54 /* declarations for NVG handler functions */ 55 uint64_t nvg_get_version(void); 56 int32_t nvg_enable_power_perf_mode(void); 57 int32_t nvg_disable_power_perf_mode(void); 58 int32_t nvg_enable_power_saver_modes(void); 59 int32_t nvg_disable_power_saver_modes(void); 60 void nvg_set_wake_time(uint32_t wake_time); 61 void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, 62 uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask); 63 int32_t nvg_update_crossover_time(uint32_t type, uint32_t time); 64 int32_t nvg_set_cstate_stat_query_value(uint64_t data); 65 uint64_t nvg_get_cstate_stat_query_value(void); 66 int32_t nvg_is_sc7_allowed(void); 67 int32_t nvg_online_core(uint32_t core); 68 int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable); 69 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx); 70 int32_t nvg_roc_flush_cache(void); 71 int32_t nvg_roc_clean_cache(void); 72 int32_t nvg_roc_clean_cache_trbits(void); 73 int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time); 74 75 void nvg_set_request_data(uint64_t req, uint64_t data); 76 void nvg_set_request(uint64_t req); 77 uint64_t nvg_get_result(void); 78 uint64_t nvg_cache_clean(void); 79 uint64_t nvg_cache_clean_inval(void); 80 uint64_t nvg_cache_inval_all(void); 81 82 #endif /* __MCE_PRIVATE_H__ */ 83