1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef T194_NVG_H 8 #define T194_NVG_H 9 10 /** 11 * t194_nvg.h - Header for the NVIDIA Generic interface (NVG). 12 * Official documentation for this interface is included as part 13 * of the T194 TRM. 14 */ 15 16 /** 17 * Current version - Major version increments may break backwards 18 * compatiblity and binary compatibility. Minor version increments 19 * occur when there is only new functionality. 20 */ 21 enum { 22 TEGRA_NVG_VERSION_MAJOR = 6, 23 TEGRA_NVG_VERSION_MINOR = 1 24 }; 25 26 typedef enum { 27 TEGRA_NVG_CHANNEL_VERSION = 0, 28 TEGRA_NVG_CHANNEL_POWER_PERF = 1, 29 TEGRA_NVG_CHANNEL_POWER_MODES = 2, 30 TEGRA_NVG_CHANNEL_WAKE_TIME = 3, 31 TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, 32 TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, 33 TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, 34 TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, 35 TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, 36 TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, 37 TEGRA_NVG_CHANNEL_SHUTDOWN = 42, 38 TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, 39 TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, 40 TEGRA_NVG_CHANNEL_CC3_CTRL = 45, 41 TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49, 42 TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, 43 TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, 44 TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, 45 TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55, 46 TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56, 47 TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57, 48 TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58, 49 TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59, 50 TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 60, 51 TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 61, 52 TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 62, 53 TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 63, 54 TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 64, 55 TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 65, 56 TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 66, 57 TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 67, 58 TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 68, 59 TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 69, 60 TEGRA_NVG_CHANNEL_LAST_INDEX 61 } tegra_nvg_channel_id_t; 62 63 typedef enum { 64 NVG_STAT_QUERY_SC7_ENTRIES = 1, 65 NVG_STAT_QUERY_CC6_ENTRIES = 6, 66 NVG_STAT_QUERY_CG7_ENTRIES = 7, 67 NVG_STAT_QUERY_C6_ENTRIES = 10, 68 NVG_STAT_QUERY_C7_ENTRIES = 14, 69 NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32, 70 NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41, 71 NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46, 72 NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51, 73 NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56 74 } tegra_nvg_stat_query_t; 75 76 typedef enum { 77 TEGRA_NVG_CORE_C0 = 0, 78 TEGRA_NVG_CORE_C1 = 1, 79 TEGRA_NVG_CORE_C6 = 6, 80 TEGRA_NVG_CORE_C7 = 7, 81 TEGRA_NVG_CORE_WARMRSTREQ = 8 82 } tegra_nvg_core_sleep_state_t; 83 84 typedef enum { 85 TEGRA_NVG_CLUSTER_CC0 = 0, 86 TEGRA_NVG_CLUSTER_CC6 = 6 87 } tegra_nvg_cluster_sleep_state_t; 88 89 typedef enum { 90 TEGRA_NVG_CG_CG0 = 0, 91 TEGRA_NVG_CG_CG7 = 1 92 93 } tegra_nvg_cluster_group_sleep_state_t; 94 95 typedef enum { 96 TEGRA_NVG_SYSTEM_SC0 = 0, 97 TEGRA_NVG_SYSTEM_SC7 = 7, 98 TEGRA_NVG_SYSTEM_SC8 = 8 99 } tegra_nvg_system_sleep_state_t; 100 101 // --------------------------------------------------------------------------- 102 // NVG Data subformats 103 // --------------------------------------------------------------------------- 104 105 typedef union 106 { 107 uint64_t flat; 108 struct nvg_version_channel_t { 109 uint64_t minor_version : 32; 110 uint64_t major_version : 32; 111 } bits; 112 } nvg_version_data_t; 113 114 typedef union nvg_channel_1_data_u 115 { 116 uint64_t flat; 117 struct nvg_channel_1_data_s 118 { 119 uint32_t perf_per_watt_mode : 1; 120 uint32_t reserved_31_1 : 31; 121 uint32_t reserved_63_32 : 32; 122 } bits; 123 } nvg_channel_1_data_t; 124 125 typedef union 126 { 127 uint64_t flat; 128 struct nvg_ccplex_cache_control_channel_t { 129 uint32_t gpu_ways : 5; 130 uint32_t reserved_7_5 : 3; 131 uint32_t gpu_only_ways : 5; 132 uint32_t reserved_31_13 : 19; 133 uint32_t reserved_63_32 : 32; 134 } bits; 135 } nvg_ccplex_cache_control_channel_t; 136 137 typedef union nvg_channel_2_data_u 138 { 139 uint64_t flat; 140 struct nvg_channel_2_data_s 141 { 142 uint32_t reserved_1_0 : 2; 143 uint32_t battery_saver_mode : 1; 144 uint32_t reserved_31_3 : 29; 145 uint32_t reserved_63_32 : 32; 146 } bits; 147 } nvg_channel_2_data_t; 148 149 typedef union 150 { 151 uint64_t flat; 152 struct nvg_wake_time_channel_t { 153 uint32_t wake_time : 32; 154 uint32_t reserved_63_32 : 32; 155 } bits; 156 } nvg_wake_time_channel_t; 157 158 typedef union 159 { 160 uint64_t flat; 161 struct nvg_cstate_info_channel_t { 162 uint32_t cluster_state : 3; 163 uint32_t reserved_6_3 : 4; 164 uint32_t update_cluster : 1; 165 uint32_t cg_cstate : 3; 166 uint32_t reserved_14_11 : 4; 167 uint32_t update_cg : 1; 168 uint32_t system_cstate : 4; 169 uint32_t reserved_22_20 : 3; 170 uint32_t update_system : 1; 171 uint32_t reserved_30_24 : 7; 172 uint32_t update_wake_mask : 1; 173 uint32_t wake_mask : 32; 174 } bits; 175 } nvg_cstate_info_channel_t; 176 177 typedef union 178 { 179 uint64_t flat; 180 struct nvg_lower_bound_channel_t { 181 uint32_t crossover_value : 32; 182 uint32_t reserved_63_32 : 32; 183 } bits; 184 } nvg_lower_bound_channel_t; 185 186 typedef union 187 { 188 uint64_t flat; 189 struct nvg_cstate_stat_query_channel_t { 190 uint32_t unit_id : 4; 191 uint32_t reserved_15_4 : 12; 192 uint32_t stat_id : 16; 193 uint32_t reserved_63_32 : 32; 194 } bits; 195 } nvg_cstate_stat_query_channel_t; 196 197 typedef union 198 { 199 uint64_t flat; 200 struct nvg_is_sc7_allowed_channel_t { 201 uint32_t is_sc7_allowed : 1; 202 uint32_t reserved_31_1 : 31; 203 uint32_t reserved_63_32 : 32; 204 } bits; 205 } nvg_is_sc7_allowed_channel_t; 206 207 typedef union 208 { 209 uint64_t flat; 210 struct nvg_core_online_channel_t { 211 uint32_t core_id : 4; 212 uint32_t reserved_31_4 : 28; 213 uint32_t reserved_63_32 : 32; 214 } bits; 215 } nvg_core_online_channel_t; 216 217 typedef union 218 { 219 uint64_t flat; 220 struct nvg_cc3_control_channel_t { 221 uint32_t freq_req : 8; 222 uint32_t reserved_30_8 : 23; 223 uint32_t enable : 1; 224 uint32_t reserved_63_32 : 32; 225 } bits; 226 } nvg_cc3_control_channel_t; 227 228 typedef enum { 229 TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0 , 230 TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1 , 231 TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2 , 232 TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3 , 233 TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4 , 234 TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5 , 235 TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6 , 236 TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7 , 237 TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8 , 238 TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9 , 239 TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10, 240 TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11, 241 TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12, 242 TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13, 243 TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14, 244 TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15, 245 TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16, 246 TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17, 247 TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18, 248 TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19, 249 TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20, 250 TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21, 251 TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22, 252 TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23, 253 TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24, 254 TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25, 255 TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26, 256 TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27, 257 TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28, 258 TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29, 259 TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30, 260 TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31, 261 TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32, 262 TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33, 263 TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34, 264 TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35, 265 TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX 266 } tegra_nvg_channel_update_gsc_gsc_enum_t; 267 268 typedef union 269 { 270 uint64_t flat; 271 struct nvg_update_ccplex_gsc_channel_t { 272 uint32_t gsc_enum : 16; 273 uint32_t reserved_31_16 : 16; 274 uint32_t reserved_63_32 : 32; 275 } bits; 276 } nvg_update_ccplex_gsc_channel_t; 277 278 typedef union 279 { 280 uint64_t flat; 281 struct nvg_security_config_channel_t { 282 uint32_t strict_checking_enabled : 1; 283 uint32_t strict_checking_locked : 1; 284 uint32_t reserved_31_2 : 30; 285 uint32_t reserved_63_32 : 32; 286 } bits; 287 } nvg_security_config_t; 288 289 typedef union 290 { 291 uint64_t flat; 292 struct nvg_shutdown_channel_t { 293 uint32_t reboot : 1; 294 uint32_t reserved_31_1 : 31; 295 uint32_t reserved_63_32 : 32; 296 } bits; 297 } nvg_shutdown_t; 298 299 #endif 300