1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl31/bl31.h> 10 #include <common/bl_common.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/console.h> 13 #include <context.h> 14 #include <lib/el3_runtime/context_mgmt.h> 15 #include <cortex_a57.h> 16 #include <common/debug.h> 17 #include <denver.h> 18 #include <drivers/arm/gic_common.h> 19 #include <drivers/arm/gicv2.h> 20 #include <bl31/interrupt_mgmt.h> 21 #include <mce.h> 22 #include <plat/common/platform.h> 23 #include <tegra_def.h> 24 #include <tegra_platform.h> 25 #include <tegra_private.h> 26 #include <lib/xlat_tables/xlat_tables_v2.h> 27 28 /******************************************************************************* 29 * The Tegra power domain tree has a single system level power domain i.e. a 30 * single root node. The first entry in the power domain descriptor specifies 31 * the number of power domains at the highest power level. 32 ******************************************************************************* 33 */ 34 const unsigned char tegra_power_domain_tree_desc[] = { 35 /* No of root nodes */ 36 1, 37 /* No of clusters */ 38 PLATFORM_CLUSTER_COUNT, 39 /* No of CPU cores - cluster0 */ 40 PLATFORM_MAX_CPUS_PER_CLUSTER, 41 /* No of CPU cores - cluster1 */ 42 PLATFORM_MAX_CPUS_PER_CLUSTER 43 }; 44 45 /******************************************************************************* 46 * This function returns the Tegra default topology tree information. 47 ******************************************************************************/ 48 const unsigned char *plat_get_power_domain_tree_desc(void) 49 { 50 return tegra_power_domain_tree_desc; 51 } 52 53 /* 54 * Table of regions to map using the MMU. 55 */ 56 static const mmap_region_t tegra_mmap[] = { 57 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 58 MT_DEVICE | MT_RW | MT_SECURE), 59 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 60 MT_DEVICE | MT_RW | MT_SECURE), 61 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 62 MT_DEVICE | MT_RW | MT_SECURE), 63 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 64 MT_DEVICE | MT_RW | MT_SECURE), 65 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ 66 MT_DEVICE | MT_RW | MT_SECURE), 67 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ 68 MT_DEVICE | MT_RW | MT_SECURE), 69 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ 70 MT_DEVICE | MT_RW | MT_SECURE), 71 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 72 MT_DEVICE | MT_RW | MT_SECURE), 73 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 74 MT_DEVICE | MT_RW | MT_SECURE), 75 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 76 MT_DEVICE | MT_RW | MT_SECURE), 77 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 78 MT_DEVICE | MT_RW | MT_SECURE), 79 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 80 MT_DEVICE | MT_RW | MT_SECURE), 81 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 82 MT_DEVICE | MT_RW | MT_SECURE), 83 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 84 MT_DEVICE | MT_RW | MT_SECURE), 85 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 86 MT_DEVICE | MT_RW | MT_SECURE), 87 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 88 MT_DEVICE | MT_RW | MT_SECURE), 89 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */ 90 MT_DEVICE | MT_RW | MT_SECURE), 91 MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000, /* 64KB */ 92 MT_DEVICE | MT_RW | MT_SECURE), 93 MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000, /* 64KB */ 94 MT_DEVICE | MT_RW | MT_SECURE), 95 MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000, /* 64KB */ 96 MT_DEVICE | MT_RW | MT_SECURE), 97 {0} 98 }; 99 100 /******************************************************************************* 101 * Set up the pagetables as per the platform memory map & initialize the MMU 102 ******************************************************************************/ 103 const mmap_region_t *plat_get_mmio_map(void) 104 { 105 /* MMIO space */ 106 return tegra_mmap; 107 } 108 109 /******************************************************************************* 110 * Handler to get the System Counter Frequency 111 ******************************************************************************/ 112 unsigned int plat_get_syscnt_freq2(void) 113 { 114 return 31250000; 115 } 116 117 /******************************************************************************* 118 * Maximum supported UART controllers 119 ******************************************************************************/ 120 #define TEGRA186_MAX_UART_PORTS 7 121 122 /******************************************************************************* 123 * This variable holds the UART port base addresses 124 ******************************************************************************/ 125 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 126 0, /* undefined - treated as an error case */ 127 TEGRA_UARTA_BASE, 128 TEGRA_UARTB_BASE, 129 TEGRA_UARTC_BASE, 130 TEGRA_UARTD_BASE, 131 TEGRA_UARTE_BASE, 132 TEGRA_UARTF_BASE, 133 TEGRA_UARTG_BASE, 134 }; 135 136 /******************************************************************************* 137 * Retrieve the UART controller base to be used as the console 138 ******************************************************************************/ 139 uint32_t plat_get_console_from_id(int id) 140 { 141 if (id > TEGRA186_MAX_UART_PORTS) 142 return 0; 143 144 return tegra186_uart_addresses[id]; 145 } 146 147 /******************************************************************************* 148 * Handler for early platform setup 149 ******************************************************************************/ 150 void plat_early_platform_setup(void) 151 { 152 153 /* sanity check MCE firmware compatibility */ 154 mce_verify_firmware_version(); 155 156 /* Program XUSB STREAMIDs 157 * Xavier XUSB has support for XUSB virtualization. It will have one 158 * physical function (PF) and four Virtual function (VF) 159 * 160 * There were below two SIDs for XUSB until T186. 161 * 1) #define TEGRA_SID_XUSB_HOST 0x1bU 162 * 2) #define TEGRA_SID_XUSB_DEV 0x1cU 163 * 164 * We have below four new SIDs added for VF(s) 165 * 3) #define TEGRA_SID_XUSB_VF0 0x5dU 166 * 4) #define TEGRA_SID_XUSB_VF1 0x5eU 167 * 5) #define TEGRA_SID_XUSB_VF2 0x5fU 168 * 6) #define TEGRA_SID_XUSB_VF3 0x60U 169 * 170 * When virtualization is enabled then we have to disable SID override 171 * and program above SIDs in below newly added SID registers in XUSB 172 * PADCTL MMIO space. These registers are TZ protected and so need to 173 * be done in ATF. 174 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) 175 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) 176 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) 177 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) 178 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) 179 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) 180 * 181 * This change disables SID override and programs XUSB SIDs in 182 * above registers to support both virtualization and non-virtualization 183 * 184 * Known Limitations: 185 * If xusb interface disables SMMU in XUSB DT in non-virtualization 186 * setup then there will be SMMU fault. We need to use WAR at 187 * https://git-master.nvidia.com/r/1529227/ to the issue. 188 * 189 * More details can be found in the bug 1971161 190 */ 191 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 192 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); 193 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 194 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); 195 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 196 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); 197 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 198 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); 199 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 200 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); 201 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 202 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); 203 } 204 205 /* Secure IRQs for Tegra186 */ 206 static const irq_sec_cfg_t tegra186_sec_irqs[] = { 207 [0] = { 208 TEGRA186_BPMP_WDT_IRQ, 209 TEGRA186_SEC_IRQ_TARGET_MASK, 210 INTR_TYPE_EL3, 211 }, 212 [1] = { 213 TEGRA186_BPMP_WDT_IRQ, 214 TEGRA186_SEC_IRQ_TARGET_MASK, 215 INTR_TYPE_EL3, 216 }, 217 [2] = { 218 TEGRA186_SPE_WDT_IRQ, 219 TEGRA186_SEC_IRQ_TARGET_MASK, 220 INTR_TYPE_EL3, 221 }, 222 [3] = { 223 TEGRA186_SCE_WDT_IRQ, 224 TEGRA186_SEC_IRQ_TARGET_MASK, 225 INTR_TYPE_EL3, 226 }, 227 [4] = { 228 TEGRA186_TOP_WDT_IRQ, 229 TEGRA186_SEC_IRQ_TARGET_MASK, 230 INTR_TYPE_EL3, 231 }, 232 [5] = { 233 TEGRA186_AON_WDT_IRQ, 234 TEGRA186_SEC_IRQ_TARGET_MASK, 235 INTR_TYPE_EL3, 236 }, 237 }; 238 239 /******************************************************************************* 240 * Initialize the GIC and SGIs 241 ******************************************************************************/ 242 void plat_gic_setup(void) 243 { 244 tegra_gic_setup(tegra186_sec_irqs, 245 sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 246 247 /* 248 * Initialize the FIQ handler only if the platform supports any 249 * FIQ interrupt sources. 250 */ 251 if (sizeof(tegra186_sec_irqs) > 0) 252 tegra_fiq_handler_setup(); 253 } 254 255 /******************************************************************************* 256 * Return pointer to the BL31 params from previous bootloader 257 ******************************************************************************/ 258 struct tegra_bl31_params *plat_get_bl31_params(void) 259 { 260 uint32_t val; 261 262 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 263 264 return (struct tegra_bl31_params *)(uintptr_t)val; 265 } 266 267 /******************************************************************************* 268 * Return pointer to the BL31 platform params from previous bootloader 269 ******************************************************************************/ 270 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 271 { 272 uint32_t val; 273 274 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 275 276 return (plat_params_from_bl2_t *)(uintptr_t)val; 277 } 278