1# 2# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# platform configs 8ENABLE_AFI_DEVICE := 0 9$(eval $(call add_define,ENABLE_AFI_DEVICE)) 10 11ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 0 12$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS)) 13 14ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM := 1 15$(eval $(call add_define,ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM)) 16 17RELOCATE_TO_BL31_BASE := 1 18$(eval $(call add_define,RELOCATE_TO_BL31_BASE)) 19 20ENABLE_CHIP_VERIFICATION_HARNESS := 0 21$(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS)) 22 23ENABLE_SMMU_DEVICE := 1 24$(eval $(call add_define,ENABLE_SMMU_DEVICE)) 25 26RESET_TO_BL31 := 1 27 28PROGRAMMABLE_RESET_ADDRESS := 1 29 30COLD_BOOT_SINGLE_CPU := 1 31 32# platform settings 33TZDRAM_BASE := 0x40000000 34$(eval $(call add_define,TZDRAM_BASE)) 35 36PLATFORM_CLUSTER_COUNT := 2 37$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) 38 39PLATFORM_MAX_CPUS_PER_CLUSTER := 4 40$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) 41 42MAX_XLAT_TABLES := 25 43$(eval $(call add_define,MAX_XLAT_TABLES)) 44 45MAX_MMAP_REGIONS := 25 46$(eval $(call add_define,MAX_MMAP_REGIONS)) 47 48# platform files 49PLAT_INCLUDES += -I${SOC_DIR}/drivers/include 50 51BL31_SOURCES += lib/cpus/aarch64/denver.S \ 52 ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ 53 ${COMMON_DIR}/drivers/smmu/smmu.c \ 54 ${SOC_DIR}/drivers/mce/mce.c \ 55 ${SOC_DIR}/drivers/mce/nvg.c \ 56 ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \ 57 ${SOC_DIR}/plat_memctrl.c \ 58 ${SOC_DIR}/plat_psci_handlers.c \ 59 ${SOC_DIR}/plat_setup.c \ 60 ${SOC_DIR}/plat_secondary.c \ 61 ${SOC_DIR}/plat_sip_calls.c \ 62 ${SOC_DIR}/plat_smmu.c 63 64ifeq (${ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM}, 1) 65BL31_SOURCES += ${SOC_DIR}/plat_trampoline.S 66endif 67