xref: /rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c (revision ac2cc6b091c34ba0a0d63ae5c8c8ee2f235fa7a1)
1 /*
2  * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <arch.h>
8 #include <arch_helpers.h>
9 #include <assert.h>
10 #include <common/bl_common.h>
11 #include <context.h>
12 #include <lib/el3_runtime/context_mgmt.h>
13 #include <common/debug.h>
14 #include <denver.h>
15 #include <mce.h>
16 #include <mce_private.h>
17 #include <platform_def.h>
18 #include <stdbool.h>
19 #include <string.h>
20 #include <errno.h>
21 #include <t194_nvg.h>
22 #include <tegra_def.h>
23 #include <tegra_platform.h>
24 
25 /* Handler to check if MCE firmware is supported */
26 static bool mce_firmware_not_supported(void)
27 {
28 	bool status;
29 
30 	/* these platforms do not load MCE firmware */
31 	status = tegra_platform_is_linsim() || tegra_platform_is_qt() ||
32 		 tegra_platform_is_virt_dev_kit();
33 
34 	return status;
35 }
36 
37 /*******************************************************************************
38  * Common handler for all MCE commands
39  ******************************************************************************/
40 int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
41 			uint64_t arg2)
42 {
43 	int32_t ret = 0;
44 
45 	switch (cmd) {
46 	case (uint64_t)MCE_CMD_ENTER_CSTATE:
47 		ret = nvg_enter_cstate((uint32_t)arg0, (uint32_t)arg1);
48 		if (ret < 0) {
49 			ERROR("%s: enter_cstate failed(%d)\n", __func__, ret);
50 		}
51 
52 		break;
53 
54 	case (uint64_t)MCE_CMD_IS_SC7_ALLOWED:
55 		ret = nvg_is_sc7_allowed();
56 		if (ret < 0) {
57 			ERROR("%s: is_sc7_allowed failed(%d)\n", __func__, ret);
58 		}
59 
60 		break;
61 
62 	case (uint64_t)MCE_CMD_ONLINE_CORE:
63 		ret = nvg_online_core((uint32_t)arg0);
64 		if (ret < 0) {
65 			ERROR("%s: online_core failed(%d)\n", __func__, ret);
66 		}
67 
68 		break;
69 
70 	default:
71 		ERROR("unknown MCE command (%llu)\n", cmd);
72 		ret = -EINVAL;
73 		break;
74 	}
75 
76 	return ret;
77 }
78 
79 /*******************************************************************************
80  * Handler to update carveout values for Video Memory Carveout region
81  ******************************************************************************/
82 int32_t mce_update_gsc_videomem(void)
83 {
84 	int32_t ret;
85 
86 	/*
87 	 * MCE firmware is not running on simulation platforms.
88 	 */
89 	if (mce_firmware_not_supported()) {
90 		ret = -EINVAL;
91 	} else {
92 		ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR);
93 	}
94 
95 	return ret;
96 }
97 
98 /*******************************************************************************
99  * Handler to update carveout values for TZDRAM aperture
100  ******************************************************************************/
101 int32_t mce_update_gsc_tzdram(void)
102 {
103 	int32_t ret;
104 
105 	/*
106 	 * MCE firmware is not running on simulation platforms.
107 	 */
108 	if (mce_firmware_not_supported()) {
109 		ret = -EINVAL;
110 	} else {
111 		ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM);
112 	}
113 
114 	return ret;
115 }
116 
117 /*******************************************************************************
118  * Handler to update carveout values for TZ SysRAM aperture
119  ******************************************************************************/
120 int32_t mce_update_gsc_tzram(void)
121 {
122 	int32_t ret;
123 
124 	/*
125 	 * MCE firmware is not running on simulation platforms.
126 	 */
127 	if (mce_firmware_not_supported()) {
128 		ret = -EINVAL;
129 	} else {
130 		ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM);
131 	}
132 
133 	return ret;
134 }
135 
136 /*******************************************************************************
137  * Handler to issue the UPDATE_CSTATE_INFO request
138  ******************************************************************************/
139 void mce_update_cstate_info(const mce_cstate_info_t *cstate)
140 {
141 	/* issue the UPDATE_CSTATE_INFO request */
142 	nvg_update_cstate_info(cstate->cluster, cstate->ccplex, cstate->system,
143 		cstate->wake_mask, cstate->update_wake_mask);
144 }
145 
146 /*******************************************************************************
147  * Handler to read the MCE firmware version and check if it is compatible
148  * with interface header the BL3-1 was compiled against
149  ******************************************************************************/
150 void mce_verify_firmware_version(void)
151 {
152 	uint64_t version;
153 	uint32_t major, minor;
154 
155 	/*
156 	 * MCE firmware is not running on simulation platforms.
157 	 */
158 	if (mce_firmware_not_supported()) {
159 		return;
160 	}
161 
162 	/*
163 	 * Read the MCE firmware version and extract the major and minor
164 	 * version fields
165 	 */
166 	version = nvg_get_version();
167 	minor = (uint32_t)version;
168 	major = (uint32_t)(version >> 32);
169 
170 	INFO("MCE Version - HW=%u:%u, SW=%u:%u\n", major, minor,
171 		TEGRA_NVG_VERSION_MAJOR, TEGRA_NVG_VERSION_MINOR);
172 
173 	/*
174 	 * Verify that the MCE firmware version and the interface header
175 	 * match
176 	 */
177 	if (major != (uint32_t)TEGRA_NVG_VERSION_MAJOR) {
178 		ERROR("MCE major version mismatch\n");
179 		panic();
180 	}
181 
182 	if (minor < (uint32_t)TEGRA_NVG_VERSION_MINOR) {
183 		ERROR("MCE minor version mismatch\n");
184 		panic();
185 	}
186 }
187