| 5d1c211e | 05-Aug-2021 |
Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> |
fix(plat/xilinx/versal): resolve misra R10.3 in pm services
MISRA Violation: MISRA-C:2012 R.10.3
- The value of an expression shall not be assigned to an object with a
narrower essential type or o
fix(plat/xilinx/versal): resolve misra R10.3 in pm services
MISRA Violation: MISRA-C:2012 R.10.3
- The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I73c056ff4df2f14e04c92a49ac5c97e578e82107
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| fa98d7f2 | 05-Aug-2021 |
Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> |
fix(plat/xilinx/versal): resolve misra R10.6 in pm services
MISRA Violation: MISRA-C:2012 R.10.6
- The value of a composite expression shall not be assigned to an object
with wider essential type.
fix(plat/xilinx/versal): resolve misra R10.6 in pm services
MISRA Violation: MISRA-C:2012 R.10.6
- The value of a composite expression shall not be assigned to an object
with wider essential type.
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I67ac6b6b4b643f57e76a435345540e241c9a88b9
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| 27ae5310 | 05-Aug-2021 |
Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> |
fix(plat/xilinx/versal): resolve misra R16.3 in pm services
MISRA Violation: MISRA-C:2012 R.16.3
- An unconditional break statement shall terminate every switch-clause
Signed-off-by: Abhyuday Godha
fix(plat/xilinx/versal): resolve misra R16.3 in pm services
MISRA Violation: MISRA-C:2012 R.16.3
- An unconditional break statement shall terminate every switch-clause
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I576b2c6eb7d1b7ef20440b9a616886ccf230b63e
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| 41567195 | 05-Aug-2021 |
Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> |
fix(plat/xilinx/versal): resolve misra R15.6 in pm services
MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
a compound statement
Signed
fix(plat/xilinx/versal): resolve misra R15.6 in pm services
MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
a compound statement
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I82e924a77ee3afeb56fa18714e94cc4f6fff5a49
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| 4ce3e99a | 25-Aug-2020 |
Scott Branden <scott.branden@broadcom.com> |
fix: libc: use long for 64-bit types on aarch64
Use long instead of long long on aarch64 for 64_t stdint types.
Introduce inttypes.h to properly support printf format specifiers for
fixed width type
fix: libc: use long for 64-bit types on aarch64
Use long instead of long long on aarch64 for 64_t stdint types.
Introduce inttypes.h to properly support printf format specifiers for
fixed width types for such change.
Change-Id: I0bca594687a996fde0a9702d7a383055b99f10a1
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
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| 578f468a | 11-Aug-2021 |
Ronak Jain <ronak.jain@xilinx.com> |
feat(plat/xilinx/zynqmp): add support for runtime feature config
Add support for runtime feature configuration which are running on the
firmware. Add new IOCTL IDs like IOCTL_SET_FEATURE_CONFIG and
feat(plat/xilinx/zynqmp): add support for runtime feature config
Add support for runtime feature configuration which are running on the
firmware. Add new IOCTL IDs like IOCTL_SET_FEATURE_CONFIG and
IOCTL_GET_FEATURE_CONFIG for configuring the features.
Signed-off-by: Ronak Jain <ronak.jain@xilinx.com>
Change-Id: I976aef15932783a25396b2adeb4c8f140cc87e79
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| 38c0b252 | 28-Jun-2021 |
Ronak Jain <ronak.jain@xilinx.com> |
feat(plat/xilinx/zynqmp): sync IOCTL IDs
Sync IOCTL IDs in order to avoid conflict with other components like,
Linux and firmware. Hence assigning value to IDs to make it more
specific.
Signed-of
feat(plat/xilinx/zynqmp): sync IOCTL IDs
Sync IOCTL IDs in order to avoid conflict with other components like,
Linux and firmware. Hence assigning value to IDs to make it more
specific.
Signed-off-by: Ronak Jain <ronak.jain@xilinx.com>
Change-Id: I11ae679fbd0a953290306b62d661cc142f50dc28
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| be3a51ce | 13-Aug-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(plat/versal): add support for SLS mitigation" into integration |
| 62f9134d | 05-Aug-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
revert(plat/xilinx): add timeout while waiting for IPI Ack
This reverts commit 4d9b9b2352f9a67849faf2d4484f5fcdd2788b01.
Timeout in IPI ack was added for functional safety reason.
Functional safety
revert(plat/xilinx): add timeout while waiting for IPI Ack
This reverts commit 4d9b9b2352f9a67849faf2d4484f5fcdd2788b01.
Timeout in IPI ack was added for functional safety reason.
Functional safety is not criteria for ATF. However, this
creates issues for APIs that take long or non-deterministic
duration like FPGA load. So revert this patch for now to fix
FPGA loading issue. Need to add support for non-blocking API
for FPGA loading with callback when API completes.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I940e798f1e2f7d0dfca1da5caaf8b94036d440c6
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| 302b4dfb | 21-Jul-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
feat(plat/versal): add support for SLS mitigation
This patch adds the option HARDEN_SLS_ALL that can be used to enable
the -mharden-sls=all, which mitigates the straight-line speculation
vulnerabili
feat(plat/versal): add support for SLS mitigation
This patch adds the option HARDEN_SLS_ALL that can be used to enable
the -mharden-sls=all, which mitigates the straight-line speculation
vulnerability. Enable this by adding the option HARDEN_SLS_ALL=1,
default this will be disabled.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I0d498d9e96903fcb879993ad491949f6f17769b2
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| fa581715 | 24-Jun-2021 |
Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> |
fix(plat/xilinx/versal): use sync method for blocking calls
All API calls except non-blocking should wait for
IPI response and read buffer to check return status
from firmware. Some of API calls are
fix(plat/xilinx/versal): use sync method for blocking calls
All API calls except non-blocking should wait for
IPI response and read buffer to check return status
from firmware. Some of API calls are not reading
status from IPI payload data. Use sync method which
reads actual return status from IPI payload.
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I6f568b85d0da639c264f507122e3015807d8423d
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| c063c5a4 | 24-Jun-2021 |
Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> |
fix(plat/xilinx/zynqmp): use sync method for blocking calls
All API calls except non-blocking should wait for
IPI response and read buffer to check return status
from firmware. Some of API calls are
fix(plat/xilinx/zynqmp): use sync method for blocking calls
All API calls except non-blocking should wait for
IPI response and read buffer to check return status
from firmware. Some of API calls are not reading
status from IPI payload data. Use sync method which
reads actual return status from IPI payload.
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I78f9c061a80cee6d524ade4ef124ca88ce1848cf
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| a43179a6 | 07-Jul-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(plat/zynqmp): extend DT description by TF-A" into integration |
| db97f939 | 17-Jun-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
refactor(plat/zynqmp): optimize the code to save some space
As there is constraint with the space for the release builds,
remove some of the legacy code.
Signed-off-by: Venkatesh Yadav Abbarapu <ve
refactor(plat/zynqmp): optimize the code to save some space
As there is constraint with the space for the release builds,
remove some of the legacy code.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I5b8b16f34ed8e480f16ab1aeac80b85cdb391852
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| 0a8143dd | 27-May-2021 |
Michal Simek <michal.simek@xilinx.com> |
feat(plat/zynqmp): extend DT description by TF-A
In case of TF-A running out of DDR there is a need to reserved
memory to let other SW know that none can't use this memory. HW
wise this region can b
feat(plat/zynqmp): extend DT description by TF-A
In case of TF-A running out of DDR there is a need to reserved
memory to let other SW know that none can't use this memory. HW
wise this region can be (and should be) also protected by
protection unit XMPU. This is the first step to add reserved
memory location to DT.
DT address corresponds with default address in U-Boot and also
default address in Xilinx BSPs.
Code is valid only when TF-A runs out of DDR. When it runs out
of OCM there is no need to reseve anything because OCM is hidden
to OS.
Change-Id: I01f230ced67207a159128cc11d11d36dd4590cab
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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| 4143268a | 14-Jul-2020 |
Jan Kiszka <jan.kiszka@siemens.com> |
feat(plat/zynqmp): add SDEI support
Add basic SDEI support, implementing the software event 0 only for now.
This already allows hypervisors like Jailhouse to use SDEI for internal
signaling while pa
feat(plat/zynqmp): add SDEI support
Add basic SDEI support, implementing the software event 0 only for now.
This already allows hypervisors like Jailhouse to use SDEI for internal
signaling while passing the GICC through to the guest (see also IMX8).
With SDEI on, we overrun the SRAM and need to stay in DRAM. So keep SDEI
off by default.
Co-developed-by: Angelo Ruocco <angeloruocco90@gmail.com>
Signed-off-by: Angelo Ruocco <angeloruocco90@gmail.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: Ic0d71b4ef0978c0a34393f4e3530ed1e24a39ca2
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| 7a30e08b | 22-Apr-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
feat(plat/zynqmp): add support for XCK26 silicon
Add support for XCK26 silicon which is available on SOM board.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Venkatesh Yadav
feat(plat/zynqmp): add support for XCK26 silicon
Add support for XCK26 silicon which is available on SOM board.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ic98213328702903af8a79f487a2868f3e6d60338
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| e1e5b133 | 20-Apr-2021 |
Rajan Vaja <rajan.vaja@xilinx.com> |
fix(plat/xilinx/versal/include): correct IPI buffer offset
Use proper offset for IPI data based on offset for IPI0
channel.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Abhyuday
fix(plat/xilinx/versal/include): correct IPI buffer offset
Use proper offset for IPI data based on offset for IPI0
channel.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I3070517944dd353c3733aa595df0da030127751a
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| 78c7beb4 | 31-Mar-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat: send an sgi to communicate to linux
Upon recieving the interrupt send an SGI.
The sgi number is communicated by linux.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Change
plat: send an sgi to communicate to linux
Upon recieving the interrupt send an SGI.
The sgi number is communicated by linux.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Change-Id: Ib8f07ff7132ba5ac202b546914efb16d04820ed3
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
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| 8b48bfb8 | 17-Mar-2021 |
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> |
plat: xilinx: Error management support
Add support for the trapping the IPI in TF-A.
Register handler for the irq no 62 which is the IPI interrupt.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.d
plat: xilinx: Error management support
Add support for the trapping the IPI in TF-A.
Register handler for the irq no 62 which is the IPI interrupt.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Change-Id: I9c04fdae7be3dda6a34a9b196274c0b5fdf39223
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
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| d8dc8c9e | 21-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "plat: xilinx: zynqmp: Configure counter frequency during initialization" into integration |
| 9f0ddae3 | 26-Mar-2021 |
Rajan Vaja <rajan.vaja@xilinx.com> |
plat: xilinx: zynqmp: Configure counter frequency during initialization
Counter frequency for generic timer of Arm-A53 based Application
Processing Unit(APU) is not configuring in case if First Stag
plat: xilinx: zynqmp: Configure counter frequency during initialization
Counter frequency for generic timer of Arm-A53 based Application
Processing Unit(APU) is not configuring in case if First Stage Boot
Loader(FSBL) does not initialize counter frequency. This happens
when FSBL is running from Arm-R5 based Real-time Processing Unit(RPU).
Because of that generic timer driver functionality is not working.
So configure counter frequency during initialization.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Icfccd59d7d2340fba25ebfb2ef6a813af4290896
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| 654bd99d | 19-Feb-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat: xilinx: versal: Add the IPI CRC checksum macro support
Add support for CRC checksum for IPI data when the macro
IPI_CRC_CHECK is enabled.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.ab
plat: xilinx: versal: Add the IPI CRC checksum macro support
Add support for CRC checksum for IPI data when the macro
IPI_CRC_CHECK is enabled.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I3c25c715885759076055c6505471339b5d6edcd5
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| d7758354 | 19-Feb-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat: xilinx: common: Rename the IPI CRC checksum macro
Rename the macro ZYNQMP_IPI_CRC_CHECK to IPI_CRC_CHECK and
move the related defines to the common include.
Signed-off-by: Venkatesh Yadav Abb
plat: xilinx: common: Rename the IPI CRC checksum macro
Rename the macro ZYNQMP_IPI_CRC_CHECK to IPI_CRC_CHECK and
move the related defines to the common include.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I6d30b081ac607572a0b23e10ca8031bc90489e58
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| 0b25f404 | 27-Nov-2020 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat:xilinx:versal: Add JTAG DCC support
As per the new multi-console framework, updating the JTAG DCC support.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Mic
plat:xilinx:versal: Add JTAG DCC support
As per the new multi-console framework, updating the JTAG DCC support.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I77994ce387caf0d695986df3d01d414a920978d0
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