fix(intel): update boot scratch cold register to use cold 8

Boot scratch cold 8 register is fully used by n5x.
Update to use boot scratch cold 8 bit 19 register for cpu0 ON/OFF
indicator.

Change-Id

fix(intel): update boot scratch cold register to use cold 8

Boot scratch cold 8 register is fully used by n5x.
Update to use boot scratch cold 8 bit 19 register for cpu0 ON/OFF
indicator.

Change-Id: I45ebfdcc17c47bcce69f5f611e677ac7838ecf52
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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feat(intel): restructure watchdog

This patch is to restructure watchdog.
Move platform dependent MACROs to individual platform socfpga_plat_def.
Common watchdog code file and header file will remain

feat(intel): restructure watchdog

This patch is to restructure watchdog.
Move platform dependent MACROs to individual platform socfpga_plat_def.
Common watchdog code file and header file will remain for those common
declaration.

Change-Id: Ibb640f08ac313bbad6d9295596cb8ff26e3e626d
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): platform enablement for Agilex5 SoC FPGA

This patch is used to enable platform enablement for
Agilex5 SoC FPGA.

New feature:
1. Added ATF->Zephyr boot option
2. Added xlat_v2 for MMU

feat(intel): platform enablement for Agilex5 SoC FPGA

This patch is used to enable platform enablement for
Agilex5 SoC FPGA.

New feature:
1. Added ATF->Zephyr boot option
2. Added xlat_v2 for MMU
3. Added ATF->Linux boot option
4. Added SMP support
5. Added HPS bridges support
6. Added EMULATOR support
7. Added DDR support
8. Added GICv3 Redistirbution init
9. Added SDMMC/NAND/Combo Phy support
10. Updated GIC as secure access
11. Added CCU driver support
12. Updated product name -> Agilex5
13. Updated register address based on y22ww52.2 RTL
14. Updated system counter freq to 400MHz

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ice82f3e4535527cfd01500d4d528402985f72009

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feat(intel): ccu driver for Agilex5 SoC FPGA

This patch is used to implement CCU driver for
Agilex5 SoC FPGA.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic5e38499c969486682761c

feat(intel): ccu driver for Agilex5 SoC FPGA

This patch is used to implement CCU driver for
Agilex5 SoC FPGA.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic5e38499c969486682761c00d9e050e60c883725

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feat(intel): vab support for Agilex5 SoC FPGA

This patch is used to implement VAB to support for
Agilex5 SoC FPGA.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I421f11225cd549f35

feat(intel): vab support for Agilex5 SoC FPGA

This patch is used to implement VAB to support for
Agilex5 SoC FPGA.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I421f11225cd549f35f06e87b8ad2c44b716b2a78

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feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA

This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-

feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA

This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-PHY support.
2. Updated product name -> Agilex5
3. Updated QSPI base address

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6

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feat(intel): ddr driver for Agilex5 SoC FPGA

This patch is used to implement ddr driver to
support IO96b for Agilex5 SoC FPGA.
1. Added DDR support.
2. Updated product name -> Agilex5

Signed-off-

feat(intel): ddr driver for Agilex5 SoC FPGA

This patch is used to implement ddr driver to
support IO96b for Agilex5 SoC FPGA.
1. Added DDR support.
2. Updated product name -> Agilex5

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ibda053de6dbec4a0f12f011d8feeb6c5890fc7a4

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feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA

This patch is used to implement
1. Cold/Warm reset and SMP support for
Agilex5 SoC FPGA
2. Updated product name -> Agilex5

Signe

feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA

This patch is used to implement
1. Cold/Warm reset and SMP support for
Agilex5 SoC FPGA
2. Updated product name -> Agilex5

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I2c0645bcbf3a5907a4c79f35cffe674920b48f9d

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feat(intel): reset manager support for Agilex5 SoC FPGA

This patch is used to enable reset manager support
for Agilex5 SoC FPGA.
1. Added HPS bridges support
a. SOC2FPGA
b. LWSOC2FPGA
c. F2SD

feat(intel): reset manager support for Agilex5 SoC FPGA

This patch is used to enable reset manager support
for Agilex5 SoC FPGA.
1. Added HPS bridges support
a. SOC2FPGA
b. LWSOC2FPGA
c. F2SDRAM
d. F2SOC
2. Added EMULATOR support
3. Added WDT support
4. Updated product name -> Agilex5
5. Added SMP support

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Icab15b25f787fdccce1de75d102604db23beaf11

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feat(intel): mailbox and SMC support for Agilex5 SoC FPGA

This patch is used to enable mailbox and SMC support
for Agilex5 SoC FPGA.
1. Enabled mailbox and SMC support.
2. Updated product name ->

feat(intel): mailbox and SMC support for Agilex5 SoC FPGA

This patch is used to enable mailbox and SMC support
for Agilex5 SoC FPGA.
1. Enabled mailbox and SMC support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
4. Updated TSN register base address

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I152bee5668b96ef599ded09945167f27a71f23fe

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feat(intel): system manager support for Agilex5 SoC FPGA

This patch is used to implement system manager data
support for Agilex5 SoC FPGA.

1. Initial SM bring up
2. Support Candence SDMMC/NAND/CO

feat(intel): system manager support for Agilex5 SoC FPGA

This patch is used to implement system manager data
support for Agilex5 SoC FPGA.

1. Initial SM bring up
2. Support Candence SDMMC/NAND/COMBO PHY
3. Updated product name -> Agilex5
4. Updated register address based on y22ww52.2 RTL

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I12712bddfb67e36a2bf56d2d98ea4ca3037f0a82

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feat(intel): uart support for Agilex5 SoC FPGA

This patch is used to enable UART & WDT support
for Agilex5 SoC FPGA.

1. Added watchdog support.
2. Updated product name -> Agilex5

Signed-off-by:

feat(intel): uart support for Agilex5 SoC FPGA

This patch is used to enable UART & WDT support
for Agilex5 SoC FPGA.

1. Added watchdog support.
2. Updated product name -> Agilex5

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I9346cfde6e033026e4c1e612250e9521bc6b0d47

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feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA

This patch is used to enable pinmux, peripheral and handoff support
for Agilex5 SoC FPGA.
1. Initial handoff bring up
2. Ad

feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA

This patch is used to enable pinmux, peripheral and handoff support
for Agilex5 SoC FPGA.
1. Initial handoff bring up
2. Added power manager handoff implementation
3. Added sdram handoff implementation
4. Updated product name -> Agilex5
5. Updated register address based on y22ww52.2 RTL

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I4b0176bc86c57823127bf41086306015d702577d

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fix(intel): fix ncore ccu snoop dvm enable bug

Incorrect value stored in Coherent Subsystem ACE DVM Snoop Enable
register (CSADSER0). Set individual bit othervise previous value
is overwritten.

Sig

fix(intel): fix ncore ccu snoop dvm enable bug

Incorrect value stored in Coherent Subsystem ACE DVM Snoop Enable
register (CSADSER0). Set individual bit othervise previous value
is overwritten.

Signed-off-by: Anders Hedlund <anders.hedlund@windriver.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ib72fed261cbc3076ce385e19c4a5fa8e9e8b9924

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feat(intel): add intel_rsu_update() to sip_svc_v2

Add smc function id for intel_rsu_update() in sip_svc_v2. For temporarily
saving the RSU application image address before a cold reset is
issued.

S

feat(intel): add intel_rsu_update() to sip_svc_v2

Add smc function id for intel_rsu_update() in sip_svc_v2. For temporarily
saving the RSU application image address before a cold reset is
issued.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43bc7bd5aa5fa9238bceba1d826bf0a34ff87adb

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Merge "fix(intel): update checking for memcpy and memset" into integration

Merge changes I38545567,I2f52d3ea into integration

* changes:
feat(intel): restructure sys mgr for S10/N5X
feat(intel): restructure sys mgr for Agilex

feat(intel): restructure sys mgr for S10/N5X

This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for

feat(intel): restructure sys mgr for S10/N5X

This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for those common declaration only.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I385455671413e154d04a879d33fdd774fcfefbd6

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feat(intel): restructure sys mgr for Agilex

This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for t

feat(intel): restructure sys mgr for Agilex

This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for those common declaration only.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I2f52d3eaf47716f7dfc636bbf1a23d68a04f39cb

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fix(intel): update checking for memcpy and memset

Add checking on the size of source data does not exceed source size
when using memcpy and memset.

Add checking on the size of source data in FPGA C

fix(intel): update checking for memcpy and memset

Add checking on the size of source data does not exceed source size
when using memcpy and memset.

Add checking on the size of source data in FPGA Crypto Service does
not exceed the maximum of expected data size and does not meet the
minimum of expected data size.

Signed-off-by: Phui Kei Wong <phui.kei.wong@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Idb18f05c18d9142fbe703c3f4075341d179d8bad

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feat(intel): setup SEU ERR read interface for FP8

Enable SEU ERR read interfaces for non-secure world to read out SEU status
for DDR.
SEU ERR SMC opcode updated to 0xC2000099

Signed-off-by: Jit Loo

feat(intel): setup SEU ERR read interface for FP8

Enable SEU ERR read interfaces for non-secure world to read out SEU status
for DDR.
SEU ERR SMC opcode updated to 0xC2000099

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I0618dfcdc86a7c1e0c8047b7214d369866dd2281

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fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373

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fix(intel): fix Agilex and N5X clock manager to main PLL C0

Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ

fix(intel): fix Agilex and N5X clock manager to main PLL C0

Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ to
PLAT_HZ_CONVERT_TO_MHZ.
2. Updated get_cpu_clk to point to get_mpu_clk and added comment.
3. Added get_mpu_clk to get clock from main PLL C0 and Peri PLL C0.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43a9d83caa832b61eba93a830e2a671fd4dffa19

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feat(intel): implement timer init divider via CPU frequency for N5X

Get CPU frequency and update the timer init div with it.
The timer is vary based on the CPU frequency instead of hardcoded.

Signe

feat(intel): implement timer init divider via CPU frequency for N5X

Get CPU frequency and update the timer init div with it.
The timer is vary based on the CPU frequency instead of hardcoded.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibfaa47fb7a25176eebf06f4828bf9729d56f12ed

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Merge "feat(intel): fix bridge disable and reset" into integration