1# 2# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's 32# progbits limit. We need a way to build all useful configurations while waiting 33# on the fvp to increase its SRAM size. The problem is twofild: 34# 1. the cleanup that introduced these enables cleaned up tf-a a little too 35# well and things that previously (incorrectly) were enabled, no longer are. 36# A bunch of CI configs build subtly incorrectly and this combo makes it 37# necessary to forcefully and unconditionally enable them here. 38# 2. the progbits limit is exceeded only when the tsp is involved. However, 39# there are tsp CI configs that run on very high architecture revisions so 40# disabling everything isn't an option. 41# The fix is to enable everything, as before. When the tsp is included, though, 42# we need to slim the size down. In that case, disable all optional features, 43# that will not be present in CI when the tsp is. 44# Similarly, DRTM support is only tested on v8.0 models. Disable everything just 45# for it. 46# TODO: make all of this unconditional (or only base the condition on 47# ARM_ARCH_* when the makefile supports it). 48ifneq (${DRTM_SUPPORT}, 1) 49ifneq (${SPD}, tspd) 50 ENABLE_FEAT_AMU := 2 51 ENABLE_FEAT_AMUv1p1 := 2 52 ENABLE_FEAT_HCX := 2 53 ENABLE_MPAM_FOR_LOWER_ELS := 2 54 ENABLE_FEAT_RNG := 2 55 ENABLE_FEAT_TWED := 2 56 ENABLE_FEAT_GCS := 2 57 ENABLE_FEAT_RAS := 2 58ifeq (${ARCH}, aarch64) 59ifneq (${SPD}, spmd) 60ifeq (${SPM_MM}, 0) 61ifeq (${ENABLE_RME}, 0) 62ifeq (${CTX_INCLUDE_FPREGS}, 0) 63 ENABLE_SME_FOR_NS := 2 64 ENABLE_SME2_FOR_NS := 2 65endif 66endif 67endif 68endif 69endif 70endif 71 72# enable unconditionally for all builds 73ifeq (${ARCH}, aarch64) 74ifeq (${ENABLE_RME},0) 75 ENABLE_BRBE_FOR_NS := 2 76endif 77endif 78ENABLE_TRBE_FOR_NS := 2 79ENABLE_SYS_REG_TRACE_FOR_NS := 2 80ENABLE_FEAT_CSV2_2 := 2 81ENABLE_FEAT_DIT := 2 82ENABLE_FEAT_PAN := 2 83ENABLE_FEAT_VHE := 2 84CTX_INCLUDE_NEVE_REGS := 2 85ENABLE_FEAT_SEL2 := 2 86ENABLE_TRF_FOR_NS := 2 87ENABLE_FEAT_ECV := 2 88ENABLE_FEAT_FGT := 2 89ENABLE_FEAT_TCR2 := 2 90ENABLE_FEAT_S2PIE := 2 91ENABLE_FEAT_S1PIE := 2 92ENABLE_FEAT_S2POE := 2 93ENABLE_FEAT_S1POE := 2 94endif 95 96# The FVP platform depends on this macro to build with correct GIC driver. 97$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 98 99# Pass FVP_CLUSTER_COUNT to the build system. 100$(eval $(call add_define,FVP_CLUSTER_COUNT)) 101 102# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 103$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 104 105# Pass FVP_MAX_PE_PER_CPU to the build system. 106$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 107 108# Pass FVP_GICR_REGION_PROTECTION to the build system. 109$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 110 111# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 112$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 113 114# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 115# choose the CCI driver , else the CCN driver 116ifeq ($(FVP_CLUSTER_COUNT), 0) 117$(error "Incorrect cluster count specified for FVP port") 118else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 119FVP_INTERCONNECT_DRIVER := FVP_CCI 120else 121FVP_INTERCONNECT_DRIVER := FVP_CCN 122endif 123 124$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 125 126# Choose the GIC sources depending upon the how the FVP will be invoked 127ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 128 129# The GIC model (GIC-600 or GIC-500) will be detected at runtime 130GICV3_SUPPORT_GIC600 := 1 131GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 132 133# Include GICv3 driver files 134include drivers/arm/gic/v3/gicv3.mk 135 136FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 137 plat/common/plat_gicv3.c \ 138 plat/arm/common/arm_gicv3.c 139 140 ifeq ($(filter 1,${RESET_TO_BL2} \ 141 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 142 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 143 endif 144 145else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 146 147# No GICv4 extension 148GIC_ENABLE_V4_EXTN := 0 149$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 150 151# Include GICv2 driver files 152include drivers/arm/gic/v2/gicv2.mk 153 154FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 155 plat/common/plat_gicv2.c \ 156 plat/arm/common/arm_gicv2.c 157 158FVP_DT_PREFIX := fvp-base-gicv2-psci 159else 160$(error "Incorrect GIC driver chosen on FVP port") 161endif 162 163ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 164FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 165else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 166FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 167 plat/arm/common/arm_ccn.c 168else 169$(error "Incorrect CCN driver chosen on FVP port") 170endif 171 172FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 173 plat/arm/board/fvp/fvp_security.c \ 174 plat/arm/common/arm_tzc400.c 175 176 177PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 178 -Iinclude/lib/psa 179 180 181PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 182 183FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 184 185ifeq (${ARCH}, aarch64) 186 187# select a different set of CPU files, depending on whether we compile for 188# hardware assisted coherency cores or not 189ifeq (${HW_ASSISTED_COHERENCY}, 0) 190# Cores used without DSU 191 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 192 lib/cpus/aarch64/cortex_a53.S \ 193 lib/cpus/aarch64/cortex_a57.S \ 194 lib/cpus/aarch64/cortex_a72.S \ 195 lib/cpus/aarch64/cortex_a73.S 196else 197# Cores used with DSU only 198 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 199 # AArch64-only cores 200 # TODO: add all cores to the appropriate lists 201 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 202 lib/cpus/aarch64/cortex_a65ae.S \ 203 lib/cpus/aarch64/cortex_a76.S \ 204 lib/cpus/aarch64/cortex_a76ae.S \ 205 lib/cpus/aarch64/cortex_a77.S \ 206 lib/cpus/aarch64/cortex_a78.S \ 207 lib/cpus/aarch64/cortex_a78_ae.S \ 208 lib/cpus/aarch64/cortex_a78c.S \ 209 lib/cpus/aarch64/cortex_a710.S \ 210 lib/cpus/aarch64/neoverse_n_common.S \ 211 lib/cpus/aarch64/neoverse_n1.S \ 212 lib/cpus/aarch64/neoverse_n2.S \ 213 lib/cpus/aarch64/neoverse_v1.S \ 214 lib/cpus/aarch64/neoverse_e1.S \ 215 lib/cpus/aarch64/cortex_x2.S 216 endif 217 # AArch64/AArch32 cores 218 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 219 lib/cpus/aarch64/cortex_a75.S 220endif 221 222else 223FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 224 lib/cpus/aarch32/cortex_a57.S 225endif 226 227BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 228 drivers/arm/sp805/sp805.c \ 229 drivers/delay_timer/delay_timer.c \ 230 drivers/io/io_semihosting.c \ 231 lib/semihosting/semihosting.c \ 232 lib/semihosting/${ARCH}/semihosting_call.S \ 233 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 234 plat/arm/board/fvp/fvp_bl1_setup.c \ 235 plat/arm/board/fvp/fvp_err.c \ 236 plat/arm/board/fvp/fvp_io_storage.c \ 237 ${FVP_CPU_LIBS} \ 238 ${FVP_INTERCONNECT_SOURCES} 239 240ifeq (${USE_SP804_TIMER},1) 241BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 242else 243BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 244endif 245 246 247BL2_SOURCES += drivers/arm/sp805/sp805.c \ 248 drivers/io/io_semihosting.c \ 249 lib/utils/mem_region.c \ 250 lib/semihosting/semihosting.c \ 251 lib/semihosting/${ARCH}/semihosting_call.S \ 252 plat/arm/board/fvp/fvp_bl2_setup.c \ 253 plat/arm/board/fvp/fvp_err.c \ 254 plat/arm/board/fvp/fvp_io_storage.c \ 255 plat/arm/common/arm_nor_psci_mem_protect.c \ 256 ${FVP_SECURITY_SOURCES} 257 258 259ifeq (${COT_DESC_IN_DTB},1) 260BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 261endif 262 263ifeq (${ENABLE_RME},1) 264BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 265 266BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 267 plat/arm/board/fvp/fvp_realm_attest_key.c 268 269# FVP platform does not support RSS, but it can leverage RSS APIs to 270# provide hardcoded token/key on request. 271BL31_SOURCES += lib/psa/delegated_attestation.c 272 273endif 274 275ifeq (${ENABLE_FEAT_RNG_TRAP},1) 276BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 277endif 278 279ifeq (${RESET_TO_BL2},1) 280BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 281 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 282 ${FVP_CPU_LIBS} \ 283 ${FVP_INTERCONNECT_SOURCES} 284endif 285 286ifeq (${USE_SP804_TIMER},1) 287BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 288endif 289 290BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 291 ${FVP_SECURITY_SOURCES} 292 293ifeq (${USE_SP804_TIMER},1) 294BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 295endif 296 297BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 298 drivers/arm/smmu/smmu_v3.c \ 299 drivers/delay_timer/delay_timer.c \ 300 drivers/cfi/v2m/v2m_flash.c \ 301 lib/utils/mem_region.c \ 302 plat/arm/board/fvp/fvp_bl31_setup.c \ 303 plat/arm/board/fvp/fvp_console.c \ 304 plat/arm/board/fvp/fvp_pm.c \ 305 plat/arm/board/fvp/fvp_topology.c \ 306 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 307 plat/arm/common/arm_nor_psci_mem_protect.c \ 308 ${FVP_CPU_LIBS} \ 309 ${FVP_GIC_SOURCES} \ 310 ${FVP_INTERCONNECT_SOURCES} \ 311 ${FVP_SECURITY_SOURCES} 312 313# Support for fconf in BL31 314# Added separately from the above list for better readability 315ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 316BL31_SOURCES += lib/fconf/fconf.c \ 317 lib/fconf/fconf_dyn_cfg_getter.c \ 318 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 319 320BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 321 322ifeq (${SEC_INT_DESC_IN_FCONF},1) 323BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 324endif 325 326endif 327 328ifeq (${USE_SP804_TIMER},1) 329BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 330else 331BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 332endif 333 334# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 335ifdef UNIX_MK 336FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 337FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 338 ${PLAT}_fw_config.dts \ 339 ${PLAT}_tb_fw_config.dts \ 340 ${PLAT}_soc_fw_config.dts \ 341 ${PLAT}_nt_fw_config.dts \ 342 ) 343 344FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 345FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 346FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 347FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 348 349ifeq (${SPD},tspd) 350FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 351FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 352 353# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 354$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 355endif 356 357ifeq (${SPD},spmd) 358 359ifeq ($(ARM_SPMC_MANIFEST_DTS),) 360ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 361endif 362 363FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 364FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 365 366# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 367$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 368endif 369 370# Add the FW_CONFIG to FIP and specify the same to certtool 371$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 372# Add the TB_FW_CONFIG to FIP and specify the same to certtool 373$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 374# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 375$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 376# Add the NT_FW_CONFIG to FIP and specify the same to certtool 377$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 378 379FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 380$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 381 382# Add the HW_CONFIG to FIP and specify the same to certtool 383$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 384endif 385 386# Enable dynamic mitigation support by default 387DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 388 389ifneq (${ENABLE_FEAT_AMU},0) 390BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 391 lib/cpus/aarch64/cpuamu_helpers.S 392 393ifeq (${HW_ASSISTED_COHERENCY}, 1) 394BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 395 lib/cpus/aarch64/neoverse_n1_pubsub.c 396endif 397endif 398 399ifeq (${RAS_FFH_SUPPORT},1) 400BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 401endif 402 403ifneq (${ENABLE_STACK_PROTECTOR},0) 404PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 405endif 406 407ifeq (${ARCH},aarch32) 408 NEED_BL32 := yes 409endif 410 411# Enable the dynamic translation tables library. 412ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 413 ifeq (${ARCH},aarch32) 414 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 415 else # AArch64 416 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 417 endif 418endif 419 420ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 421 ifeq (${ARCH},aarch32) 422 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 423 else # AArch64 424 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 425 ifeq (${SPD},tspd) 426 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 427 endif 428 endif 429endif 430 431ifeq (${USE_DEBUGFS},1) 432 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 433endif 434 435# Add support for platform supplied linker script for BL31 build 436$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 437 438ifneq (${RESET_TO_BL2}, 0) 439 override BL1_SOURCES = 440endif 441 442# RSS is not supported on FVP right now. Thus, we use the mocked version 443# of the provided PSA APIs. They return with success and hard-coded token/key. 444PLAT_RSS_NOT_SUPPORTED := 1 445 446# Include Measured Boot makefile before any Crypto library makefile. 447# Crypto library makefile may need default definitions of Measured Boot build 448# flags present in Measured Boot makefile. 449ifeq (${MEASURED_BOOT},1) 450 RSS_MEASURED_BOOT_MK := drivers/measured_boot/rss/rss_measured_boot.mk 451 $(info Including ${RSS_MEASURED_BOOT_MK}) 452 include ${RSS_MEASURED_BOOT_MK} 453 454 ifneq (${MBOOT_RSS_HASH_ALG}, sha256) 455 $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) 456 endif 457 458 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} 459 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} 460endif 461 462include plat/arm/board/common/board_common.mk 463include plat/arm/common/arm_common.mk 464 465ifeq (${MEASURED_BOOT},1) 466BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 467 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 468 lib/psa/measured_boot.c 469 470BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 471 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 472 lib/psa/measured_boot.c 473 474# Even though RSS is not supported on FVP (see above), we support overriding 475# PLAT_RSS_NOT_SUPPORTED from the command line, just for the purpose of building 476# the code to detect any build regressions. The resulting firmware will not be 477# functional. 478ifneq (${PLAT_RSS_NOT_SUPPORTED},1) 479 $(warning "RSS is not supported on FVP. The firmware will not be functional.") 480 include drivers/arm/rss/rss_comms.mk 481 BL1_SOURCES += ${RSS_COMMS_SOURCES} 482 BL2_SOURCES += ${RSS_COMMS_SOURCES} 483 BL31_SOURCES += ${RSS_COMMS_SOURCES} 484 485 BL1_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 486 BL2_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 487 BL31_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 488endif 489 490endif 491 492ifeq (${DRTM_SUPPORT}, 1) 493BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 494 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 495 plat/arm/board/fvp/fvp_drtm_err.c \ 496 plat/arm/board/fvp/fvp_drtm_measurement.c \ 497 plat/arm/board/fvp/fvp_drtm_stub.c \ 498 plat/arm/common/arm_dyn_cfg.c \ 499 plat/arm/board/fvp/fvp_err.c 500endif 501 502ifeq (${TRUSTED_BOARD_BOOT}, 1) 503BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 504BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 505 506# FVP being a development platform, enable capability to disable Authentication 507# dynamically if TRUSTED_BOARD_BOOT is set. 508DYN_DISABLE_AUTH := 1 509endif 510 511ifeq (${SPMC_AT_EL3}, 1) 512PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 513endif 514 515PSCI_OS_INIT_MODE := 1 516 517ifeq (${SPD},spmd) 518BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 519endif 520 521# Test specific macros, keep them at bottom of this file 522$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 523ifeq (${PLATFORM_TEST_EA_FFH}, 1) 524 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 525 $(error "PLATFORM_TEST_EA_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 526 endif 527BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 528endif 529 530$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 531ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 532 ifeq (${RAS_EXTENSION}, 0) 533 $(error "PLATFORM_TEST_RAS_FFH expects RAS_EXTENSION to be 1") 534 endif 535endif 536 537ifeq (${ERRATA_ABI_SUPPORT}, 1) 538include plat/arm/board/fvp/fvp_cpu_errata.mk 539endif 540