feat(imx8mn): add workaround for errata ERR050362

Port the workaround from the downstream imx-atf [1]:

| commit 1990081264f40822d1564f4562f05bbbc0c2941b
| Author: Ji Luo <ji.luo@nxp.com>
| Date:

feat(imx8mn): add workaround for errata ERR050362

Port the workaround from the downstream imx-atf [1]:

| commit 1990081264f40822d1564f4562f05bbbc0c2941b
| Author: Ji Luo <ji.luo@nxp.com>
| Date: Thu May 20 16:26:55 2021 +0800
|
| MA-19071 imx8mn: workaround for errata ERR050362
|
| Configure the force_incr programmable bit in GPV_5 of PL301_display,
| which fixes partial write issue. This workaround was done in MCU FW
| before, move it to TF-A now as MCU should not touch secure world.
|
| Change-Id: I2e5bbc764640afeab6ac2f4b202939b59bd3b3f2
| Signed-off-by: Ji Luo <ji.luo@nxp.com>

[1] https://github.com/nxp-imx/imx-atf.git

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: Iaff5f1faa143204d64c075b288f8dd13eb2902d8

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feat(imx8m): enable snvs privileged registers access

Allow non-privileged access to all SNVS registers in case of no TEE is
available.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-I

feat(imx8m): enable snvs privileged registers access

Allow non-privileged access to all SNVS registers in case of no TEE is
available.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I44686a3639a68c72c7eacc80691c294d5c32c9ae

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Merge "feat(imx8m): move the gpc reg & macro to a separate header file" into integration

feat(imx8m): move the gpc reg & macro to a separate header file

move the gpc reg offset, bit define & macro to a separate header
file for code reuse.

This fixes suspend to mem on i.MX8M Plus too, s

feat(imx8m): move the gpc reg & macro to a separate header file

move the gpc reg offset, bit define & macro to a separate header
file for code reuse.

This fixes suspend to mem on i.MX8M Plus too, since the register
layout is different there.

Change-Id: Ibec60c3a68ffa8c378de5334577a7b0e463ca875
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Upgrade to latest, update commit message

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feat(imx8m): add more dram pll setting

Add DRAM PLL frequency setting for 3732mts & 3733mts.

Change-Id: I74feab2185376bbb84826d7ee79b5e25cbc4d263
Signed-off-by: Marek Vasut <marex@denx.de>

Merge changes from topic "mb/mb-signer-id" into integration

* changes:
feat(qemu): add dummy plat_mboot_measure_key() function
docs(rss): update RSS doc for signer-ID
feat(imx): add dummy 'pla

Merge changes from topic "mb/mb-signer-id" into integration

* changes:
feat(qemu): add dummy plat_mboot_measure_key() function
docs(rss): update RSS doc for signer-ID
feat(imx): add dummy 'plat_mboot_measure_key' function
feat(tc): implement platform function to measure and publish Public Key
feat(auth): measure and publicise the Public Key
feat(fvp): implement platform function to measure and publish Public Key
feat(fvp): add public key-OID information in RSS metadata structure
feat(auth): add explicit entries for key OIDs
feat(rss): set the signer-ID in the RSS metadata
feat(auth): create a zero-OID for Subject Public Key
docs: add details about plat_mboot_measure_key function
feat(measured-boot): introduce platform function to measure and publish Public Key

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fix(imx8m): make IMX_BOOT_UART_BASE autodetection option more obvious

Switch from IMX_BOOT_UART_BASE=0 to IMX_BOOT_UART_BASE=auto to make it
more obvious that the detection is based on the runtime a

fix(imx8m): make IMX_BOOT_UART_BASE autodetection option more obvious

Switch from IMX_BOOT_UART_BASE=0 to IMX_BOOT_UART_BASE=auto to make it
more obvious that the detection is based on the runtime autodetection.

In addition this moves the evaluation of IMX_BOOT_UART_BASE into the
makefile which removes the ugly conditional compilation as well.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I92c13607bf81c6267f4b6aee829d74902b7f72d2

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feat(imx): add dummy 'plat_mboot_measure_key' function

Added dummy implementation of 'plat_mboot_measure_key'
function for IMX platform.

Change-Id: Ib41fd86a9da330f62561707bda7d16f2825c0a7f
Signed-

feat(imx): add dummy 'plat_mboot_measure_key' function

Added dummy implementation of 'plat_mboot_measure_key'
function for IMX platform.

Change-Id: Ib41fd86a9da330f62561707bda7d16f2825c0a7f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(imx8m): detect console base address during runtime

Provide a helper to detect the enabled UART device during runtime. This
lower the integration effort and make it more straight forward for
'si

feat(imx8m): detect console base address during runtime

Provide a helper to detect the enabled UART device during runtime. This
lower the integration effort and make it more straight forward for
'simple' use-cases with a single UART enabled. If multiple UARTs are
enabled the first enabled is returned.

The auto-detection is enabled by setting IMX_BOOT_UART_BASE=0 to keep
the backward compatibility. For more advanced use-cases (multiple UARTs
are enabled) the user still has to provide the correct base address.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I300a167e1a10f9aa991c8d1c3efe2c6b23f56c47

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fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373

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fix(imx8mq): fix compilation with gcc >= 12.x

Starting with GCC >= 12.x the -Wall option includes -Werror=array-bounds
checks. Per default GCC treats all memory accesses below 4096 as NULL,
so acces

fix(imx8mq): fix compilation with gcc >= 12.x

Starting with GCC >= 12.x the -Wall option includes -Werror=array-bounds
checks. Per default GCC treats all memory accesses below 4096 as NULL,
so access to ROMAPI causes the following warning:

------------
In file included from plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:20:
In function 'mmio_read_8',
inlined from 'imx8mq_soc_info_init' at plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:70:16,
inlined from 'bl31_platform_setup' at plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:206:2:
include/lib/mmio.h:19:16: error: array subscript 0 is outside array bounds of 'volatile uint8_t[0]' {aka 'volatile unsigned char[]'} [-Werror=array-bounds]
19 | return *(volatile uint8_t*)addr;
| ^~~~~~~~~~~~~~~~~~~~~~~~
In function 'mmio_read_8',
inlined from 'imx8mq_soc_info_init' at plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:74:16,
inlined from 'bl31_platform_setup' at plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:206:2:
include/lib/mmio.h:19:16: error: array subscript 0 is outside array bounds of 'volatile uint8_t[0]' {aka 'volatile unsigned char[]'} [-Werror=array-bounds]
19 | return *(volatile uint8_t*)addr;
| ^~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
------------

This comes arguably from us somewhat abusing pointers to access MMIO
memory regions, which is not really covered by the C language.

Replace the pointer-dereferencing mmio_read_8() with an implementation
that uses inline assembly, to directly generate an 8-bit load
instruction. This avoids the compiler thinking that this access is using
a pointer it needs to jealously look after.

Change-Id: Iab39f6f615d51d3e8a1c54a1262d1e6ec208811d
Reported-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3

BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is runnin

refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3

BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is running at EL3 exception level
These two scenarios are not exactly same even though first implicitly
means second to be true. To distinguish between these two use cases we
introduce new macros.
BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2.
Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where
BL2 runs at EL3 (including four world systems).

BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the
repository.

Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>

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feat(imx8mq): enable dram dvfs support on imx8mq

Enable DRAM DVFS support on i.MX8MQ.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Id72c5eb9625936052ec51e5a52d9d31175ed1b1b

feat(imx8m): use non-fast wakeup stop mode for system suspend

Use non-fast wakeup stop mode for system suspend support, so
the SOC can enter DSM mode by default.

Signed-off-by: Jacky Bai <ping.bai@

feat(imx8m): use non-fast wakeup stop mode for system suspend

Use non-fast wakeup stop mode for system suspend support, so
the SOC can enter DSM mode by default.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I37828d4e66ee2ebd48e7adca054b93c520cb2c82

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feat(imx8mq): correct the slot ack setting for STOP mode

A53 core's power up ack need to be used when system resume
from DSM mode.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I47fb33c058

feat(imx8mq): correct the slot ack setting for STOP mode

A53 core's power up ack need to be used when system resume
from DSM mode.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I47fb33c0582ae5f483ffaa887f95e27bd47875f7

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feat(imx8mq): add anamix pll override setting for DSM mode

Add the anamix PLL override setting for DSM mode support,
so that the PLL can be power down in DSM mode to save power.

Signed-off-by: Jack

feat(imx8mq): add anamix pll override setting for DSM mode

Add the anamix PLL override setting for DSM mode support,
so that the PLL can be power down in DSM mode to save power.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ibe954bc7c4a7b453ace13f8e4b6a335e6d4856c3

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feat(imx8mq): add workaround code for ERR11171 on imx8mq

This new workaround takes advantage of the per core IMR
registers in GPC in order to unmask the IRQ0, still generated
by the 12bit in IOMUX_G

feat(imx8mq): add workaround code for ERR11171 on imx8mq

This new workaround takes advantage of the per core IMR
registers in GPC in order to unmask the IRQ0, still generated
by the 12bit in IOMUX_GPR register (which now remains always set),
so it can only wake up one core at the time.Also, this entire
workaround has now been moved here in TF-A, allowing the kernel
side to be minimal.

Another advantage this workaround brings is the removal of the
50us delay (which was necessary before in gic_raise_softirq in
kernel) by allowing the core that is waking up to mask his own
IRQ0 in the suspend finish callback.

One important change here is the way the cores are woken up in
dram_dvfs_handler. Since the wake up mechanism has changed from
asserting the 12th bit in IOMUX_GPR and leaving the IMR1 1st bit
on for each core to exactly the reverse, that is, leaving the
IOMUX_GPR 12th bit always set and then masking/unmasking the IMR1
1st bit for each independent core, we need to use the imx_gpc_core_wake
to wake up the cores.

Also, the 50us udelay is moved to TF-A (inside imx_pwr_domain_off)
from kernel(gic_raise_softirq), since the new cpuidle workaround
does not need it in order to clean the IOMUX_GPC 12bit. For now,
the udelay seems to be still needed in order to delay the affinity
info OFF for the dying core. This is something that needs further
investigation.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I9f17ff6fc3452b8225a50b232964712aafeab78a

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feat(imx8mq): add the dram retention support for imx8mq

Add the dram retention support for i.MX8MQ. As there is
no enough ocram space available before entering TF-A,
so the timing info need to be co

feat(imx8mq): add the dram retention support for imx8mq

Add the dram retention support for i.MX8MQ. As there is
no enough ocram space available before entering TF-A,
so the timing info need to be copied from dram into ocram.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Id8264c342fd62e297b1969cba5ed505450c78a25

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feat(imx8mq): add version for B2

iMX8MQ B2 chip uses same OCOTP magic value with B1. So
read the ROM version to distinguish it with B1.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <

feat(imx8mq): add version for B2

iMX8MQ B2 chip uses same OCOTP magic value with B1. So
read the ROM version to distinguish it with B1.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3e6865922deeb66816a0dddb49d986405e802b6f

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fix(imx8m): backup mr12/14 value from lpddr4 chip

Backup the mr12/14 value as the actual value used is not the
one we configured in the ddrc config timing.

Signed-off-by: Jacky Bai <ping.bai@nxp.co

fix(imx8m): backup mr12/14 value from lpddr4 chip

Backup the mr12/14 value as the actual value used is not the
one we configured in the ddrc config timing.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: If04733b34a3b4c080828bb7c82e83f0badbeaafd

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fix(imx8m): add ddr4 dvfs sw workaround for ERR050712

APB Write data corruption following MRCTRL0.mr_wr=1 while
hardware-driven MR access is occurring

When performing a software driven MR access, t

fix(imx8m): add ddr4 dvfs sw workaround for ERR050712

APB Write data corruption following MRCTRL0.mr_wr=1 while
hardware-driven MR access is occurring

When performing a software driven MR access, the following
sequence must be done automatically before performing other
APB register accesses:

1. Set MRCTRL0.mr_wr=1
2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2)
3. Check for MRSTAT.mr_wr_busy=0 again (for the second time),
if not, go to step (2).

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ie26e08bcc83d3ed4844ed04a853162308dcdccd0

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fix(imx8m): fix coverity out of bound access issue

Fix the out of bound access to the rank setting array.

Fix Coverity issue:

CID 6474575: Out-of-bounds access (OVERRUN)
CID 11014855: Unused value

fix(imx8m): fix coverity out of bound access issue

Fix the out of bound access to the rank setting array.

Fix Coverity issue:

CID 6474575: Out-of-bounds access (OVERRUN)
CID 11014855: Unused value (UNUSED_VALUE)

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I5d9ef90f1479e5d46d1b6c8693a27e3abd614766

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fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0

It seems the DRAM APB clock root slice can NOT work normally
if the PLLs is power down in DSM mode. So update this clock
slice's

fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0

It seems the DRAM APB clock root slice can NOT work normally
if the PLLs is power down in DSM mode. So update this clock
slice's setting explicitly to make it work. This piece of code
is there for a long while on previous release, so just add
it back to align with previous flow.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Change-Id: I113069494074194e116fdb1229052d2956bf90ea

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feat(imx8m): add more dram pll setting

Add DRAM PLL frequency setting for 3200mts & 4000mts.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: I4

feat(imx8m): add more dram pll setting

Add DRAM PLL frequency setting for 3200mts & 4000mts.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: I4b0609f9e7c0f35d75a26ec9ccebec77b3dbe68f

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fix(imx8m): fix the current fsp init

The dfimisc reg value should be shift right 8 bit to
get the current fsp.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.

fix(imx8m): fix the current fsp init

The dfimisc reg value should be shift right 8 bit to
get the current fsp.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Change-Id: I4c8c166bc3ad4cc1376961cbf47631c68b5900cc

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