1 /* 2 * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <plat/common/platform.h> 23 24 #include <gpc.h> 25 #include <imx_aipstz.h> 26 #include <imx_uart.h> 27 #include <imx8m_caam.h> 28 #include <plat_imx8.h> 29 30 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 31 32 static const mmap_region_t imx_mmap[] = { 33 MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */ 34 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM map */ 35 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 36 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */ 37 {0}, 38 }; 39 40 static const struct aipstz_cfg aipstz[] = { 41 {AIPSTZ1_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 42 {AIPSTZ2_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 43 {AIPSTZ3_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 44 {AIPSTZ4_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 45 {0}, 46 }; 47 48 static entry_point_info_t bl32_image_ep_info; 49 static entry_point_info_t bl33_image_ep_info; 50 51 static uint32_t imx_soc_revision; 52 53 int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, 54 u_register_t x3) 55 { 56 return imx_soc_revision; 57 } 58 59 #define ANAMIX_DIGPROG 0x6c 60 #define ROM_SOC_INFO_A0 0x800 61 #define ROM_SOC_INFO_B0 0x83C 62 #define OCOTP_SOC_INFO_B1 0x40 63 64 static void imx8mq_soc_info_init(void) 65 { 66 uint32_t rom_version; 67 uint32_t ocotp_val; 68 69 imx_soc_revision = mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_DIGPROG); 70 rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_A0); 71 if (rom_version == 0x10) 72 return; 73 74 rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_B0); 75 if (rom_version == 0x20) { 76 imx_soc_revision &= ~0xff; 77 imx_soc_revision |= rom_version; 78 return; 79 } 80 81 /* 0xff0055aa is magic number for B1 */ 82 ocotp_val = mmio_read_32(IMX_OCOTP_BASE + OCOTP_SOC_INFO_B1); 83 if (ocotp_val == 0xff0055aa) { 84 imx_soc_revision &= ~0xff; 85 if (rom_version == 0x22) { 86 imx_soc_revision |= 0x22; 87 } else { 88 imx_soc_revision |= 0x21; 89 } 90 return; 91 } 92 } 93 94 /* get SPSR for BL33 entry */ 95 static uint32_t get_spsr_for_bl33_entry(void) 96 { 97 unsigned long el_status; 98 unsigned long mode; 99 uint32_t spsr; 100 101 /* figure out what mode we enter the non-secure world */ 102 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 103 el_status &= ID_AA64PFR0_ELX_MASK; 104 105 mode = (el_status) ? MODE_EL2 : MODE_EL1; 106 107 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 108 return spsr; 109 } 110 111 static void bl31_tz380_setup(void) 112 { 113 unsigned int val; 114 115 val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10); 116 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 117 return; 118 119 tzc380_init(IMX_TZASC_BASE); 120 /* 121 * Need to substact offset 0x40000000 from CPU address when 122 * programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW 123 */ 124 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 125 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 126 } 127 128 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 129 u_register_t arg2, u_register_t arg3) 130 { 131 static console_t console; 132 int i; 133 /* enable CSU NS access permission */ 134 for (i = 0; i < 64; i++) { 135 mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff); 136 } 137 138 imx_aipstz_init(aipstz); 139 140 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 141 IMX_CONSOLE_BAUDRATE, &console); 142 /* This console is only used for boot stage */ 143 console_set_scope(&console, CONSOLE_FLAG_BOOT); 144 145 imx8m_caam_init(); 146 147 /* 148 * tell BL3-1 where the non-secure software image is located 149 * and the entry state information. 150 */ 151 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 152 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 153 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 154 155 #if defined(SPD_opteed) || defined(SPD_trusty) 156 /* Populate entry point information for BL32 */ 157 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 158 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 159 bl32_image_ep_info.pc = BL32_BASE; 160 bl32_image_ep_info.spsr = 0; 161 162 /* Pass TEE base and size to bl33 */ 163 bl33_image_ep_info.args.arg1 = BL32_BASE; 164 bl33_image_ep_info.args.arg2 = BL32_SIZE; 165 166 #ifdef SPD_trusty 167 bl32_image_ep_info.args.arg0 = BL32_SIZE; 168 bl32_image_ep_info.args.arg1 = BL32_BASE; 169 #else 170 /* Make sure memory is clean */ 171 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 172 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 173 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 174 #endif 175 #endif 176 177 bl31_tz380_setup(); 178 } 179 180 void bl31_plat_arch_setup(void) 181 { 182 const mmap_region_t bl_regions[] = { 183 MAP_REGION_FLAT(BL31_START, BL31_SIZE, 184 MT_MEMORY | MT_RW | MT_SECURE), 185 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 186 MT_MEMORY | MT_RO | MT_SECURE), 187 #if USE_COHERENT_MEM 188 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 189 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 190 MT_DEVICE | MT_RW | MT_SECURE), 191 #endif 192 /* Map TEE memory */ 193 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW), 194 {0}, 195 }; 196 197 setup_page_tables(bl_regions, imx_mmap); 198 /* enable the MMU */ 199 enable_mmu_el3(0); 200 } 201 202 void bl31_platform_setup(void) 203 { 204 generic_delay_timer_init(); 205 206 /* init the GICv3 cpu and distributor interface */ 207 plat_gic_driver_init(); 208 plat_gic_init(); 209 210 /* determine SOC revision for erratas */ 211 imx8mq_soc_info_init(); 212 213 /* gpc init */ 214 imx_gpc_init(); 215 } 216 217 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 218 { 219 if (type == NON_SECURE) 220 return &bl33_image_ep_info; 221 if (type == SECURE) 222 return &bl32_image_ep_info; 223 224 return NULL; 225 } 226 227 unsigned int plat_get_syscnt_freq2(void) 228 { 229 return COUNTER_FREQUENCY; 230 } 231 232 #ifdef SPD_trusty 233 void plat_trusty_set_boot_args(aapcs64_params_t *args) 234 { 235 args->arg0 = BL32_SIZE; 236 args->arg1 = BL32_BASE; 237 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 238 } 239 #endif 240