1# 2# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's 32# progbits limit. We need a way to build all useful configurations while waiting 33# on the fvp to increase its SRAM size. The problem is twofild: 34# 1. the cleanup that introduced these enables cleaned up tf-a a little too 35# well and things that previously (incorrectly) were enabled, no longer are. 36# A bunch of CI configs build subtly incorrectly and this combo makes it 37# necessary to forcefully and unconditionally enable them here. 38# 2. the progbits limit is exceeded only when the tsp is involved. However, 39# there are tsp CI configs that run on very high architecture revisions so 40# disabling everything isn't an option. 41# The fix is to enable everything, as before. When the tsp is included, though, 42# we need to slim the size down. In that case, disable all optional features, 43# that will not be present in CI when the tsp is. 44# Similarly, DRTM support is only tested on v8.0 models. Disable everything just 45# for it. 46# TODO: make all of this unconditional (or only base the condition on 47# ARM_ARCH_* when the makefile supports it). 48ifneq (${DRTM_SUPPORT}, 1) 49ifneq (${SPD}, tspd) 50 ENABLE_FEAT_AMU := 2 51 ENABLE_FEAT_AMUv1p1 := 2 52 ENABLE_FEAT_HCX := 2 53 ENABLE_MPAM_FOR_LOWER_ELS := 2 54 ENABLE_FEAT_RNG := 2 55 ENABLE_FEAT_TWED := 2 56 ENABLE_FEAT_GCS := 2 57 ENABLE_FEAT_RAS := 2 58ifeq (${ARCH}, aarch64) 59ifneq (${SPD}, spmd) 60ifeq (${SPM_MM}, 0) 61ifeq (${ENABLE_RME}, 0) 62ifeq (${CTX_INCLUDE_FPREGS}, 0) 63 ENABLE_SME_FOR_NS := 2 64 ENABLE_SME2_FOR_NS := 2 65endif 66endif 67endif 68endif 69endif 70endif 71 72# enable unconditionally for all builds 73ifeq (${ARCH}, aarch64) 74ifeq (${ENABLE_RME},0) 75 ENABLE_BRBE_FOR_NS := 2 76endif 77endif 78ENABLE_TRBE_FOR_NS := 2 79ENABLE_SYS_REG_TRACE_FOR_NS := 2 80ENABLE_FEAT_CSV2_2 := 2 81ENABLE_FEAT_DIT := 2 82ENABLE_FEAT_PAN := 2 83ENABLE_FEAT_MTE_PERM := 2 84ENABLE_FEAT_VHE := 2 85CTX_INCLUDE_NEVE_REGS := 2 86ENABLE_FEAT_SEL2 := 2 87ENABLE_TRF_FOR_NS := 2 88ENABLE_FEAT_ECV := 2 89ENABLE_FEAT_FGT := 2 90ENABLE_FEAT_TCR2 := 2 91ENABLE_FEAT_S2PIE := 2 92ENABLE_FEAT_S1PIE := 2 93ENABLE_FEAT_S2POE := 2 94ENABLE_FEAT_S1POE := 2 95endif 96 97# The FVP platform depends on this macro to build with correct GIC driver. 98$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 99 100# Pass FVP_CLUSTER_COUNT to the build system. 101$(eval $(call add_define,FVP_CLUSTER_COUNT)) 102 103# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 104$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 105 106# Pass FVP_MAX_PE_PER_CPU to the build system. 107$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 108 109# Pass FVP_GICR_REGION_PROTECTION to the build system. 110$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 111 112# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 113$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 114 115# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 116# choose the CCI driver , else the CCN driver 117ifeq ($(FVP_CLUSTER_COUNT), 0) 118$(error "Incorrect cluster count specified for FVP port") 119else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 120FVP_INTERCONNECT_DRIVER := FVP_CCI 121else 122FVP_INTERCONNECT_DRIVER := FVP_CCN 123endif 124 125$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 126 127# Choose the GIC sources depending upon the how the FVP will be invoked 128ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 129 130# The GIC model (GIC-600 or GIC-500) will be detected at runtime 131GICV3_SUPPORT_GIC600 := 1 132GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 133 134# Include GICv3 driver files 135include drivers/arm/gic/v3/gicv3.mk 136 137FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 138 plat/common/plat_gicv3.c \ 139 plat/arm/common/arm_gicv3.c 140 141 ifeq ($(filter 1,${RESET_TO_BL2} \ 142 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 143 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 144 endif 145 146else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 147 148# No GICv4 extension 149GIC_ENABLE_V4_EXTN := 0 150$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 151 152# Include GICv2 driver files 153include drivers/arm/gic/v2/gicv2.mk 154 155FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 156 plat/common/plat_gicv2.c \ 157 plat/arm/common/arm_gicv2.c 158 159FVP_DT_PREFIX := fvp-base-gicv2-psci 160else 161$(error "Incorrect GIC driver chosen on FVP port") 162endif 163 164ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 165FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 166else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 167FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 168 plat/arm/common/arm_ccn.c 169else 170$(error "Incorrect CCN driver chosen on FVP port") 171endif 172 173FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 174 plat/arm/board/fvp/fvp_security.c \ 175 plat/arm/common/arm_tzc400.c 176 177 178PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 179 -Iinclude/lib/psa 180 181 182PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 183 184FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 185 186ifeq (${ARCH}, aarch64) 187 188# select a different set of CPU files, depending on whether we compile for 189# hardware assisted coherency cores or not 190ifeq (${HW_ASSISTED_COHERENCY}, 0) 191# Cores used without DSU 192 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 193 lib/cpus/aarch64/cortex_a53.S \ 194 lib/cpus/aarch64/cortex_a57.S \ 195 lib/cpus/aarch64/cortex_a72.S \ 196 lib/cpus/aarch64/cortex_a73.S 197else 198# Cores used with DSU only 199 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 200 # AArch64-only cores 201 # TODO: add all cores to the appropriate lists 202 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 203 lib/cpus/aarch64/cortex_a65ae.S \ 204 lib/cpus/aarch64/cortex_a76.S \ 205 lib/cpus/aarch64/cortex_a76ae.S \ 206 lib/cpus/aarch64/cortex_a77.S \ 207 lib/cpus/aarch64/cortex_a78.S \ 208 lib/cpus/aarch64/cortex_a78_ae.S \ 209 lib/cpus/aarch64/cortex_a78c.S \ 210 lib/cpus/aarch64/cortex_a710.S \ 211 lib/cpus/aarch64/neoverse_n_common.S \ 212 lib/cpus/aarch64/neoverse_n1.S \ 213 lib/cpus/aarch64/neoverse_n2.S \ 214 lib/cpus/aarch64/neoverse_v1.S \ 215 lib/cpus/aarch64/neoverse_e1.S \ 216 lib/cpus/aarch64/cortex_x2.S \ 217 lib/cpus/aarch64/cortex_gelas.S 218 endif 219 # AArch64/AArch32 cores 220 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 221 lib/cpus/aarch64/cortex_a75.S 222endif 223 224else 225FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 226 lib/cpus/aarch32/cortex_a57.S \ 227 lib/cpus/aarch32/cortex_a53.S 228endif 229 230BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 231 drivers/arm/sp805/sp805.c \ 232 drivers/delay_timer/delay_timer.c \ 233 drivers/io/io_semihosting.c \ 234 lib/semihosting/semihosting.c \ 235 lib/semihosting/${ARCH}/semihosting_call.S \ 236 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 237 plat/arm/board/fvp/fvp_bl1_setup.c \ 238 plat/arm/board/fvp/fvp_err.c \ 239 plat/arm/board/fvp/fvp_io_storage.c \ 240 ${FVP_CPU_LIBS} \ 241 ${FVP_INTERCONNECT_SOURCES} 242 243ifeq (${USE_SP804_TIMER},1) 244BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 245else 246BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 247endif 248 249 250BL2_SOURCES += drivers/arm/sp805/sp805.c \ 251 drivers/io/io_semihosting.c \ 252 lib/utils/mem_region.c \ 253 lib/semihosting/semihosting.c \ 254 lib/semihosting/${ARCH}/semihosting_call.S \ 255 plat/arm/board/fvp/fvp_bl2_setup.c \ 256 plat/arm/board/fvp/fvp_err.c \ 257 plat/arm/board/fvp/fvp_io_storage.c \ 258 plat/arm/common/arm_nor_psci_mem_protect.c \ 259 ${FVP_SECURITY_SOURCES} 260 261 262ifeq (${COT_DESC_IN_DTB},1) 263BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 264endif 265 266ifeq (${ENABLE_RME},1) 267BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 268 269BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 270 plat/arm/board/fvp/fvp_realm_attest_key.c 271 272# FVP platform does not support RSS, but it can leverage RSS APIs to 273# provide hardcoded token/key on request. 274BL31_SOURCES += lib/psa/delegated_attestation.c 275 276endif 277 278ifeq (${ENABLE_FEAT_RNG_TRAP},1) 279BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 280endif 281 282ifeq (${RESET_TO_BL2},1) 283BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 284 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 285 ${FVP_CPU_LIBS} \ 286 ${FVP_INTERCONNECT_SOURCES} 287endif 288 289ifeq (${USE_SP804_TIMER},1) 290BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 291endif 292 293BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 294 ${FVP_SECURITY_SOURCES} 295 296ifeq (${USE_SP804_TIMER},1) 297BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 298endif 299 300BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 301 drivers/arm/smmu/smmu_v3.c \ 302 drivers/delay_timer/delay_timer.c \ 303 drivers/cfi/v2m/v2m_flash.c \ 304 lib/utils/mem_region.c \ 305 plat/arm/board/fvp/fvp_bl31_setup.c \ 306 plat/arm/board/fvp/fvp_console.c \ 307 plat/arm/board/fvp/fvp_pm.c \ 308 plat/arm/board/fvp/fvp_topology.c \ 309 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 310 plat/arm/common/arm_nor_psci_mem_protect.c \ 311 ${FVP_CPU_LIBS} \ 312 ${FVP_GIC_SOURCES} \ 313 ${FVP_INTERCONNECT_SOURCES} \ 314 ${FVP_SECURITY_SOURCES} 315 316# Support for fconf in BL31 317# Added separately from the above list for better readability 318ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 319BL31_SOURCES += lib/fconf/fconf.c \ 320 lib/fconf/fconf_dyn_cfg_getter.c \ 321 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 322 323BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 324 325ifeq (${SEC_INT_DESC_IN_FCONF},1) 326BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 327endif 328 329endif 330 331ifeq (${USE_SP804_TIMER},1) 332BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 333else 334BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 335endif 336 337# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 338ifdef UNIX_MK 339FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 340FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 341 ${PLAT}_fw_config.dts \ 342 ${PLAT}_tb_fw_config.dts \ 343 ${PLAT}_soc_fw_config.dts \ 344 ${PLAT}_nt_fw_config.dts \ 345 ) 346 347FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 348FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 349FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 350FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 351 352ifeq (${SPD},tspd) 353FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 354FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 355 356# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 357$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 358endif 359 360ifeq (${SPD},spmd) 361 362ifeq ($(ARM_SPMC_MANIFEST_DTS),) 363ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 364endif 365 366FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 367FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 368 369# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 370$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 371endif 372 373# Add the FW_CONFIG to FIP and specify the same to certtool 374$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 375# Add the TB_FW_CONFIG to FIP and specify the same to certtool 376$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 377# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 378$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 379# Add the NT_FW_CONFIG to FIP and specify the same to certtool 380$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 381 382FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 383$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 384 385# Add the HW_CONFIG to FIP and specify the same to certtool 386$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 387endif 388 389# Enable dynamic mitigation support by default 390DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 391 392ifneq (${ENABLE_FEAT_AMU},0) 393BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 394 lib/cpus/aarch64/cpuamu_helpers.S 395 396ifeq (${HW_ASSISTED_COHERENCY}, 1) 397BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 398 lib/cpus/aarch64/neoverse_n1_pubsub.c 399endif 400endif 401 402ifeq (${RAS_FFH_SUPPORT},1) 403BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 404endif 405 406ifneq (${ENABLE_STACK_PROTECTOR},0) 407PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 408endif 409 410# Enable the dynamic translation tables library. 411ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 412 ifeq (${ARCH},aarch32) 413 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 414 else # AArch64 415 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 416 endif 417endif 418 419ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 420 ifeq (${ARCH},aarch32) 421 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 422 else # AArch64 423 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 424 ifeq (${SPD},tspd) 425 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 426 endif 427 endif 428endif 429 430ifeq (${USE_DEBUGFS},1) 431 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 432endif 433 434# Add support for platform supplied linker script for BL31 build 435$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 436 437ifneq (${RESET_TO_BL2}, 0) 438 override BL1_SOURCES = 439endif 440 441# RSS is not supported on FVP right now. Thus, we use the mocked version 442# of the provided PSA APIs. They return with success and hard-coded token/key. 443PLAT_RSS_NOT_SUPPORTED := 1 444 445# Include Measured Boot makefile before any Crypto library makefile. 446# Crypto library makefile may need default definitions of Measured Boot build 447# flags present in Measured Boot makefile. 448ifeq (${MEASURED_BOOT},1) 449 RSS_MEASURED_BOOT_MK := drivers/measured_boot/rss/rss_measured_boot.mk 450 $(info Including ${RSS_MEASURED_BOOT_MK}) 451 include ${RSS_MEASURED_BOOT_MK} 452 453 ifneq (${MBOOT_RSS_HASH_ALG}, sha256) 454 $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) 455 endif 456 457 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} 458 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} 459endif 460 461include plat/arm/board/common/board_common.mk 462include plat/arm/common/arm_common.mk 463 464ifeq (${MEASURED_BOOT},1) 465BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 466 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 467 lib/psa/measured_boot.c 468 469BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 470 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 471 lib/psa/measured_boot.c 472 473# Even though RSS is not supported on FVP (see above), we support overriding 474# PLAT_RSS_NOT_SUPPORTED from the command line, just for the purpose of building 475# the code to detect any build regressions. The resulting firmware will not be 476# functional. 477ifneq (${PLAT_RSS_NOT_SUPPORTED},1) 478 $(warning "RSS is not supported on FVP. The firmware will not be functional.") 479 include drivers/arm/rss/rss_comms.mk 480 BL1_SOURCES += ${RSS_COMMS_SOURCES} 481 BL2_SOURCES += ${RSS_COMMS_SOURCES} 482 BL31_SOURCES += ${RSS_COMMS_SOURCES} 483 484 BL1_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 485 BL2_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 486 BL31_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 487endif 488 489endif 490 491ifeq (${DRTM_SUPPORT}, 1) 492BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 493 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 494 plat/arm/board/fvp/fvp_drtm_err.c \ 495 plat/arm/board/fvp/fvp_drtm_measurement.c \ 496 plat/arm/board/fvp/fvp_drtm_stub.c \ 497 plat/arm/common/arm_dyn_cfg.c \ 498 plat/arm/board/fvp/fvp_err.c 499endif 500 501ifeq (${TRUSTED_BOARD_BOOT}, 1) 502BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 503BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 504 505# FVP being a development platform, enable capability to disable Authentication 506# dynamically if TRUSTED_BOARD_BOOT is set. 507DYN_DISABLE_AUTH := 1 508endif 509 510ifeq (${SPMC_AT_EL3}, 1) 511PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 512endif 513 514PSCI_OS_INIT_MODE := 1 515 516ifeq (${SPD},spmd) 517BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 518endif 519 520# Test specific macros, keep them at bottom of this file 521$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 522ifeq (${PLATFORM_TEST_EA_FFH}, 1) 523 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 524 $(error "PLATFORM_TEST_EA_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 525 endif 526BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 527endif 528 529$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 530ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 531 ifeq (${RAS_EXTENSION}, 0) 532 $(error "PLATFORM_TEST_RAS_FFH expects RAS_EXTENSION to be 1") 533 endif 534endif 535 536ifeq (${ERRATA_ABI_SUPPORT}, 1) 537include plat/arm/board/fvp/fvp_cpu_errata.mk 538endif 539