build(libfdt): introduce include guards

In some build configurations the `libfdt.mk` file is included multiple
times. Due to the fact that rules cannot (or rather, should not) be
defined multiple ti

build(libfdt): introduce include guards

In some build configurations the `libfdt.mk` file is included multiple
times. Due to the fact that rules cannot (or rather, should not) be
defined multiple times, the `MAKE_LIB` function (which this makefile
calls) cannot be called twice with the same inputs. Doing so leads to
warnings about overridden rules, e.g.:

lib/libfdt/libfdt.mk:19: warning: overriding recipe for target libfdt'
lib/libfdt/libfdt.mk:19: warning: ignoring old recipe for target libfdt'
lib/libfdt/libfdt.mk:19: warning: overriding recipe for target libfdt/fdt.o'
lib/libfdt/libfdt.mk:19: warning: ignoring old recipe for target libfdt/fdt.o'
lib/libfdt/libfdt.mk:19: warning: overriding recipe for target libfdt/fdt_addresses.o'
lib/libfdt/libfdt.mk:19: warning: ignoring old recipe for target libfdt/fdt_addresses.o'
lib/libfdt/libfdt.mk:19: warning: overriding recipe for target libfdt/fdt_empty_tree.o'
lib/libfdt/libfdt.mk:19: warning: ignoring old recipe for target libfdt/fdt_empty_tree.o'
lib/libfdt/libfdt.mk:19: warning: overriding recipe for target libfdt/fdt_ro.o'
lib/libfdt/libfdt.mk:19: warning: ignoring old recipe for target libfdt/fdt_ro.o'
lib/libfdt/libfdt.mk:19: warning: overriding recipe for target libfdt/fdt_rw.o'
lib/libfdt/libfdt.mk:19: warning: ignoring old recipe for target libfdt/fdt_rw.o'
lib/libfdt/libfdt.mk:19: warning: overriding recipe for target libfdt/fdt_strerror.o'
lib/libfdt/libfdt.mk:19: warning: ignoring old recipe for target libfdt/fdt_strerror.o'
lib/libfdt/libfdt.mk:19: warning: overriding recipe for target libfdt/fdt_sw.o'
lib/libfdt/libfdt.mk:19: warning: ignoring old recipe for target libfdt/fdt_sw.o'
lib/libfdt/libfdt.mk:19: warning: overriding recipe for target libfdt/fdt_wip.o'
lib/libfdt/libfdt.mk:19: warning: ignoring old recipe for target libfdt/fdt_wip.o'
lib/libfdt/libfdt.mk:19: warning: overriding recipe for target lib/libfdt.a'
lib/libfdt/libfdt.mk:19: warning: ignoring old recipe for target lib/libfdt.a'

This change introduces an include guard to the file to prevent it from
executing twice. This avoids redefining the rules defined by `MAKE_LIB`.

Change-Id: I07e0648b07dbd907eaa6dd6fbd0788203b19fddb
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "chore(compiler-rt): update compiler-rt source files" into integration

chore(compiler-rt): update compiler-rt source files

Update the compiler-rt source files to the tip of llvm-project [1]
on 9th May 2024, sha 673cfcd03b7b938b422fee07d8ca4a127d480b1f

[1] https://gith

chore(compiler-rt): update compiler-rt source files

Update the compiler-rt source files to the tip of llvm-project [1]
on 9th May 2024, sha 673cfcd03b7b938b422fee07d8ca4a127d480b1f

[1] https://github.com/llvm/llvm-project

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I19f2b8ea6676d365780783f902003b0e95f0f606

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Merge "feat(cpus): support to update External LLC presence in Neoverse N3" into integration

Merge "feat(cpus): support to update External LLC presence in Neoverse V2" into integration

feat(cpus): support to update External LLC presence in Neoverse N3

The CPUECTLR_EL1.EXTLLC bit indicates that an external last level
cache(LLC) is present in the system. The default value is interna

feat(cpus): support to update External LLC presence in Neoverse N3

The CPUECTLR_EL1.EXTLLC bit indicates that an external last level
cache(LLC) is present in the system. The default value is internal LLC.
Some systems which may have External LLC can enable the External LLC
presece with the build option 'NEOVERSE_Nx_EXTERNAL_LLC'.

Change-Id: I2567283a55c0d6e2f9fd986b7dbab91c7a815d3d
Signed-off-by: Younghyun Park <younghyunpark@google.com>

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Merge changes from topic "fix_psci_osi" into integration

* changes:
fix(psci): fix parent_idx in psci_validate_state_coordination
fix(psci): mask the Last in Level nibble in StateId

fix(psci): fix parent_idx in psci_validate_state_coordination

Update parent_idx support in psci_validate_state_coordination() as
it is done in psci_do_state_coordination(). The modified loop verifie

fix(psci): fix parent_idx in psci_validate_state_coordination

Update parent_idx support in psci_validate_state_coordination() as
it is done in psci_do_state_coordination(). The modified loop verifies
the targeted state for all the branch up to end_pwrlvl in the topology
for the current cpu.

Fixes: 606b7430077c ("feat(psci): add support for OS-initiated mode")
Change-Id: I14420f64a18b543eb4e10a1279f51cc17558c13c
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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chore: rename hermes to neoverse-n3

Rename hermes cpu to Neoverse-N3

Change-Id: I912d4c824c5004a8c1909c68fef77f1f5e202b8a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

Merge changes from topic "sm/feat_detect" into integration

* changes:
refactor(cpufeat): restore functions in detect_arch_features
refactor(cpufeat): add macro to simplify is_feat_xx_present
c

Merge changes from topic "sm/feat_detect" into integration

* changes:
refactor(cpufeat): restore functions in detect_arch_features
refactor(cpufeat): add macro to simplify is_feat_xx_present
chore: simplify the macro names in ENABLE_FEAT mechanism

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feat(cpus): support to update External LLC presence in Neoverse V2

The CPUECTLR_EL1.EXTLLC bit indicates that an external last level
cache(LLC) is present in the system. The default value is interna

feat(cpus): support to update External LLC presence in Neoverse V2

The CPUECTLR_EL1.EXTLLC bit indicates that an external last level
cache(LLC) is present in the system. The default value is internal LLC.
Some systems which may have External LLC can enable the External LLC
presece with new build option 'NEOVERSE_Vx_EXTERNAL_LLC'.

Change-Id: I740947f1ef78e31626dc5b96f6d6dc6658d0120f
Signed-off-by: Younghyun Park <younghyunpark@google.com>

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feat((smccc): add version FID for PMF

Introduce a version FID for PMF.

Change-Id: I6b0a7f54aefc2839704e03c5da2243d7c85f8a49
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

refactor(smccc): move pmf to vendor el3 calls

Move pmf support to vendor-specific EL3 Monitor Service Calls. Remove
pmf call count as it's not supported in vendor-specific el3 as per
SMCCC Documenta

refactor(smccc): move pmf to vendor el3 calls

Move pmf support to vendor-specific EL3 Monitor Service Calls. Remove
pmf call count as it's not supported in vendor-specific el3 as per
SMCCC Documentation 1.5:
https://developer.arm.com/documentation/den0028/latest

Add a deprecation notice to inform PMF is moved from arm-sip range to
vendor-specific EL3 range. PMF support from arm-sip range will be
removed and will not available after TF-A 2.12 release.

Change-Id: Ie1e14aa601d4fc3db352cd5621d842017a18e9ec
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(cpus): replace adr with adr_l

Replace "adr" with "adr_l" to handle symbols or labels that exceeds 1MB
access range. This modification resolves the link error.

Change-Id: I9eba2e34c0a303b40

refactor(cpus): replace adr with adr_l

Replace "adr" with "adr_l" to handle symbols or labels that exceeds 1MB
access range. This modification resolves the link error.

Change-Id: I9eba2e34c0a303b40e4c7b3ea7c5b113f4c6d989
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>

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refactor(cpufeat): add macro to simplify is_feat_xx_present

In this patch, we are trying to introduce the wrapper macro
CREATE_FEATURE_PRESENT to get the following capability and
align it for all th

refactor(cpufeat): add macro to simplify is_feat_xx_present

In this patch, we are trying to introduce the wrapper macro
CREATE_FEATURE_PRESENT to get the following capability and
align it for all the features:

-> is_feat_xx_present(): Does Hardware implement the feature.
-> uniformity in naming the function across multiple features.
-> improved readability

The is_feat_xx_present() is implemented to check if the hardware
implements the feature and does not take into account the
ENABLE_FEAT_XXX flag enabled/disabled in software.

- CREATE_FEATURE_PRESENT(name, idreg, shift, mask, idval)
The wrapper macro reduces the function to a single line and
creates the is_feat_xx_present function that checks the
id register based on the shift and mask values and compares
this against a determined idvalue.

Change-Id: I7b91d2c9c6fbe55f94c693aa1b2c50be54fb9ecc
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore: simplify the macro names in ENABLE_FEAT mechanism

Currently, the macros used to denote feature implementation
in hardware follow a random pattern with a few macros having
suffix as SUPPORTED

chore: simplify the macro names in ENABLE_FEAT mechanism

Currently, the macros used to denote feature implementation
in hardware follow a random pattern with a few macros having
suffix as SUPPORTED and a few using the suffix IMPLEMENTED.
This patch aligns the macro names uniformly using the suffix
IMPLEMENTED across all the features and removes unused macros
pertaining to the Enable feat mechanism.

FEAT_SUPPORTED --> FEAT_IMPLEMENTED
FEAT_NOT_SUPPORTED --> FEAT_NOT_IMPLEMENTED

Change-Id: I61bb7d154b23f677b80756a4b6a81f74b10cd24f
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge changes from topic "rss_rse_rename" into integration

* changes:
refactor(changelog): change all occurrences of RSS to RSE
refactor(qemu): change all occurrences of RSS to RSE
refactor(fv

Merge changes from topic "rss_rse_rename" into integration

* changes:
refactor(changelog): change all occurrences of RSS to RSE
refactor(qemu): change all occurrences of RSS to RSE
refactor(fvp): change all occurrences of RSS to RSE
refactor(fiptool): change all occurrences of RSS to RSE
refactor(psa): change all occurrences of RSS to RSE
refactor(fvp): remove leftovers from rss measured boot support
refactor(tc): change all occurrences of RSS to RSE
docs: change all occurrences of RSS to RSE
refactor(measured-boot): change all occurrences of RSS to RSE
refactor(rse): change all occurrences of RSS to RSE
refactor(psa): rename all 'rss' files to 'rse'
refactor(tc): rename all 'rss' files to 'rse'
docs: rename all 'rss' files to 'rse'
refactor(measured-boot): rename all 'rss' files to 'rse'
refactor(rss): rename all 'rss' files to 'rse'

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Merge changes from topic "hm/handoff" into integration

* changes:
feat(handoff): add support for RESET_TO_BL2
feat(arm): support FW handoff b/w BL1 & BL2
feat(handoff): add TL source files to

Merge changes from topic "hm/handoff" into integration

* changes:
feat(handoff): add support for RESET_TO_BL2
feat(arm): support FW handoff b/w BL1 & BL2
feat(handoff): add TL source files to BL1
feat(handoff): add TE's for BL1 handoff interface
refactor(bl1): clean up bl2 layout calculation
feat(arm): support FW handoff b/w BL2 & BL31

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feat(handoff): add TL source files to BL1

Change-Id: Id9843ba0ccfb448cf17e09e0659b743741ae01ac
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

fix(cpus): workaround for Cortex-X4 erratum 2763018

Cortex-X4 erratum 2763018 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[47] of CP

fix(cpus): workaround for Cortex-X4 erratum 2763018

Cortex-X4 erratum 2763018 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[47] of CPUACTLR3_EL1 register.
Setting this chicken bit might have a small impact on power
and negligible impact on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest

Change-Id: Ia188e08c2eb2952923ec72e2a56efdeea836fe1e
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge "fix(cpus): workaround for Cortex-X4 erratum 2740089" into integration

Merge "fix(cpus): workaround for Cortex-A715 erratum 2728106" into integration

refactor(psa): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id

refactor(psa): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I606e2663fb3719edf6372d6ffa4f1982eef45994

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refactor(psa): rename all 'rss' files to 'rse'

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I379c471c541dda25d8ee9087fcf67e05b4204474

fix(cm): add more feature registers to EL1 context mgmt

The following system registers are made part of save and restore
operations for EL1 context:

TRFCR_EL1
SCXTNUM_EL0
SCXTNUM_EL1
GCSCR_EL1
GCSC

fix(cm): add more feature registers to EL1 context mgmt

The following system registers are made part of save and restore
operations for EL1 context:

TRFCR_EL1
SCXTNUM_EL0
SCXTNUM_EL1
GCSCR_EL1
GCSCRE0_EL1
GCSPR_EL1
GCSPR_EL0

Change-Id: I1077112bdc29a6c9cd39b9707d6cf10b95fa15e3
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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