1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/mpam.h> 32 #include <lib/extensions/pmuv3.h> 33 #include <lib/extensions/sme.h> 34 #include <lib/extensions/spe.h> 35 #include <lib/extensions/sve.h> 36 #include <lib/extensions/sys_reg_trace.h> 37 #include <lib/extensions/tcr2.h> 38 #include <lib/extensions/trbe.h> 39 #include <lib/extensions/trf.h> 40 #include <lib/utils.h> 41 42 #if ENABLE_FEAT_TWED 43 /* Make sure delay value fits within the range(0-15) */ 44 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 45 #endif /* ENABLE_FEAT_TWED */ 46 47 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 48 static bool has_secure_perworld_init; 49 50 static void manage_extensions_common(cpu_context_t *ctx); 51 static void manage_extensions_nonsecure(cpu_context_t *ctx); 52 static void manage_extensions_secure(cpu_context_t *ctx); 53 static void manage_extensions_secure_per_world(void); 54 55 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 56 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 57 { 58 u_register_t sctlr_elx, actlr_elx; 59 60 /* 61 * Initialise SCTLR_EL1 to the reset value corresponding to the target 62 * execution state setting all fields rather than relying on the hw. 63 * Some fields have architecturally UNKNOWN reset values and these are 64 * set to zero. 65 * 66 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 67 * 68 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 69 * required by PSCI specification) 70 */ 71 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 72 if (GET_RW(ep->spsr) == MODE_RW_64) { 73 sctlr_elx |= SCTLR_EL1_RES1; 74 } else { 75 /* 76 * If the target execution state is AArch32 then the following 77 * fields need to be set. 78 * 79 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 80 * instructions are not trapped to EL1. 81 * 82 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 83 * instructions are not trapped to EL1. 84 * 85 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 86 * CP15DMB, CP15DSB, and CP15ISB instructions. 87 */ 88 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 89 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 90 } 91 92 /* 93 * If workaround of errata 764081 for Cortex-A75 is used then set 94 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 95 */ 96 if (errata_a75_764081_applies()) { 97 sctlr_elx |= SCTLR_IESB_BIT; 98 } 99 100 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 101 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 102 103 /* 104 * Base the context ACTLR_EL1 on the current value, as it is 105 * implementation defined. The context restore process will write 106 * the value from the context to the actual register and can cause 107 * problems for processor cores that don't expect certain bits to 108 * be zero. 109 */ 110 actlr_elx = read_actlr_el1(); 111 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 112 } 113 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 114 115 /****************************************************************************** 116 * This function performs initializations that are specific to SECURE state 117 * and updates the cpu context specified by 'ctx'. 118 *****************************************************************************/ 119 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 120 { 121 u_register_t scr_el3; 122 el3_state_t *state; 123 124 state = get_el3state_ctx(ctx); 125 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 126 127 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 128 /* 129 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 130 * indicated by the interrupt routing model for BL31. 131 */ 132 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 133 #endif 134 135 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 136 if (is_feat_mte2_supported()) { 137 scr_el3 |= SCR_ATA_BIT; 138 } 139 140 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 141 142 /* 143 * Initialize EL1 context registers unless SPMC is running 144 * at S-EL2. 145 */ 146 #if (!SPMD_SPM_AT_SEL2) 147 setup_el1_context(ctx, ep); 148 #endif 149 150 manage_extensions_secure(ctx); 151 152 /** 153 * manage_extensions_secure_per_world api has to be executed once, 154 * as the registers getting initialised, maintain constant value across 155 * all the cpus for the secure world. 156 * Henceforth, this check ensures that the registers are initialised once 157 * and avoids re-initialization from multiple cores. 158 */ 159 if (!has_secure_perworld_init) { 160 manage_extensions_secure_per_world(); 161 } 162 } 163 164 #if ENABLE_RME 165 /****************************************************************************** 166 * This function performs initializations that are specific to REALM state 167 * and updates the cpu context specified by 'ctx'. 168 *****************************************************************************/ 169 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 170 { 171 u_register_t scr_el3; 172 el3_state_t *state; 173 174 state = get_el3state_ctx(ctx); 175 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 176 177 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 178 179 /* CSV2 version 2 and above */ 180 if (is_feat_csv2_2_supported()) { 181 /* Enable access to the SCXTNUM_ELx registers. */ 182 scr_el3 |= SCR_EnSCXT_BIT; 183 } 184 185 if (is_feat_sctlr2_supported()) { 186 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 187 * SCTLR2_ELx registers. 188 */ 189 scr_el3 |= SCR_SCTLR2En_BIT; 190 } 191 192 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 193 } 194 #endif /* ENABLE_RME */ 195 196 /****************************************************************************** 197 * This function performs initializations that are specific to NON-SECURE state 198 * and updates the cpu context specified by 'ctx'. 199 *****************************************************************************/ 200 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 201 { 202 u_register_t scr_el3; 203 el3_state_t *state; 204 205 state = get_el3state_ctx(ctx); 206 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 207 208 /* SCR_NS: Set the NS bit */ 209 scr_el3 |= SCR_NS_BIT; 210 211 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 212 if (is_feat_mte2_supported()) { 213 scr_el3 |= SCR_ATA_BIT; 214 } 215 216 #if !CTX_INCLUDE_PAUTH_REGS 217 /* 218 * Pointer Authentication feature, if present, is always enabled by default 219 * for Non secure lower exception levels. We do not have an explicit 220 * flag to set it. 221 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 222 * exception levels of secure and realm worlds. 223 * 224 * To prevent the leakage between the worlds during world switch, 225 * we enable it only for the non-secure world. 226 * 227 * If the Secure/realm world wants to use pointer authentication, 228 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 229 * it will be enabled globally for all the contexts. 230 * 231 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 232 * other than EL3 233 * 234 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 235 * than EL3 236 */ 237 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 238 239 #endif /* CTX_INCLUDE_PAUTH_REGS */ 240 241 #if HANDLE_EA_EL3_FIRST_NS 242 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 243 scr_el3 |= SCR_EA_BIT; 244 #endif 245 246 #if RAS_TRAP_NS_ERR_REC_ACCESS 247 /* 248 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 249 * and RAS ERX registers from EL1 and EL2(from any security state) 250 * are trapped to EL3. 251 * Set here to trap only for NS EL1/EL2 252 * 253 */ 254 scr_el3 |= SCR_TERR_BIT; 255 #endif 256 257 /* CSV2 version 2 and above */ 258 if (is_feat_csv2_2_supported()) { 259 /* Enable access to the SCXTNUM_ELx registers. */ 260 scr_el3 |= SCR_EnSCXT_BIT; 261 } 262 263 #ifdef IMAGE_BL31 264 /* 265 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 266 * indicated by the interrupt routing model for BL31. 267 */ 268 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 269 #endif 270 271 if (is_feat_the_supported()) { 272 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 273 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 274 */ 275 scr_el3 |= SCR_RCWMASKEn_BIT; 276 } 277 278 if (is_feat_sctlr2_supported()) { 279 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 280 * SCTLR2_ELx registers. 281 */ 282 scr_el3 |= SCR_SCTLR2En_BIT; 283 } 284 285 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 286 287 /* Initialize EL2 context registers */ 288 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 289 290 /* 291 * Initialize SCTLR_EL2 context register with reset value. 292 */ 293 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 294 295 if (is_feat_hcx_supported()) { 296 /* 297 * Initialize register HCRX_EL2 with its init value. 298 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 299 * chance that this can lead to unexpected behavior in lower 300 * ELs that have not been updated since the introduction of 301 * this feature if not properly initialized, especially when 302 * it comes to those bits that enable/disable traps. 303 */ 304 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 305 HCRX_EL2_INIT_VAL); 306 } 307 308 if (is_feat_fgt_supported()) { 309 /* 310 * Initialize HFG*_EL2 registers with a default value so legacy 311 * systems unaware of FEAT_FGT do not get trapped due to their lack 312 * of initialization for this feature. 313 */ 314 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 315 HFGITR_EL2_INIT_VAL); 316 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 317 HFGRTR_EL2_INIT_VAL); 318 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 319 HFGWTR_EL2_INIT_VAL); 320 } 321 #else 322 /* Initialize EL1 context registers */ 323 setup_el1_context(ctx, ep); 324 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 325 326 manage_extensions_nonsecure(ctx); 327 } 328 329 /******************************************************************************* 330 * The following function performs initialization of the cpu_context 'ctx' 331 * for first use that is common to all security states, and sets the 332 * initial entrypoint state as specified by the entry_point_info structure. 333 * 334 * The EE and ST attributes are used to configure the endianness and secure 335 * timer availability for the new execution context. 336 ******************************************************************************/ 337 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 338 { 339 u_register_t scr_el3; 340 u_register_t mdcr_el3; 341 el3_state_t *state; 342 gp_regs_t *gp_regs; 343 344 state = get_el3state_ctx(ctx); 345 346 /* Clear any residual register values from the context */ 347 zeromem(ctx, sizeof(*ctx)); 348 349 /* 350 * The lower-EL context is zeroed so that no stale values leak to a world. 351 * It is assumed that an all-zero lower-EL context is good enough for it 352 * to boot correctly. However, there are very few registers where this 353 * is not true and some values need to be recreated. 354 */ 355 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 356 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 357 358 /* 359 * These bits are set in the gicv3 driver. Losing them (especially the 360 * SRE bit) is problematic for all worlds. Henceforth recreate them. 361 */ 362 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 363 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 364 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 365 366 /* 367 * The actlr_el2 register can be initialized in platform's reset handler 368 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 369 */ 370 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 371 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 372 373 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 374 scr_el3 = SCR_RESET_VAL; 375 376 /* 377 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 378 * EL2, EL1 and EL0 are not trapped to EL3. 379 * 380 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 381 * EL2, EL1 and EL0 are not trapped to EL3. 382 * 383 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 384 * both Security states and both Execution states. 385 * 386 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 387 * Non-secure memory. 388 */ 389 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 390 391 scr_el3 |= SCR_SIF_BIT; 392 393 /* 394 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 395 * Exception level as specified by SPSR. 396 */ 397 if (GET_RW(ep->spsr) == MODE_RW_64) { 398 scr_el3 |= SCR_RW_BIT; 399 } 400 401 /* 402 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 403 * Secure timer registers to EL3, from AArch64 state only, if specified 404 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 405 * bit always behaves as 1 (i.e. secure physical timer register access 406 * is not trapped) 407 */ 408 if (EP_GET_ST(ep->h.attr) != 0U) { 409 scr_el3 |= SCR_ST_BIT; 410 } 411 412 /* 413 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 414 * SCR_EL3.HXEn. 415 */ 416 if (is_feat_hcx_supported()) { 417 scr_el3 |= SCR_HXEn_BIT; 418 } 419 420 /* 421 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 422 * registers are trapped to EL3. 423 */ 424 #if ENABLE_FEAT_RNG_TRAP 425 scr_el3 |= SCR_TRNDR_BIT; 426 #endif 427 428 #if FAULT_INJECTION_SUPPORT 429 /* Enable fault injection from lower ELs */ 430 scr_el3 |= SCR_FIEN_BIT; 431 #endif 432 433 #if CTX_INCLUDE_PAUTH_REGS 434 /* 435 * Enable Pointer Authentication globally for all the worlds. 436 * 437 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 438 * other than EL3 439 * 440 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 441 * than EL3 442 */ 443 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 444 #endif /* CTX_INCLUDE_PAUTH_REGS */ 445 446 /* 447 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 448 */ 449 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 450 scr_el3 |= SCR_TCR2EN_BIT; 451 } 452 453 /* 454 * SCR_EL3.PIEN: Enable permission indirection and overlay 455 * registers for AArch64 if present. 456 */ 457 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 458 scr_el3 |= SCR_PIEN_BIT; 459 } 460 461 /* 462 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 463 */ 464 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 465 scr_el3 |= SCR_GCSEn_BIT; 466 } 467 468 /* 469 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 470 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 471 * next mode is Hyp. 472 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 473 * same conditions as HVC instructions and when the processor supports 474 * ARMv8.6-FGT. 475 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 476 * CNTPOFF_EL2 register under the same conditions as HVC instructions 477 * and when the processor supports ECV. 478 */ 479 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 480 || ((GET_RW(ep->spsr) != MODE_RW_64) 481 && (GET_M32(ep->spsr) == MODE32_hyp))) { 482 scr_el3 |= SCR_HCE_BIT; 483 484 if (is_feat_fgt_supported()) { 485 scr_el3 |= SCR_FGTEN_BIT; 486 } 487 488 if (is_feat_ecv_supported()) { 489 scr_el3 |= SCR_ECVEN_BIT; 490 } 491 } 492 493 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 494 if (is_feat_twed_supported()) { 495 /* Set delay in SCR_EL3 */ 496 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 497 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 498 << SCR_TWEDEL_SHIFT); 499 500 /* Enable WFE delay */ 501 scr_el3 |= SCR_TWEDEn_BIT; 502 } 503 504 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 505 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 506 if (is_feat_sel2_supported()) { 507 scr_el3 |= SCR_EEL2_BIT; 508 } 509 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 510 511 /* 512 * Populate EL3 state so that we've the right context 513 * before doing ERET 514 */ 515 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 516 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 517 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 518 519 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 520 mdcr_el3 = MDCR_EL3_RESET_VAL; 521 522 /* --------------------------------------------------------------------- 523 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 524 * Some fields are architecturally UNKNOWN on reset. 525 * 526 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 527 * Debug exceptions, other than Breakpoint Instruction exceptions, are 528 * disabled from all ELs in Secure state. 529 * 530 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 531 * privileged debug from S-EL1. 532 * 533 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 534 * access to the powerdown debug registers do not trap to EL3. 535 * 536 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 537 * debug registers, other than those registers that are controlled by 538 * MDCR_EL3.TDOSA. 539 */ 540 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 541 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 542 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 543 544 /* 545 * Configure MDCR_EL3 register as applicable for each world 546 * (NS/Secure/Realm) context. 547 */ 548 manage_extensions_common(ctx); 549 550 /* 551 * Store the X0-X7 value from the entrypoint into the context 552 * Use memcpy as we are in control of the layout of the structures 553 */ 554 gp_regs = get_gpregs_ctx(ctx); 555 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 556 } 557 558 /******************************************************************************* 559 * Context management library initialization routine. This library is used by 560 * runtime services to share pointers to 'cpu_context' structures for secure 561 * non-secure and realm states. Management of the structures and their associated 562 * memory is not done by the context management library e.g. the PSCI service 563 * manages the cpu context used for entry from and exit to the non-secure state. 564 * The Secure payload dispatcher service manages the context(s) corresponding to 565 * the secure state. It also uses this library to get access to the non-secure 566 * state cpu context pointers. 567 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 568 * which will be used for programming an entry into a lower EL. The same context 569 * will be used to save state upon exception entry from that EL. 570 ******************************************************************************/ 571 void __init cm_init(void) 572 { 573 /* 574 * The context management library has only global data to initialize, but 575 * that will be done when the BSS is zeroed out. 576 */ 577 } 578 579 /******************************************************************************* 580 * This is the high-level function used to initialize the cpu_context 'ctx' for 581 * first use. It performs initializations that are common to all security states 582 * and initializations specific to the security state specified in 'ep' 583 ******************************************************************************/ 584 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 585 { 586 unsigned int security_state; 587 588 assert(ctx != NULL); 589 590 /* 591 * Perform initializations that are common 592 * to all security states 593 */ 594 setup_context_common(ctx, ep); 595 596 security_state = GET_SECURITY_STATE(ep->h.attr); 597 598 /* Perform security state specific initializations */ 599 switch (security_state) { 600 case SECURE: 601 setup_secure_context(ctx, ep); 602 break; 603 #if ENABLE_RME 604 case REALM: 605 setup_realm_context(ctx, ep); 606 break; 607 #endif 608 case NON_SECURE: 609 setup_ns_context(ctx, ep); 610 break; 611 default: 612 ERROR("Invalid security state\n"); 613 panic(); 614 break; 615 } 616 } 617 618 /******************************************************************************* 619 * Enable architecture extensions for EL3 execution. This function only updates 620 * registers in-place which are expected to either never change or be 621 * overwritten by el3_exit. 622 ******************************************************************************/ 623 #if IMAGE_BL31 624 void cm_manage_extensions_el3(void) 625 { 626 if (is_feat_amu_supported()) { 627 amu_init_el3(); 628 } 629 630 if (is_feat_sme_supported()) { 631 sme_init_el3(); 632 } 633 634 pmuv3_init_el3(); 635 } 636 #endif /* IMAGE_BL31 */ 637 638 /****************************************************************************** 639 * Function to initialise the registers with the RESET values in the context 640 * memory, which are maintained per world. 641 ******************************************************************************/ 642 #if IMAGE_BL31 643 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 644 { 645 /* 646 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 647 * 648 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 649 * by Advanced SIMD, floating-point or SVE instructions (if 650 * implemented) do not trap to EL3. 651 * 652 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 653 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 654 */ 655 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 656 657 per_world_ctx->ctx_cptr_el3 = cptr_el3; 658 659 /* 660 * Initialize MPAM3_EL3 to its default reset value 661 * 662 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 663 * all lower ELn MPAM3_EL3 register access to, trap to EL3 664 */ 665 666 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 667 } 668 #endif /* IMAGE_BL31 */ 669 670 /******************************************************************************* 671 * Initialise per_world_context for Non-Secure world. 672 * This function enables the architecture extensions, which have same value 673 * across the cores for the non-secure world. 674 ******************************************************************************/ 675 #if IMAGE_BL31 676 void manage_extensions_nonsecure_per_world(void) 677 { 678 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 679 680 if (is_feat_sme_supported()) { 681 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 682 } 683 684 if (is_feat_sve_supported()) { 685 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 686 } 687 688 if (is_feat_amu_supported()) { 689 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 690 } 691 692 if (is_feat_sys_reg_trace_supported()) { 693 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 694 } 695 696 if (is_feat_mpam_supported()) { 697 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 698 } 699 } 700 #endif /* IMAGE_BL31 */ 701 702 /******************************************************************************* 703 * Initialise per_world_context for Secure world. 704 * This function enables the architecture extensions, which have same value 705 * across the cores for the secure world. 706 ******************************************************************************/ 707 static void manage_extensions_secure_per_world(void) 708 { 709 #if IMAGE_BL31 710 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 711 712 if (is_feat_sme_supported()) { 713 714 if (ENABLE_SME_FOR_SWD) { 715 /* 716 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 717 * SME, SVE, and FPU/SIMD context properly managed. 718 */ 719 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 720 } else { 721 /* 722 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 723 * world can safely use the associated registers. 724 */ 725 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 726 } 727 } 728 if (is_feat_sve_supported()) { 729 if (ENABLE_SVE_FOR_SWD) { 730 /* 731 * Enable SVE and FPU in secure context, SPM must ensure 732 * that the SVE and FPU register contexts are properly managed. 733 */ 734 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 735 } else { 736 /* 737 * Disable SVE and FPU in secure context so non-secure world 738 * can safely use them. 739 */ 740 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 741 } 742 } 743 744 /* NS can access this but Secure shouldn't */ 745 if (is_feat_sys_reg_trace_supported()) { 746 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 747 } 748 749 has_secure_perworld_init = true; 750 #endif /* IMAGE_BL31 */ 751 } 752 753 /******************************************************************************* 754 * Enable architecture extensions on first entry to Non-secure world only 755 * and disable for secure world. 756 * 757 * NOTE: Arch features which have been provided with the capability of getting 758 * enabled only for non-secure world and being disabled for secure world are 759 * grouped here, as the MDCR_EL3 context value remains same across the worlds. 760 ******************************************************************************/ 761 static void manage_extensions_common(cpu_context_t *ctx) 762 { 763 #if IMAGE_BL31 764 if (is_feat_spe_supported()) { 765 /* 766 * Enable FEAT_SPE for Non-Secure and prohibit for Secure state. 767 */ 768 spe_enable(ctx); 769 } 770 771 if (is_feat_trbe_supported()) { 772 /* 773 * Enable FEAT_TRBE for Non-Secure and prohibit for Secure and 774 * Realm state. 775 */ 776 trbe_enable(ctx); 777 } 778 779 if (is_feat_trf_supported()) { 780 /* 781 * Enable FEAT_TRF for Non-Secure and prohibit for Secure state. 782 */ 783 trf_enable(ctx); 784 } 785 #endif /* IMAGE_BL31 */ 786 } 787 788 /******************************************************************************* 789 * Enable architecture extensions on first entry to Non-secure world. 790 ******************************************************************************/ 791 static void manage_extensions_nonsecure(cpu_context_t *ctx) 792 { 793 #if IMAGE_BL31 794 if (is_feat_amu_supported()) { 795 amu_enable(ctx); 796 } 797 798 if (is_feat_sme_supported()) { 799 sme_enable(ctx); 800 } 801 802 if (is_feat_fgt2_supported()) { 803 fgt2_enable(ctx); 804 } 805 806 if (is_feat_debugv8p9_supported()) { 807 debugv8p9_extended_bp_wp_enable(ctx); 808 } 809 810 if (is_feat_brbe_supported()) { 811 brbe_enable(ctx); 812 } 813 814 pmuv3_enable(ctx); 815 #endif /* IMAGE_BL31 */ 816 } 817 818 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 819 static __unused void enable_pauth_el2(void) 820 { 821 u_register_t hcr_el2 = read_hcr_el2(); 822 /* 823 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 824 * accessing key registers or using pointer authentication instructions 825 * from lower ELs. 826 */ 827 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 828 829 write_hcr_el2(hcr_el2); 830 } 831 832 #if INIT_UNUSED_NS_EL2 833 /******************************************************************************* 834 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 835 * world when EL2 is empty and unused. 836 ******************************************************************************/ 837 static void manage_extensions_nonsecure_el2_unused(void) 838 { 839 #if IMAGE_BL31 840 if (is_feat_spe_supported()) { 841 spe_init_el2_unused(); 842 } 843 844 if (is_feat_amu_supported()) { 845 amu_init_el2_unused(); 846 } 847 848 if (is_feat_mpam_supported()) { 849 mpam_init_el2_unused(); 850 } 851 852 if (is_feat_trbe_supported()) { 853 trbe_init_el2_unused(); 854 } 855 856 if (is_feat_sys_reg_trace_supported()) { 857 sys_reg_trace_init_el2_unused(); 858 } 859 860 if (is_feat_trf_supported()) { 861 trf_init_el2_unused(); 862 } 863 864 pmuv3_init_el2_unused(); 865 866 if (is_feat_sve_supported()) { 867 sve_init_el2_unused(); 868 } 869 870 if (is_feat_sme_supported()) { 871 sme_init_el2_unused(); 872 } 873 874 #if ENABLE_PAUTH 875 enable_pauth_el2(); 876 #endif /* ENABLE_PAUTH */ 877 #endif /* IMAGE_BL31 */ 878 } 879 #endif /* INIT_UNUSED_NS_EL2 */ 880 881 /******************************************************************************* 882 * Enable architecture extensions on first entry to Secure world. 883 ******************************************************************************/ 884 static void manage_extensions_secure(cpu_context_t *ctx) 885 { 886 #if IMAGE_BL31 887 if (is_feat_sme_supported()) { 888 if (ENABLE_SME_FOR_SWD) { 889 /* 890 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 891 * must ensure SME, SVE, and FPU/SIMD context properly managed. 892 */ 893 sme_init_el3(); 894 sme_enable(ctx); 895 } else { 896 /* 897 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 898 * world can safely use the associated registers. 899 */ 900 sme_disable(ctx); 901 } 902 } 903 #endif /* IMAGE_BL31 */ 904 } 905 906 #if !IMAGE_BL1 907 /******************************************************************************* 908 * The following function initializes the cpu_context for a CPU specified by 909 * its `cpu_idx` for first use, and sets the initial entrypoint state as 910 * specified by the entry_point_info structure. 911 ******************************************************************************/ 912 void cm_init_context_by_index(unsigned int cpu_idx, 913 const entry_point_info_t *ep) 914 { 915 cpu_context_t *ctx; 916 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 917 cm_setup_context(ctx, ep); 918 } 919 #endif /* !IMAGE_BL1 */ 920 921 /******************************************************************************* 922 * The following function initializes the cpu_context for the current CPU 923 * for first use, and sets the initial entrypoint state as specified by the 924 * entry_point_info structure. 925 ******************************************************************************/ 926 void cm_init_my_context(const entry_point_info_t *ep) 927 { 928 cpu_context_t *ctx; 929 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 930 cm_setup_context(ctx, ep); 931 } 932 933 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 934 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 935 { 936 #if INIT_UNUSED_NS_EL2 937 u_register_t hcr_el2 = HCR_RESET_VAL; 938 u_register_t mdcr_el2; 939 u_register_t scr_el3; 940 941 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 942 943 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 944 if ((scr_el3 & SCR_RW_BIT) != 0U) { 945 hcr_el2 |= HCR_RW_BIT; 946 } 947 948 write_hcr_el2(hcr_el2); 949 950 /* 951 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 952 * All fields have architecturally UNKNOWN reset values. 953 */ 954 write_cptr_el2(CPTR_EL2_RESET_VAL); 955 956 /* 957 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 958 * reset and are set to zero except for field(s) listed below. 959 * 960 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 961 * Non-secure EL0 and EL1 accesses to the physical timer registers. 962 * 963 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 964 * Non-secure EL0 and EL1 accesses to the physical counter registers. 965 */ 966 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 967 968 /* 969 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 970 * UNKNOWN value. 971 */ 972 write_cntvoff_el2(0); 973 974 /* 975 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 976 * respectively. 977 */ 978 write_vpidr_el2(read_midr_el1()); 979 write_vmpidr_el2(read_mpidr_el1()); 980 981 /* 982 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 983 * 984 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 985 * translation is disabled, cache maintenance operations depend on the 986 * VMID. 987 * 988 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 989 * disabled. 990 */ 991 write_vttbr_el2(VTTBR_RESET_VAL & 992 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 993 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 994 995 /* 996 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 997 * Some fields are architecturally UNKNOWN on reset. 998 * 999 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1000 * register accesses to the Debug ROM registers are not trapped to EL2. 1001 * 1002 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1003 * accesses to the powerdown debug registers are not trapped to EL2. 1004 * 1005 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1006 * debug registers do not trap to EL2. 1007 * 1008 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1009 * EL2. 1010 */ 1011 mdcr_el2 = MDCR_EL2_RESET_VAL & 1012 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1013 MDCR_EL2_TDE_BIT); 1014 1015 write_mdcr_el2(mdcr_el2); 1016 1017 /* 1018 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1019 * 1020 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1021 * EL1 accesses to System registers do not trap to EL2. 1022 */ 1023 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1024 1025 /* 1026 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1027 * reset. 1028 * 1029 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1030 * and prevent timer interrupts. 1031 */ 1032 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1033 1034 manage_extensions_nonsecure_el2_unused(); 1035 #endif /* INIT_UNUSED_NS_EL2 */ 1036 } 1037 1038 /******************************************************************************* 1039 * Prepare the CPU system registers for first entry into realm, secure, or 1040 * normal world. 1041 * 1042 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1043 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1044 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1045 * For all entries, the EL1 registers are initialized from the cpu_context 1046 ******************************************************************************/ 1047 void cm_prepare_el3_exit(uint32_t security_state) 1048 { 1049 u_register_t sctlr_el2, scr_el3; 1050 cpu_context_t *ctx = cm_get_context(security_state); 1051 1052 assert(ctx != NULL); 1053 1054 if (security_state == NON_SECURE) { 1055 uint64_t el2_implemented = el_implemented(2); 1056 1057 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1058 CTX_SCR_EL3); 1059 1060 if (el2_implemented != EL_IMPL_NONE) { 1061 1062 /* 1063 * If context is not being used for EL2, initialize 1064 * HCRX_EL2 with its init value here. 1065 */ 1066 if (is_feat_hcx_supported()) { 1067 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1068 } 1069 1070 /* 1071 * Initialize Fine-grained trap registers introduced 1072 * by FEAT_FGT so all traps are initially disabled when 1073 * switching to EL2 or a lower EL, preventing undesired 1074 * behavior. 1075 */ 1076 if (is_feat_fgt_supported()) { 1077 /* 1078 * Initialize HFG*_EL2 registers with a default 1079 * value so legacy systems unaware of FEAT_FGT 1080 * do not get trapped due to their lack of 1081 * initialization for this feature. 1082 */ 1083 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1084 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1085 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1086 } 1087 1088 /* Condition to ensure EL2 is being used. */ 1089 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1090 /* Initialize SCTLR_EL2 register with reset value. */ 1091 sctlr_el2 = SCTLR_EL2_RES1; 1092 1093 /* 1094 * If workaround of errata 764081 for Cortex-A75 1095 * is used then set SCTLR_EL2.IESB to enable 1096 * Implicit Error Synchronization Barrier. 1097 */ 1098 if (errata_a75_764081_applies()) { 1099 sctlr_el2 |= SCTLR_IESB_BIT; 1100 } 1101 1102 write_sctlr_el2(sctlr_el2); 1103 } else { 1104 /* 1105 * (scr_el3 & SCR_HCE_BIT==0) 1106 * EL2 implemented but unused. 1107 */ 1108 init_nonsecure_el2_unused(ctx); 1109 } 1110 } 1111 } 1112 #if (!CTX_INCLUDE_EL2_REGS) 1113 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1114 cm_el1_sysregs_context_restore(security_state); 1115 #endif 1116 cm_set_next_eret_context(security_state); 1117 } 1118 1119 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1120 1121 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1122 { 1123 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1124 if (is_feat_amu_supported()) { 1125 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1126 } 1127 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1128 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1129 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1130 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1131 } 1132 1133 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1134 { 1135 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1136 if (is_feat_amu_supported()) { 1137 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1138 } 1139 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1140 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1141 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1142 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1143 } 1144 1145 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1146 { 1147 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1148 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1149 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1150 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1151 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1152 } 1153 1154 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1155 { 1156 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1157 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1158 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1159 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1160 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1161 } 1162 1163 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1164 { 1165 u_register_t mpam_idr = read_mpamidr_el1(); 1166 1167 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1168 1169 /* 1170 * The context registers that we intend to save would be part of the 1171 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1172 */ 1173 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1174 return; 1175 } 1176 1177 /* 1178 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1179 * MPAMIDR_HAS_HCR_BIT == 1. 1180 */ 1181 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1182 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1183 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1184 1185 /* 1186 * The number of MPAMVPM registers is implementation defined, their 1187 * number is stored in the MPAMIDR_EL1 register. 1188 */ 1189 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1190 case 7: 1191 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1192 __fallthrough; 1193 case 6: 1194 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1195 __fallthrough; 1196 case 5: 1197 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1198 __fallthrough; 1199 case 4: 1200 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1201 __fallthrough; 1202 case 3: 1203 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1204 __fallthrough; 1205 case 2: 1206 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1207 __fallthrough; 1208 case 1: 1209 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1210 break; 1211 } 1212 } 1213 1214 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1215 { 1216 u_register_t mpam_idr = read_mpamidr_el1(); 1217 1218 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1219 1220 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1221 return; 1222 } 1223 1224 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1225 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1226 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1227 1228 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1229 case 7: 1230 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1231 __fallthrough; 1232 case 6: 1233 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1234 __fallthrough; 1235 case 5: 1236 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1237 __fallthrough; 1238 case 4: 1239 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1240 __fallthrough; 1241 case 3: 1242 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1243 __fallthrough; 1244 case 2: 1245 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1246 __fallthrough; 1247 case 1: 1248 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1249 break; 1250 } 1251 } 1252 1253 /* --------------------------------------------------------------------------- 1254 * The following registers are not added: 1255 * ICH_AP0R<n>_EL2 1256 * ICH_AP1R<n>_EL2 1257 * ICH_LR<n>_EL2 1258 * 1259 * NOTE: For a system with S-EL2 present but not enabled, accessing 1260 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1261 * SCR_EL3.NS = 1 before accessing this register. 1262 * --------------------------------------------------------------------------- 1263 */ 1264 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) 1265 { 1266 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1267 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1268 #else 1269 u_register_t scr_el3 = read_scr_el3(); 1270 write_scr_el3(scr_el3 | SCR_NS_BIT); 1271 isb(); 1272 1273 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1274 1275 write_scr_el3(scr_el3); 1276 isb(); 1277 #endif 1278 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1279 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1280 } 1281 1282 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) 1283 { 1284 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1285 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1286 #else 1287 u_register_t scr_el3 = read_scr_el3(); 1288 write_scr_el3(scr_el3 | SCR_NS_BIT); 1289 isb(); 1290 1291 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1292 1293 write_scr_el3(scr_el3); 1294 isb(); 1295 #endif 1296 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1297 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1298 } 1299 1300 /* ----------------------------------------------------- 1301 * The following registers are not added: 1302 * AMEVCNTVOFF0<n>_EL2 1303 * AMEVCNTVOFF1<n>_EL2 1304 * ----------------------------------------------------- 1305 */ 1306 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1307 { 1308 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1309 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1310 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1311 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1312 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1313 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1314 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1315 if (CTX_INCLUDE_AARCH32_REGS) { 1316 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1317 } 1318 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1319 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1320 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1321 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1322 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1323 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1324 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1325 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1326 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1327 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1328 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1329 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1330 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1331 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1332 write_el2_ctx_common(ctx, ttbr0_el2, read_ttbr0_el2()); 1333 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1334 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1335 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1336 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1337 write_el2_ctx_common(ctx, vttbr_el2, read_vttbr_el2()); 1338 } 1339 1340 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1341 { 1342 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1343 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1344 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1345 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1346 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1347 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1348 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1349 if (CTX_INCLUDE_AARCH32_REGS) { 1350 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1351 } 1352 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1353 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1354 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1355 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1356 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1357 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1358 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1359 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1360 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1361 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1362 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1363 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1364 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1365 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1366 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1367 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1368 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1369 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1370 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1371 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1372 } 1373 1374 /******************************************************************************* 1375 * Save EL2 sysreg context 1376 ******************************************************************************/ 1377 void cm_el2_sysregs_context_save(uint32_t security_state) 1378 { 1379 cpu_context_t *ctx; 1380 el2_sysregs_t *el2_sysregs_ctx; 1381 1382 ctx = cm_get_context(security_state); 1383 assert(ctx != NULL); 1384 1385 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1386 1387 el2_sysregs_context_save_common(el2_sysregs_ctx); 1388 el2_sysregs_context_save_gic(el2_sysregs_ctx); 1389 1390 if (is_feat_mte2_supported()) { 1391 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1392 } 1393 1394 if (is_feat_mpam_supported()) { 1395 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1396 } 1397 1398 if (is_feat_fgt_supported()) { 1399 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1400 } 1401 1402 if (is_feat_fgt2_supported()) { 1403 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1404 } 1405 1406 if (is_feat_ecv_v2_supported()) { 1407 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1408 } 1409 1410 if (is_feat_vhe_supported()) { 1411 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1412 read_contextidr_el2()); 1413 write_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1414 } 1415 1416 if (is_feat_ras_supported()) { 1417 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1418 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1419 } 1420 1421 if (is_feat_nv2_supported()) { 1422 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1423 } 1424 1425 if (is_feat_trf_supported()) { 1426 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1427 } 1428 1429 if (is_feat_csv2_2_supported()) { 1430 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1431 read_scxtnum_el2()); 1432 } 1433 1434 if (is_feat_hcx_supported()) { 1435 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1436 } 1437 1438 if (is_feat_tcr2_supported()) { 1439 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1440 } 1441 1442 if (is_feat_sxpie_supported()) { 1443 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1444 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1445 } 1446 1447 if (is_feat_sxpoe_supported()) { 1448 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1449 } 1450 1451 if (is_feat_s2pie_supported()) { 1452 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1453 } 1454 1455 if (is_feat_gcs_supported()) { 1456 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1457 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1458 } 1459 1460 if (is_feat_sctlr2_supported()) { 1461 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1462 } 1463 } 1464 1465 /******************************************************************************* 1466 * Restore EL2 sysreg context 1467 ******************************************************************************/ 1468 void cm_el2_sysregs_context_restore(uint32_t security_state) 1469 { 1470 cpu_context_t *ctx; 1471 el2_sysregs_t *el2_sysregs_ctx; 1472 1473 ctx = cm_get_context(security_state); 1474 assert(ctx != NULL); 1475 1476 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1477 1478 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1479 el2_sysregs_context_restore_gic(el2_sysregs_ctx); 1480 1481 if (is_feat_mte2_supported()) { 1482 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1483 } 1484 1485 if (is_feat_mpam_supported()) { 1486 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1487 } 1488 1489 if (is_feat_fgt_supported()) { 1490 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1491 } 1492 1493 if (is_feat_fgt2_supported()) { 1494 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1495 } 1496 1497 if (is_feat_ecv_v2_supported()) { 1498 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1499 } 1500 1501 if (is_feat_vhe_supported()) { 1502 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1503 contextidr_el2)); 1504 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1505 } 1506 1507 if (is_feat_ras_supported()) { 1508 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1509 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1510 } 1511 1512 if (is_feat_nv2_supported()) { 1513 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1514 } 1515 1516 if (is_feat_trf_supported()) { 1517 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1518 } 1519 1520 if (is_feat_csv2_2_supported()) { 1521 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1522 scxtnum_el2)); 1523 } 1524 1525 if (is_feat_hcx_supported()) { 1526 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1527 } 1528 1529 if (is_feat_tcr2_supported()) { 1530 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1531 } 1532 1533 if (is_feat_sxpie_supported()) { 1534 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1535 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1536 } 1537 1538 if (is_feat_sxpoe_supported()) { 1539 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1540 } 1541 1542 if (is_feat_s2pie_supported()) { 1543 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1544 } 1545 1546 if (is_feat_gcs_supported()) { 1547 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1548 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1549 } 1550 1551 if (is_feat_sctlr2_supported()) { 1552 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1553 } 1554 } 1555 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1556 1557 #if IMAGE_BL31 1558 /********************************************************************************* 1559 * This function allows Architecture features asymmetry among cores. 1560 * TF-A assumes that all the cores in the platform has architecture feature parity 1561 * and hence the context is setup on different core (e.g. primary sets up the 1562 * context for secondary cores).This assumption may not be true for systems where 1563 * cores are not conforming to same Arch version or there is CPU Erratum which 1564 * requires certain feature to be be disabled only on a given core. 1565 * 1566 * This function is called on secondary cores to override any disparity in context 1567 * setup by primary, this would be called during warmboot path. 1568 *********************************************************************************/ 1569 void cm_handle_asymmetric_features(void) 1570 { 1571 cpu_context_t *ctx __maybe_unused = cm_get_context(NON_SECURE); 1572 1573 assert(ctx != NULL); 1574 1575 #if ENABLE_SPE_FOR_NS == FEAT_STATE_CHECK_ASYMMETRIC 1576 if (is_feat_spe_supported()) { 1577 spe_enable(ctx); 1578 } else { 1579 spe_disable(ctx); 1580 } 1581 #endif 1582 1583 #if ERRATA_A520_2938996 || ERRATA_X4_2726228 1584 if (check_if_affected_core() == ERRATA_APPLIES) { 1585 if (is_feat_trbe_supported()) { 1586 trbe_disable(ctx); 1587 } 1588 } 1589 #endif 1590 1591 #if ENABLE_FEAT_TCR2 == FEAT_STATE_CHECK_ASYMMETRIC 1592 el3_state_t *el3_state = get_el3state_ctx(ctx); 1593 u_register_t spsr = read_ctx_reg(el3_state, CTX_SPSR_EL3); 1594 1595 if (is_feat_tcr2_supported() && (GET_RW(spsr) == MODE_RW_64)) { 1596 tcr2_enable(ctx); 1597 } else { 1598 tcr2_disable(ctx); 1599 } 1600 #endif 1601 1602 } 1603 #endif 1604 1605 /******************************************************************************* 1606 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1607 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1608 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1609 * cm_prepare_el3_exit function. 1610 ******************************************************************************/ 1611 void cm_prepare_el3_exit_ns(void) 1612 { 1613 #if IMAGE_BL31 1614 /* 1615 * Check and handle Architecture feature asymmetry among cores. 1616 * 1617 * In warmboot path secondary cores context is initialized on core which 1618 * did CPU_ON SMC call, if there is feature asymmetry in these cores handle 1619 * it in this function call. 1620 * For Symmetric cores this is an empty function. 1621 */ 1622 cm_handle_asymmetric_features(); 1623 #endif 1624 1625 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1626 #if ENABLE_ASSERTIONS 1627 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1628 assert(ctx != NULL); 1629 1630 /* Assert that EL2 is used. */ 1631 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1632 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1633 (el_implemented(2U) != EL_IMPL_NONE)); 1634 #endif /* ENABLE_ASSERTIONS */ 1635 1636 /* Restore EL2 sysreg contexts */ 1637 cm_el2_sysregs_context_restore(NON_SECURE); 1638 cm_set_next_eret_context(NON_SECURE); 1639 #else 1640 cm_prepare_el3_exit(NON_SECURE); 1641 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1642 } 1643 1644 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1645 /******************************************************************************* 1646 * The next set of six functions are used by runtime services to save and restore 1647 * EL1 context on the 'cpu_context' structure for the specified security state. 1648 ******************************************************************************/ 1649 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1650 { 1651 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1652 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1653 1654 #if (!ERRATA_SPECULATIVE_AT) 1655 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1656 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1657 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1658 1659 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1660 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1661 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1662 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1663 write_el1_ctx_common(ctx, ttbr0_el1, read_ttbr0_el1()); 1664 write_el1_ctx_common(ctx, ttbr1_el1, read_ttbr1_el1()); 1665 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1666 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1667 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1668 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1669 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1670 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1671 write_el1_ctx_common(ctx, par_el1, read_par_el1()); 1672 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1673 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1674 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1675 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1676 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1677 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1678 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1679 1680 if (CTX_INCLUDE_AARCH32_REGS) { 1681 /* Save Aarch32 registers */ 1682 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1683 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1684 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1685 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1686 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1687 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1688 } 1689 1690 if (NS_TIMER_SWITCH) { 1691 /* Save NS Timer registers */ 1692 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1693 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1694 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1695 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1696 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1697 } 1698 1699 if (is_feat_mte2_supported()) { 1700 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1701 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1702 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1703 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1704 } 1705 1706 if (is_feat_ras_supported()) { 1707 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1708 } 1709 1710 if (is_feat_s1pie_supported()) { 1711 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1712 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1713 } 1714 1715 if (is_feat_s1poe_supported()) { 1716 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1717 } 1718 1719 if (is_feat_s2poe_supported()) { 1720 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1721 } 1722 1723 if (is_feat_tcr2_supported()) { 1724 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1725 } 1726 1727 if (is_feat_trf_supported()) { 1728 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1729 } 1730 1731 if (is_feat_csv2_2_supported()) { 1732 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1733 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1734 } 1735 1736 if (is_feat_gcs_supported()) { 1737 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1738 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1739 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1740 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1741 } 1742 1743 if (is_feat_the_supported()) { 1744 write_el1_ctx_the(ctx, rcwmask_el1, read_rcwmask_el1()); 1745 write_el1_ctx_the(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1746 } 1747 1748 if (is_feat_sctlr2_supported()) { 1749 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1750 } 1751 1752 } 1753 1754 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1755 { 1756 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1757 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1758 1759 #if (!ERRATA_SPECULATIVE_AT) 1760 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1761 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1762 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1763 1764 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1765 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1766 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1767 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1768 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1769 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1770 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1771 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1772 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1773 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1774 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1775 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1776 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1777 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1778 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1779 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1780 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1781 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1782 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1783 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1784 1785 if (CTX_INCLUDE_AARCH32_REGS) { 1786 /* Restore Aarch32 registers */ 1787 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1788 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1789 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1790 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1791 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1792 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1793 } 1794 1795 if (NS_TIMER_SWITCH) { 1796 /* Restore NS Timer registers */ 1797 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1798 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1799 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1800 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1801 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1802 } 1803 1804 if (is_feat_mte2_supported()) { 1805 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1806 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1807 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1808 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1809 } 1810 1811 if (is_feat_ras_supported()) { 1812 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1813 } 1814 1815 if (is_feat_s1pie_supported()) { 1816 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1817 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1818 } 1819 1820 if (is_feat_s1poe_supported()) { 1821 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1822 } 1823 1824 if (is_feat_s2poe_supported()) { 1825 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1826 } 1827 1828 if (is_feat_tcr2_supported()) { 1829 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1830 } 1831 1832 if (is_feat_trf_supported()) { 1833 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1834 } 1835 1836 if (is_feat_csv2_2_supported()) { 1837 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1838 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1839 } 1840 1841 if (is_feat_gcs_supported()) { 1842 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1843 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1844 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1845 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1846 } 1847 1848 if (is_feat_the_supported()) { 1849 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1850 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1851 } 1852 1853 if (is_feat_sctlr2_supported()) { 1854 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1855 } 1856 1857 } 1858 1859 /******************************************************************************* 1860 * The next couple of functions are used by runtime services to save and restore 1861 * EL1 context on the 'cpu_context' structure for the specified security state. 1862 ******************************************************************************/ 1863 void cm_el1_sysregs_context_save(uint32_t security_state) 1864 { 1865 cpu_context_t *ctx; 1866 1867 ctx = cm_get_context(security_state); 1868 assert(ctx != NULL); 1869 1870 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1871 1872 #if IMAGE_BL31 1873 if (security_state == SECURE) 1874 PUBLISH_EVENT(cm_exited_secure_world); 1875 else 1876 PUBLISH_EVENT(cm_exited_normal_world); 1877 #endif 1878 } 1879 1880 void cm_el1_sysregs_context_restore(uint32_t security_state) 1881 { 1882 cpu_context_t *ctx; 1883 1884 ctx = cm_get_context(security_state); 1885 assert(ctx != NULL); 1886 1887 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1888 1889 #if IMAGE_BL31 1890 if (security_state == SECURE) 1891 PUBLISH_EVENT(cm_entering_secure_world); 1892 else 1893 PUBLISH_EVENT(cm_entering_normal_world); 1894 #endif 1895 } 1896 1897 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1898 1899 /******************************************************************************* 1900 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1901 * given security state with the given entrypoint 1902 ******************************************************************************/ 1903 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1904 { 1905 cpu_context_t *ctx; 1906 el3_state_t *state; 1907 1908 ctx = cm_get_context(security_state); 1909 assert(ctx != NULL); 1910 1911 /* Populate EL3 state so that ERET jumps to the correct entry */ 1912 state = get_el3state_ctx(ctx); 1913 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1914 } 1915 1916 /******************************************************************************* 1917 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1918 * pertaining to the given security state 1919 ******************************************************************************/ 1920 void cm_set_elr_spsr_el3(uint32_t security_state, 1921 uintptr_t entrypoint, uint32_t spsr) 1922 { 1923 cpu_context_t *ctx; 1924 el3_state_t *state; 1925 1926 ctx = cm_get_context(security_state); 1927 assert(ctx != NULL); 1928 1929 /* Populate EL3 state so that ERET jumps to the correct entry */ 1930 state = get_el3state_ctx(ctx); 1931 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1932 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1933 } 1934 1935 /******************************************************************************* 1936 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1937 * pertaining to the given security state using the value and bit position 1938 * specified in the parameters. It preserves all other bits. 1939 ******************************************************************************/ 1940 void cm_write_scr_el3_bit(uint32_t security_state, 1941 uint32_t bit_pos, 1942 uint32_t value) 1943 { 1944 cpu_context_t *ctx; 1945 el3_state_t *state; 1946 u_register_t scr_el3; 1947 1948 ctx = cm_get_context(security_state); 1949 assert(ctx != NULL); 1950 1951 /* Ensure that the bit position is a valid one */ 1952 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1953 1954 /* Ensure that the 'value' is only a bit wide */ 1955 assert(value <= 1U); 1956 1957 /* 1958 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1959 * and set it to its new value. 1960 */ 1961 state = get_el3state_ctx(ctx); 1962 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1963 scr_el3 &= ~(1UL << bit_pos); 1964 scr_el3 |= (u_register_t)value << bit_pos; 1965 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1966 } 1967 1968 /******************************************************************************* 1969 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1970 * given security state. 1971 ******************************************************************************/ 1972 u_register_t cm_get_scr_el3(uint32_t security_state) 1973 { 1974 cpu_context_t *ctx; 1975 el3_state_t *state; 1976 1977 ctx = cm_get_context(security_state); 1978 assert(ctx != NULL); 1979 1980 /* Populate EL3 state so that ERET jumps to the correct entry */ 1981 state = get_el3state_ctx(ctx); 1982 return read_ctx_reg(state, CTX_SCR_EL3); 1983 } 1984 1985 /******************************************************************************* 1986 * This function is used to program the context that's used for exception 1987 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1988 * the required security state 1989 ******************************************************************************/ 1990 void cm_set_next_eret_context(uint32_t security_state) 1991 { 1992 cpu_context_t *ctx; 1993 1994 ctx = cm_get_context(security_state); 1995 assert(ctx != NULL); 1996 1997 cm_set_next_context(ctx); 1998 } 1999