Workaround for Cortex A78 erratum 1951500

Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before
acquire atomic in

Workaround for Cortex A78 erratum 1951500

Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics. This workaround
works on revisions r1p0 and r1p1, in r0p0 there is no workaround.

SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3

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Workaround for Cortex A78 erratum 1941498

Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1
register, the

Workaround for Cortex A78 erratum 1941498

Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1
register, there is a small performance cost (<0.5%) for setting this bit.

SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9

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Workaround for Cortex A76 erratum 1946160

Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions
of the A76 processor core. The workaround is to insert a DMB ST before
acquire ato

Workaround for Cortex A76 erratum 1946160

Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions
of the A76 processor core. The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics. This issue is
present in revisions r0p0 - r4p1 but this workaround only applies to
revisions r3p0 - r4p1, there is no workaround for older versions.

SDEN can be found here:
https://documentation-service.arm.com/static/5fbb77d7d77dd807b9a80cc1

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ief33779ee76a89ce2649812ae5214b86a139e327

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Add support for Neoverse-N2 CPUs.

Enable basic support for Neoverse-N2 CPUs.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8

Add support for Neoverse-N2 CPUs.

Enable basic support for Neoverse-N2 CPUs.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad

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Revert workaround for A77 erratum 1800714

This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.

This is the patch being revert

Revert workaround for A77 erratum 1800714

This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.

This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4686

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I8554c75d7217331c7effd781b5f7f49b781bbebe

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Revert workaround for A76 erratum 1800710

This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.

This is the patch being revert

Revert workaround for A76 erratum 1800710

This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.

This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4684

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I560749a5b55e22fbe49d3f428a8b9545d6bdaaf0

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Workaround for Cortex A77 erratum 1925769

Cortex A77 erratum 1925769 is a Cat B erratum, present in older
revisions of the Cortex A77 processor core. The workaround is to
set bit 8 in the ECTLR_EL1

Workaround for Cortex A77 erratum 1925769

Cortex A77 erratum 1925769 is a Cat B erratum, present in older
revisions of the Cortex A77 processor core. The workaround is to
set bit 8 in the ECTLR_EL1 register, there is a small performance cost
(<0.5%) for setting this bit.

SDEN can be found here:
https://documentation-service.arm.com/static/5f7c35d0d3be967f7be46d33

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I9cf0e0b5dc1e3e32e24279d2632c759cc7bd7ce9

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Merge changes from topics "rename-herculesae-a78ae", "rename-zeus-v1" into integration

* changes:
Rename Neoverse Zeus to Neoverse V1
Rename Cortex Hercules AE to Cortex 78 AE

Rename Neoverse Zeus to Neoverse V1

Change-Id: Ieb411e2f8092fa82062e619305b680673a8f184f
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

Rename Cortex Hercules AE to Cortex 78 AE

Change-Id: Ic0ca51a855660509264ff0d084c068e1421ad09a
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

Workaround for Cortex A76 erratum 1868343

Cortex A76 erratum 1868343 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core. The workaround is to
set a bit in the CPUACTLR_

Workaround for Cortex A76 erratum 1868343

Cortex A76 erratum 1868343 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core. The workaround is to
set a bit in the CPUACTLR_EL1 system register, which delays instruction
fetch after branch misprediction. This workaround will have a small
impact on performance.

This workaround is the same as workarounds for errata 1262606 and
1275112, so all 3 have been combined into one function call.

SDEN can be found here:
https://documentation-service.arm.com/static/5f2bed6d60a93e65927bc8e7

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7f2f9965f495540a1f84bb7dcc28aff45d6cee5d

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Merge "Workaround for Cortex A77 erratum 1508412" into integration

Merge changes I1ecbe5a1,Ib5945c37,Ic6b79648 into integration

* changes:
plat/arm: Add platform support for Morello
fdts: add device tree sources for morello platform
lib/cpus: add support for

Merge changes I1ecbe5a1,Ib5945c37,Ic6b79648 into integration

* changes:
plat/arm: Add platform support for Morello
fdts: add device tree sources for morello platform
lib/cpus: add support for Morello Rainier CPUs

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lib/cpus: add support for Morello Rainier CPUs

This patch adds CPU support for the Rainier CPU which is
derived from Neoverse N1 r4p0 CPU and implements the
Morello capability architecture.

Change-

lib/cpus: add support for Morello Rainier CPUs

This patch adds CPU support for the Rainier CPU which is
derived from Neoverse N1 r4p0 CPU and implements the
Morello capability architecture.

Change-Id: Ic6b796481da5a66504ecb0648879446edf4c69fb
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>

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Workaround for Cortex A77 erratum 1508412

Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0.
The workaround is a write sequence to several implementation defined
registers based

Workaround for Cortex A77 erratum 1508412

Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0.
The workaround is a write sequence to several implementation defined
registers based on A77 revision.

This errata is explained in this SDEN:
https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b

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arm_fpga: Add support for unknown MPIDs

This patch allows the system to fallback to a default CPU library
in case the MPID does not match with any of the supported ones.

This feature can be enabled

arm_fpga: Add support for unknown MPIDs

This patch allows the system to fallback to a default CPU library
in case the MPID does not match with any of the supported ones.

This feature can be enabled by setting SUPPORT_UNKNOWN_MPID build
option to 1 (enabled by default only on arm_fpga platform).

This feature can be very dangerous on a production image and
therefore it MUST be disabled for Release images.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I0df7ef2b012d7d60a4fd5de44dea1fbbb46881ba

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Workaround for Neoverse N1 erratum 1868343

Neoverse N1 erratum 1868343 is a Cat B erratum, present in older
revisions of the Neoverse N1 processor core. The workaround is to
set a bit in the CPUACT

Workaround for Neoverse N1 erratum 1868343

Neoverse N1 erratum 1868343 is a Cat B erratum, present in older
revisions of the Neoverse N1 processor core. The workaround is to
set a bit in the CPUACTLR_EL1 system register, which delays instruction
fetch after branch misprediction. This workaround will have a small
impact on performance.

SDEN can be found here:
https://documentation-service.arm.com/static/5f2c130260a93e65927bc92f

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I37da2b3b2da697701b883bff9a1eff2772352844

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Merge "lib: cpu: Check SCU presence in DSU before accessing DSU registers" into integration

lib: cpu: Check SCU presence in DSU before accessing DSU registers

The DSU contains system control registers in the SCU and L3 logic to
control the functionality of the cluster. If "DIRECT CONNECT"

lib: cpu: Check SCU presence in DSU before accessing DSU registers

The DSU contains system control registers in the SCU and L3 logic to
control the functionality of the cluster. If "DIRECT CONNECT" L3
memory system variant is used, there won't be any L3 cache,
snoop filter, and SCU logic present hence no system control register
will be present. Hence check SCU presence before accessing DSU register
for DSU_936184 errata.

Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Change-Id: I1ffa8afb0447ae3bd1032c9dd678d68021fe5a63

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cpus: denver: skip DCO enable/disable for recent SKUs

DCO is not supported by the SKUs released after MIDR_PN4. This
patch skips enabling or disabling the DCO on these SKUs.

Change-Id: Ic31a829de3a

cpus: denver: skip DCO enable/disable for recent SKUs

DCO is not supported by the SKUs released after MIDR_PN4. This
patch skips enabling or disabling the DCO on these SKUs.

Change-Id: Ic31a829de3ae560314d0fb5c5e867689d4ba243b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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lib: cpus: denver: add MIDR PN9 variant

This patch introduces support for PN9 variant for some
Denver based platforms.

Original change by: Hemant Nigam <hnigam@nvidia.com>

Signed-off-by: Kalyani C

lib: cpus: denver: add MIDR PN9 variant

This patch introduces support for PN9 variant for some
Denver based platforms.

Original change by: Hemant Nigam <hnigam@nvidia.com>

Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
Change-Id: I331cd3a083721fd1cd1b03f4a11b32fd306a21f3

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cpus: denver: introduce macro to declare cpu_ops

This patch introduces a macro to declare cpu_op for all Denver
SKUs.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ibcf88c3256fc5dca

cpus: denver: introduce macro to declare cpu_ops

This patch introduces a macro to declare cpu_op for all Denver
SKUs.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ibcf88c3256fc5dcaa1be855749ebd2c5c396c977

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lib: cpus: sanity check pointers before use

The cpu_ops structure contains a lot of function pointers. It
is a good idea to verify that the function pointer is not NULL
before executing it.

This pa

lib: cpus: sanity check pointers before use

The cpu_ops structure contains a lot of function pointers. It
is a good idea to verify that the function pointer is not NULL
before executing it.

This patch sanity checks each pointer before use to prevent any
unforeseen crashes. These checks have been enabled for debug
builds only.

Change-Id: Ib208331c20e60f0c7c582a20eb3d8cc40fb99d21
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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lib/cpus: Report AT speculative erratum workaround

Reported the status (applies, missing) of AT speculative workaround
which is applicable for below CPUs.

+---------+--------------+
| Errata |

lib/cpus: Report AT speculative erratum workaround

Reported the status (applies, missing) of AT speculative workaround
which is applicable for below CPUs.

+---------+--------------+
| Errata | CPU |
+=========+==============+
| 1165522 | Cortex-A76 |
+---------+--------------+
| 1319367 | Cortex-A72 |
+---------+--------------+
| 1319537 | Cortex-A57 |
+---------+--------------+
| 1530923 | Cortex-A55 |
+---------+--------------+
| 1530924 | Cortex-A53 |
+---------+--------------+

Also, changes are done to enable common macro 'ERRATA_SPECULATIVE_AT'
if AT speculative errata workaround is enabled for any of the above
CPUs using 'ERRATA_*' CPU specific build macro.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I3e6a5316a2564071f3920c3ce9ae9a29adbe435b

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lib: cpus: denver: add some MIDR values

This patch adds support for additional Denver MIDRs to
cover all the current SKUs.

Change-Id: I85d0ffe9b3cb351f430ca7d7065a2609968a7a28
Signed-off-by: Alex V

lib: cpus: denver: add some MIDR values

This patch adds support for additional Denver MIDRs to
cover all the current SKUs.

Change-Id: I85d0ffe9b3cb351f430ca7d7065a2609968a7a28
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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