Merge pull request #870 from douglas-raillard-arm/dr/remove_asm_signed_test

Replace ASM signed tests with unsigned

Add workaround for ARM Cortex-A53 erratum 855873

ARM erratum 855873 applies to all Cortex-A53 CPUs.
The recommended workaround is to promote "data cache clean"
instructions to "data cache clean and

Add workaround for ARM Cortex-A53 erratum 855873

ARM erratum 855873 applies to all Cortex-A53 CPUs.
The recommended workaround is to promote "data cache clean"
instructions to "data cache clean and invalidate" instructions.
For core revisions of r0p3 and later this can be done by setting a bit
in the CPUACTLR_EL1 register, so that hardware takes care of the promotion.
As CPUACTLR_EL1 is both IMPLEMENTATION DEFINED and can be trapped to EL3,
we set the bit in firmware.
Also we dump this register upon crashing to provide more debug
information.

Enable the workaround for the Juno boards.

Change-Id: I3840114291958a406574ab6c49b01a9d9847fec8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Replace ASM signed tests with unsigned

ge, lt, gt and le condition codes in assembly provide a signed test
whereas hs, lo, hi and ls provide the unsigned counterpart. Signed tests
should only be use

Replace ASM signed tests with unsigned

ge, lt, gt and le condition codes in assembly provide a signed test
whereas hs, lo, hi and ls provide the unsigned counterpart. Signed tests
should only be used when strictly necessary, as using them on logically
unsigned values can lead to inverting the test for high enough values.
All offsets, addresses and usually counters are actually unsigned
values, and should be tested as such.

Replace the occurrences of signed condition codes where it was
unnecessary by an unsigned test as the unsigned tests allow the full
range of unsigned values to be used without inverting the result with
some large operands.

Change-Id: I58b7e98d03e3a4476dfb45230311f296d224980a
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

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Merge pull request #856 from antonio-nino-diaz-arm/an/dynamic-xlat

Introduce version 2 of the translation tables library

Apply workaround for errata 813419 of Cortex-A57

TLBI instructions for EL3 won't have the desired effect under specific
circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and
TLBI tw

Apply workaround for errata 813419 of Cortex-A57

TLBI instructions for EL3 won't have the desired effect under specific
circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and
TLBI twice each time.

Even though this errata is only needed in r0p0, the current errata
framework is not prepared to apply run-time workarounds. The current one
is always applied if compiled in, regardless of the CPU or its revision.

This errata has been enabled for Juno.

The `DSB` instruction used when initializing the translation tables has
been changed to `DSB ISH` as an optimization and to be consistent with
the barriers used for the workaround.

Change-Id: Ifc1d70b79cb5e0d87e90d88d376a59385667d338
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #853 from vwadekar/tegra-changes-from-downstream-v3

Tegra changes from downstream v3

cpus: denver: remove barrier from denver_enable_dco()

This patch removes unnecessary `isb` from the enable DCO sequence as
there is no need to synchronize this operation.

Change-Id: I0191e684bbc7fd

cpus: denver: remove barrier from denver_enable_dco()

This patch removes unnecessary `isb` from the enable DCO sequence as
there is no need to synchronize this operation.

Change-Id: I0191e684bbc7fdba635c3afbc4e4ecd793b6f06f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #848 from douglas-raillard-arm/dr/improve_errata_doc

Clarify errata ERRATA_A53_836870 documentation

cpus: denver: disable DCO operations from platform code

This patch moves the code to disable DCO operations out from common
CPU files. This allows the platform code to call thsi API as and
when requ

cpus: denver: disable DCO operations from platform code

This patch moves the code to disable DCO operations out from common
CPU files. This allows the platform code to call thsi API as and
when required. There are certain CPU power down states which require
the DCO to be kept ON and platforms can decide selectively now.

Change-Id: Icb946fe2545a7d8c5903c420d1ee169c4921a2d1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Clarify errata ERRATA_A53_836870 documentation

The errata is enabled by default on r0p4, which is confusing given that
we state we do not enable errata by default.

This patch clarifies this sentenc

Clarify errata ERRATA_A53_836870 documentation

The errata is enabled by default on r0p4, which is confusing given that
we state we do not enable errata by default.

This patch clarifies this sentence by saying it is enabled in hardware
by default.

Change-Id: I70a062d93e1da2416d5f6d5776a77a659da737aa
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

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cpus: Add support for all Denver variants

This patch adds support for all variants of the Denver CPUs. The
variants export their cpu_ops to allow all Denver platforms to run
the Trusted Firmware sta

cpus: Add support for all Denver variants

This patch adds support for all variants of the Denver CPUs. The
variants export their cpu_ops to allow all Denver platforms to run
the Trusted Firmware stack.

Change-Id: I1488813ddfd506ffe363d8a32cda1b575e437035
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Report errata workaround status to console

The errata reporting policy is as follows:

- If an errata workaround is enabled:

- If it applies (i.e. the CPU is affected by the errata), an INFO

Report errata workaround status to console

The errata reporting policy is as follows:

- If an errata workaround is enabled:

- If it applies (i.e. the CPU is affected by the errata), an INFO
message is printed, confirming that the errata workaround has been
applied.

- If it does not apply, a VERBOSE message is printed, confirming
that the errata workaround has been skipped.

- If an errata workaround is not enabled, but would have applied had
it been, a WARN message is printed, alerting that errata workaround
is missing.

The CPU errata messages are printed by both BL1 (primary CPU only) and
runtime firmware on debug builds, once for each CPU/errata combination.

Relevant output from Juno r1 console when ARM Trusted Firmware is built
with PLAT=juno LOG_LEVEL=50 DEBUG=1:

VERBOSE: BL1: cortex_a57: errata workaround for 806969 was not applied
VERBOSE: BL1: cortex_a57: errata workaround for 813420 was not applied
INFO: BL1: cortex_a57: errata workaround for disable_ldnp_overread was applied
WARNING: BL1: cortex_a57: errata workaround for 826974 was missing!
WARNING: BL1: cortex_a57: errata workaround for 826977 was missing!
WARNING: BL1: cortex_a57: errata workaround for 828024 was missing!
WARNING: BL1: cortex_a57: errata workaround for 829520 was missing!
WARNING: BL1: cortex_a57: errata workaround for 833471 was missing!
...
VERBOSE: BL31: cortex_a57: errata workaround for 806969 was not applied
VERBOSE: BL31: cortex_a57: errata workaround for 813420 was not applied
INFO: BL31: cortex_a57: errata workaround for disable_ldnp_overread was applied
WARNING: BL31: cortex_a57: errata workaround for 826974 was missing!
WARNING: BL31: cortex_a57: errata workaround for 826977 was missing!
WARNING: BL31: cortex_a57: errata workaround for 828024 was missing!
WARNING: BL31: cortex_a57: errata workaround for 829520 was missing!
WARNING: BL31: cortex_a57: errata workaround for 833471 was missing!
...
VERBOSE: BL31: cortex_a53: errata workaround for 826319 was not applied
INFO: BL31: cortex_a53: errata workaround for disable_non_temporal_hint was applied

Also update documentation.

Change-Id: Iccf059d3348adb876ca121cdf5207bdbbacf2aba
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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Use #ifdef for IMAGE_BL* instead of #if

One nasty part of ATF is some of boolean macros are always defined
as 1 or 0, and the rest of them are only defined under certain
conditions.

For the former

Use #ifdef for IMAGE_BL* instead of #if

One nasty part of ATF is some of boolean macros are always defined
as 1 or 0, and the rest of them are only defined under certain
conditions.

For the former group, "#if FOO" or "#if !FOO" must be used because
"#ifdef FOO" is always true. (Options passed by $(call add_define,)
are the cases.)

For the latter, "#ifdef FOO" or "#ifndef FOO" should be used because
checking the value of an undefined macro is strange.

Here, IMAGE_BL* is handled by make_helpers/build_macro.mk like
follows:

$(eval IMAGE := IMAGE_BL$(call uppercase,$(3)))

$(OBJ): $(2)
@echo " CC $$<"
$$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) -D$(IMAGE) -c $$< -o $$@

This means, IMAGE_BL* is defined when building the corresponding
image, but *undefined* for the other images.

So, IMAGE_BL* belongs to the latter group where we should use #ifdef
or #ifndef.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Correct system include order

NOTE - this is patch does not address all occurrences of system
includes not being in alphabetical order, just this one case.

Change-Id: I3cd23702d69b1f60a4a9dd7fd4ae27

Correct system include order

NOTE - this is patch does not address all occurrences of system
includes not being in alphabetical order, just this one case.

Change-Id: I3cd23702d69b1f60a4a9dd7fd4ae27418f15b7a3

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Add provision to extend CPU operations at more levels

Various CPU drivers in ARM Trusted Firmware register functions to handle
power-down operations. At present, separate functions are registered to

Add provision to extend CPU operations at more levels

Various CPU drivers in ARM Trusted Firmware register functions to handle
power-down operations. At present, separate functions are registered to
power down individual cores and clusters.

This scheme operates on the basis of core and cluster, and doesn't cater
for extending the hierarchy for power-down operations. For example,
future CPUs might support multiple threads which might need powering
down individually.

This patch therefore reworks the CPU operations framework to allow for
registering power down handlers on specific level basis. Henceforth:

- Generic code invokes CPU power down operations by the level
required.

- CPU drivers explicitly mention CPU_NO_RESET_FUNC when the CPU has no
reset function.

- CPU drivers register power down handlers as a list: a mandatory
handler for level 0, and optional handlers for higher levels.

All existing CPU drivers are adapted to the new CPU operations framework
without needing any functional changes within.

Also update firmware design guide.

Change-Id: I1826842d37a9e60a9e85fdcee7b4b8f6bc1ad043
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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AArch32: Fix the stack alignment issue

The AArch32 Procedure call Standard mandates that the stack must be aligned
to 8 byte boundary at external interfaces. This patch does the required
changes.

T

AArch32: Fix the stack alignment issue

The AArch32 Procedure call Standard mandates that the stack must be aligned
to 8 byte boundary at external interfaces. This patch does the required
changes.

This problem was detected when a crash was encountered in
`psci_print_power_domain_map()` while printing 64 bit values. Aligning
the stack to 8 byte boundary resolved the problem.

Fixes ARM-Software/tf-issues#437

Change-Id: I517bd8203601bb88e9311bd36d477fb7b3efb292
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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AArch32: Add support for ARM Cortex-A32 MPCore Processor

This patch adds ARM Cortex-A32 MPCore Processor support
in the CPU specific operations framework. It also includes
this support for the Base

AArch32: Add support for ARM Cortex-A32 MPCore Processor

This patch adds ARM Cortex-A32 MPCore Processor support
in the CPU specific operations framework. It also includes
this support for the Base FVP port.

Change-Id: If3697b88678df737c29f79cf3fa1ea2cb6fa565d

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AArch32: Common changes needed for BL1/BL2

This patch adds common changes to support AArch32 state in
BL1 and BL2. Following are the changes:

* Added functions for disabling MMU from Secure state.

AArch32: Common changes needed for BL1/BL2

This patch adds common changes to support AArch32 state in
BL1 and BL2. Following are the changes:

* Added functions for disabling MMU from Secure state.
* Added AArch32 specific SMC function.
* Added semihosting support.
* Added reporting of unhandled exceptions.
* Added uniprocessor stack support.
* Added `el3_entrypoint_common` macro that can be
shared by BL1 and BL32 (SP_MIN) BL stages. The
`el3_entrypoint_common` is similar to the AArch64
counterpart with the main difference in the assembly
instructions and the registers that are relevant to
AArch32 execution state.
* Enabled `LOAD_IMAGE_V2` flag in Makefile for
`ARCH=aarch32` and added check to make sure that
platform has not overridden to disable it.

Change-Id: I33c6d8dfefb2e5d142fdfd06a0f4a7332962e1a3

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AArch32: Add support in TF libraries

This patch adds AArch32 support to cpu ops, context management,
per-cpu data and spinlock libraries. The `entrypoint_info`
structure is modified to add support f

AArch32: Add support in TF libraries

This patch adds AArch32 support to cpu ops, context management,
per-cpu data and spinlock libraries. The `entrypoint_info`
structure is modified to add support for AArch32 register
arguments. The CPU operations for AEM generic cpu in AArch32
mode is also added.

Change-Id: I1e52e79f498661d8f31f1e7b3a29e222bc7a4483

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bl31: Add error reporting registers

This patch adds cpumerrsr_el1 and l2merrsr_el1 to the register dump on
error for applicable CPUs.

These registers hold the ECC errors on L1 and L2 caches.

This

bl31: Add error reporting registers

This patch adds cpumerrsr_el1 and l2merrsr_el1 to the register dump on
error for applicable CPUs.

These registers hold the ECC errors on L1 and L2 caches.

This patch updates the A53, A57, A72, A73 (l2merrsr_el1 only) CPU libraries.

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>

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Add support for ARM Cortex-A73 MPCore Processor

This patch adds ARM Cortex-A73 MPCore Processor support
in the CPU specific operations framework. It also includes
this support for the Base FVP port.

Add support for ARM Cortex-A73 MPCore Processor

This patch adds ARM Cortex-A73 MPCore Processor support
in the CPU specific operations framework. It also includes
this support for the Base FVP port.

Change-Id: I0e26b594f2ec1d28eb815db9810c682e3885716d

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Add support for Cortex-A57 erratum 833471 workaround

Change-Id: I86ac81ffd7cd094ce68c4cceb01c16563671a063

Add support for Cortex-A57 erratum 826977 workaround

Change-Id: Icaacd19c4cef9c10d02adcc2f84a4d7c97d4bcfa

Add support for Cortex-A57 erratum 829520 workaround

Change-Id: Ia2ce8aa752efb090cfc734c1895c8f2539e82439

Add support for Cortex-A57 erratum 828024 workaround

Change-Id: I632a8c5bb517ff89c69268e865be33101059be7d