1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <dram.h> 32 #include <plat_private.h> 33 #include <soc.h> 34 #include <rk3399_def.h> 35 36 __sramdata struct rk3399_sdram_params sdram_config; 37 38 void dram_init(void) 39 { 40 uint32_t os_reg2_val, i; 41 42 os_reg2_val = mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)); 43 sdram_config.dramtype = SYS_REG_DEC_DDRTYPE(os_reg2_val); 44 sdram_config.num_channels = SYS_REG_DEC_NUM_CH(os_reg2_val); 45 sdram_config.stride = (mmio_read_32(SGRF_BASE + SGRF_SOC_CON3_7(4)) >> 46 10) & 0x1f; 47 48 for (i = 0; i < 2; i++) { 49 struct rk3399_sdram_channel *ch = &sdram_config.ch[i]; 50 struct rk3399_msch_timings *noc = &ch->noc_timings; 51 52 if (!(SYS_REG_DEC_CHINFO(os_reg2_val, i))) 53 continue; 54 55 ch->rank = SYS_REG_DEC_RANK(os_reg2_val, i); 56 ch->col = SYS_REG_DEC_COL(os_reg2_val, i); 57 ch->bk = SYS_REG_DEC_BK(os_reg2_val, i); 58 ch->bw = SYS_REG_DEC_BW(os_reg2_val, i); 59 ch->dbw = SYS_REG_DEC_DBW(os_reg2_val, i); 60 ch->row_3_4 = SYS_REG_DEC_ROW_3_4(os_reg2_val, i); 61 ch->cs0_row = SYS_REG_DEC_CS0_ROW(os_reg2_val, i); 62 ch->cs1_row = SYS_REG_DEC_CS1_ROW(os_reg2_val, i); 63 ch->ddrconfig = mmio_read_32(MSCH_BASE(i) + MSCH_DEVICECONF); 64 65 noc->ddrtiminga0.d32 = mmio_read_32(MSCH_BASE(i) + 66 MSCH_DDRTIMINGA0); 67 noc->ddrtimingb0.d32 = mmio_read_32(MSCH_BASE(i) + 68 MSCH_DDRTIMINGB0); 69 noc->ddrtimingc0.d32 = mmio_read_32(MSCH_BASE(i) + 70 MSCH_DDRTIMINGC0); 71 noc->devtodev0.d32 = mmio_read_32(MSCH_BASE(i) + 72 MSCH_DEVTODEV0); 73 noc->ddrmode.d32 = mmio_read_32(MSCH_BASE(i) + MSCH_DDRMODE); 74 noc->agingx0 = mmio_read_32(MSCH_BASE(i) + MSCH_AGINGX0); 75 } 76 } 77