1/* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <arch.h> 31#include <asm_macros.S> 32#include <assert_macros.S> 33#include <bl_common.h> 34#include <cortex_a57.h> 35#include <cpu_macros.S> 36#include <debug.h> 37#include <plat_macros.S> 38 39 /* --------------------------------------------- 40 * Disable L1 data cache and unified L2 cache 41 * --------------------------------------------- 42 */ 43func cortex_a57_disable_dcache 44 mrs x1, sctlr_el3 45 bic x1, x1, #SCTLR_C_BIT 46 msr sctlr_el3, x1 47 isb 48 ret 49endfunc cortex_a57_disable_dcache 50 51 /* --------------------------------------------- 52 * Disable all types of L2 prefetches. 53 * --------------------------------------------- 54 */ 55func cortex_a57_disable_l2_prefetch 56 mrs x0, CPUECTLR_EL1 57 orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT 58 mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK 59 orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK 60 bic x0, x0, x1 61 msr CPUECTLR_EL1, x0 62 isb 63 dsb ish 64 ret 65endfunc cortex_a57_disable_l2_prefetch 66 67 /* --------------------------------------------- 68 * Disable intra-cluster coherency 69 * --------------------------------------------- 70 */ 71func cortex_a57_disable_smp 72 mrs x0, CPUECTLR_EL1 73 bic x0, x0, #CPUECTLR_SMP_BIT 74 msr CPUECTLR_EL1, x0 75 ret 76endfunc cortex_a57_disable_smp 77 78 /* --------------------------------------------- 79 * Disable debug interfaces 80 * --------------------------------------------- 81 */ 82func cortex_a57_disable_ext_debug 83 mov x0, #1 84 msr osdlr_el1, x0 85 isb 86 dsb sy 87 ret 88endfunc cortex_a57_disable_ext_debug 89 90 /* -------------------------------------------------- 91 * Errata Workaround for Cortex A57 Errata #806969. 92 * This applies only to revision r0p0 of Cortex A57. 93 * Inputs: 94 * x0: variant[4:7] and revision[0:3] of current cpu. 95 * Shall clobber: x0-x17 96 * -------------------------------------------------- 97 */ 98func errata_a57_806969_wa 99 /* 100 * Compare x0 against revision r0p0 101 */ 102 mov x17, x30 103 bl check_errata_806969 104 cbz x0, 1f 105 mrs x1, CPUACTLR_EL1 106 orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA 107 msr CPUACTLR_EL1, x1 1081: 109 ret x17 110endfunc errata_a57_806969_wa 111 112func check_errata_806969 113 mov x1, #0x00 114 b cpu_rev_var_ls 115endfunc check_errata_806969 116 117 /* --------------------------------------------------- 118 * Errata Workaround for Cortex A57 Errata #813420. 119 * This applies only to revision r0p0 of Cortex A57. 120 * Inputs: 121 * x0: variant[4:7] and revision[0:3] of current cpu. 122 * Shall clobber: x0-x17 123 * --------------------------------------------------- 124 */ 125func errata_a57_813420_wa 126 /* 127 * Compare x0 against revision r0p0 128 */ 129 mov x17, x30 130 bl check_errata_813420 131 cbz x0, 1f 132 mrs x1, CPUACTLR_EL1 133 orr x1, x1, #CPUACTLR_DCC_AS_DCCI 134 msr CPUACTLR_EL1, x1 1351: 136 ret x17 137endfunc errata_a57_813420_wa 138 139func check_errata_813420 140 mov x1, #0x00 141 b cpu_rev_var_ls 142endfunc check_errata_813420 143 144 /* -------------------------------------------------------------------- 145 * Disable the over-read from the LDNP instruction. 146 * 147 * This applies to all revisions <= r1p2. The performance degradation 148 * observed with LDNP/STNP has been fixed on r1p3 and onwards. 149 * 150 * Inputs: 151 * x0: variant[4:7] and revision[0:3] of current cpu. 152 * Shall clobber: x0-x17 153 * --------------------------------------------------------------------- 154 */ 155func a57_disable_ldnp_overread 156 /* 157 * Compare x0 against revision r1p2 158 */ 159 mov x17, x30 160 bl check_errata_disable_ldnp_overread 161 cbz x0, 1f 162 mrs x1, CPUACTLR_EL1 163 orr x1, x1, #CPUACTLR_DIS_OVERREAD 164 msr CPUACTLR_EL1, x1 1651: 166 ret x17 167endfunc a57_disable_ldnp_overread 168 169func check_errata_disable_ldnp_overread 170 mov x1, #0x12 171 b cpu_rev_var_ls 172endfunc check_errata_disable_ldnp_overread 173 174 /* --------------------------------------------------- 175 * Errata Workaround for Cortex A57 Errata #826974. 176 * This applies only to revision <= r1p1 of Cortex A57. 177 * Inputs: 178 * x0: variant[4:7] and revision[0:3] of current cpu. 179 * Shall clobber: x0-x17 180 * --------------------------------------------------- 181 */ 182func errata_a57_826974_wa 183 /* 184 * Compare x0 against revision r1p1 185 */ 186 mov x17, x30 187 bl check_errata_826974 188 cbz x0, 1f 189 mrs x1, CPUACTLR_EL1 190 orr x1, x1, #CPUACTLR_DIS_LOAD_PASS_DMB 191 msr CPUACTLR_EL1, x1 1921: 193 ret x17 194endfunc errata_a57_826974_wa 195 196func check_errata_826974 197 mov x1, #0x11 198 b cpu_rev_var_ls 199endfunc check_errata_826974 200 201 /* --------------------------------------------------- 202 * Errata Workaround for Cortex A57 Errata #826977. 203 * This applies only to revision <= r1p1 of Cortex A57. 204 * Inputs: 205 * x0: variant[4:7] and revision[0:3] of current cpu. 206 * Shall clobber: x0-x17 207 * --------------------------------------------------- 208 */ 209func errata_a57_826977_wa 210 /* 211 * Compare x0 against revision r1p1 212 */ 213 mov x17, x30 214 bl check_errata_826977 215 cbz x0, 1f 216 mrs x1, CPUACTLR_EL1 217 orr x1, x1, #CPUACTLR_GRE_NGRE_AS_NGNRE 218 msr CPUACTLR_EL1, x1 2191: 220 ret x17 221endfunc errata_a57_826977_wa 222 223func check_errata_826977 224 mov x1, #0x11 225 b cpu_rev_var_ls 226endfunc check_errata_826977 227 228 /* --------------------------------------------------- 229 * Errata Workaround for Cortex A57 Errata #828024. 230 * This applies only to revision <= r1p1 of Cortex A57. 231 * Inputs: 232 * x0: variant[4:7] and revision[0:3] of current cpu. 233 * Shall clobber: x0-x17 234 * --------------------------------------------------- 235 */ 236func errata_a57_828024_wa 237 /* 238 * Compare x0 against revision r1p1 239 */ 240 mov x17, x30 241 bl check_errata_828024 242 cbz x0, 1f 243 mrs x1, CPUACTLR_EL1 244 /* 245 * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 246 * instructions here because the resulting bitmask doesn't fit in a 247 * 16-bit value so it cannot be encoded in a single instruction. 248 */ 249 orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA 250 orr x1, x1, #(CPUACTLR_DIS_L1_STREAMING | CPUACTLR_DIS_STREAMING) 251 msr CPUACTLR_EL1, x1 2521: 253 ret x17 254endfunc errata_a57_828024_wa 255 256func check_errata_828024 257 mov x1, #0x11 258 b cpu_rev_var_ls 259endfunc check_errata_828024 260 261 /* --------------------------------------------------- 262 * Errata Workaround for Cortex A57 Errata #829520. 263 * This applies only to revision <= r1p2 of Cortex A57. 264 * Inputs: 265 * x0: variant[4:7] and revision[0:3] of current cpu. 266 * Shall clobber: x0-x17 267 * --------------------------------------------------- 268 */ 269func errata_a57_829520_wa 270 /* 271 * Compare x0 against revision r1p2 272 */ 273 mov x17, x30 274 bl check_errata_829520 275 cbz x0, 1f 276 mrs x1, CPUACTLR_EL1 277 orr x1, x1, #CPUACTLR_DIS_INDIRECT_PREDICTOR 278 msr CPUACTLR_EL1, x1 2791: 280 ret x17 281endfunc errata_a57_829520_wa 282 283func check_errata_829520 284 mov x1, #0x12 285 b cpu_rev_var_ls 286endfunc check_errata_829520 287 288 /* --------------------------------------------------- 289 * Errata Workaround for Cortex A57 Errata #833471. 290 * This applies only to revision <= r1p2 of Cortex A57. 291 * Inputs: 292 * x0: variant[4:7] and revision[0:3] of current cpu. 293 * Shall clobber: x0-x17 294 * --------------------------------------------------- 295 */ 296func errata_a57_833471_wa 297 /* 298 * Compare x0 against revision r1p2 299 */ 300 mov x17, x30 301 bl check_errata_833471 302 cbz x0, 1f 303 mrs x1, CPUACTLR_EL1 304 orr x1, x1, #CPUACTLR_FORCE_FPSCR_FLUSH 305 msr CPUACTLR_EL1, x1 3061: 307 ret x17 308endfunc errata_a57_833471_wa 309 310func check_errata_833471 311 mov x1, #0x12 312 b cpu_rev_var_ls 313endfunc check_errata_833471 314 315 /* ------------------------------------------------- 316 * The CPU Ops reset function for Cortex-A57. 317 * Shall clobber: x0-x19 318 * ------------------------------------------------- 319 */ 320func cortex_a57_reset_func 321 mov x19, x30 322 bl cpu_get_rev_var 323 mov x18, x0 324 325#if ERRATA_A57_806969 326 mov x0, x18 327 bl errata_a57_806969_wa 328#endif 329 330#if ERRATA_A57_813420 331 mov x0, x18 332 bl errata_a57_813420_wa 333#endif 334 335#if A57_DISABLE_NON_TEMPORAL_HINT 336 mov x0, x18 337 bl a57_disable_ldnp_overread 338#endif 339 340#if ERRATA_A57_826974 341 mov x0, x18 342 bl errata_a57_826974_wa 343#endif 344 345#if ERRATA_A57_826977 346 mov x0, x18 347 bl errata_a57_826977_wa 348#endif 349 350#if ERRATA_A57_828024 351 mov x0, x18 352 bl errata_a57_828024_wa 353#endif 354 355#if ERRATA_A57_829520 356 mov x0, x18 357 bl errata_a57_829520_wa 358#endif 359 360#if ERRATA_A57_833471 361 mov x0, x18 362 bl errata_a57_833471_wa 363#endif 364 365 /* --------------------------------------------- 366 * Enable the SMP bit. 367 * --------------------------------------------- 368 */ 369 mrs x0, CPUECTLR_EL1 370 orr x0, x0, #CPUECTLR_SMP_BIT 371 msr CPUECTLR_EL1, x0 372 isb 373 ret x19 374endfunc cortex_a57_reset_func 375 376 /* ---------------------------------------------------- 377 * The CPU Ops core power down function for Cortex-A57. 378 * ---------------------------------------------------- 379 */ 380func cortex_a57_core_pwr_dwn 381 mov x18, x30 382 383 /* --------------------------------------------- 384 * Turn off caches. 385 * --------------------------------------------- 386 */ 387 bl cortex_a57_disable_dcache 388 389 /* --------------------------------------------- 390 * Disable the L2 prefetches. 391 * --------------------------------------------- 392 */ 393 bl cortex_a57_disable_l2_prefetch 394 395 /* --------------------------------------------- 396 * Flush L1 caches. 397 * --------------------------------------------- 398 */ 399 mov x0, #DCCISW 400 bl dcsw_op_level1 401 402 /* --------------------------------------------- 403 * Come out of intra cluster coherency 404 * --------------------------------------------- 405 */ 406 bl cortex_a57_disable_smp 407 408 /* --------------------------------------------- 409 * Force the debug interfaces to be quiescent 410 * --------------------------------------------- 411 */ 412 mov x30, x18 413 b cortex_a57_disable_ext_debug 414endfunc cortex_a57_core_pwr_dwn 415 416 /* ------------------------------------------------------- 417 * The CPU Ops cluster power down function for Cortex-A57. 418 * ------------------------------------------------------- 419 */ 420func cortex_a57_cluster_pwr_dwn 421 mov x18, x30 422 423 /* --------------------------------------------- 424 * Turn off caches. 425 * --------------------------------------------- 426 */ 427 bl cortex_a57_disable_dcache 428 429 /* --------------------------------------------- 430 * Disable the L2 prefetches. 431 * --------------------------------------------- 432 */ 433 bl cortex_a57_disable_l2_prefetch 434 435#if !SKIP_A57_L1_FLUSH_PWR_DWN 436 /* ------------------------------------------------- 437 * Flush the L1 caches. 438 * ------------------------------------------------- 439 */ 440 mov x0, #DCCISW 441 bl dcsw_op_level1 442#endif 443 /* --------------------------------------------- 444 * Disable the optional ACP. 445 * --------------------------------------------- 446 */ 447 bl plat_disable_acp 448 449 /* ------------------------------------------------- 450 * Flush the L2 caches. 451 * ------------------------------------------------- 452 */ 453 mov x0, #DCCISW 454 bl dcsw_op_level2 455 456 /* --------------------------------------------- 457 * Come out of intra cluster coherency 458 * --------------------------------------------- 459 */ 460 bl cortex_a57_disable_smp 461 462 /* --------------------------------------------- 463 * Force the debug interfaces to be quiescent 464 * --------------------------------------------- 465 */ 466 mov x30, x18 467 b cortex_a57_disable_ext_debug 468endfunc cortex_a57_cluster_pwr_dwn 469 470#if REPORT_ERRATA 471/* 472 * Errata printing function for Cortex A57. Must follow AAPCS. 473 */ 474func cortex_a57_errata_report 475 stp x8, x30, [sp, #-16]! 476 477 bl cpu_get_rev_var 478 mov x8, x0 479 480 /* 481 * Report all errata. The revision-variant information is passed to 482 * checking functions of each errata. 483 */ 484 report_errata ERRATA_A57_806969, cortex_a57, 806969 485 report_errata ERRATA_A57_813420, cortex_a57, 813420 486 report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ 487 disable_ldnp_overread 488 report_errata ERRATA_A57_826974, cortex_a57, 826974 489 report_errata ERRATA_A57_826977, cortex_a57, 826977 490 report_errata ERRATA_A57_828024, cortex_a57, 828024 491 report_errata ERRATA_A57_829520, cortex_a57, 829520 492 report_errata ERRATA_A57_833471, cortex_a57, 833471 493 494 ldp x8, x30, [sp], #16 495 ret 496endfunc cortex_a57_errata_report 497#endif 498 499 /* --------------------------------------------- 500 * This function provides cortex_a57 specific 501 * register information for crash reporting. 502 * It needs to return with x6 pointing to 503 * a list of register names in ascii and 504 * x8 - x15 having values of registers to be 505 * reported. 506 * --------------------------------------------- 507 */ 508.section .rodata.cortex_a57_regs, "aS" 509cortex_a57_regs: /* The ascii list of register names to be reported */ 510 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 511 512func cortex_a57_cpu_reg_dump 513 adr x6, cortex_a57_regs 514 mrs x8, CPUECTLR_EL1 515 mrs x9, CPUMERRSR_EL1 516 mrs x10, L2MERRSR_EL1 517 ret 518endfunc cortex_a57_cpu_reg_dump 519 520 521declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \ 522 cortex_a57_reset_func, \ 523 cortex_a57_core_pwr_dwn, \ 524 cortex_a57_cluster_pwr_dwn 525