1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <debug.h> 34 #include <delay_timer.h> 35 #include <mmio.h> 36 #include <platform.h> 37 #include <platform_def.h> 38 #include <psci.h> 39 #include <pmc.h> 40 #include <flowctrl.h> 41 #include <tegra_def.h> 42 #include <tegra_private.h> 43 44 /* 45 * Register used to clear CPU reset signals. Each CPU has two reset 46 * signals: CPU reset (3:0) and Core reset (19:16). 47 */ 48 #define CPU_CMPLX_RESET_CLR 0x454 49 #define CPU_CORE_RESET_MASK 0x10001 50 51 /* Clock and Reset controller registers for system clock's settings */ 52 #define SCLK_RATE 0x30 53 #define SCLK_BURST_POLICY 0x28 54 #define SCLK_BURST_POLICY_DEFAULT 0x10000000 55 56 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; 57 58 int32_t tegra_soc_validate_power_state(unsigned int power_state, 59 psci_power_state_t *req_state) 60 { 61 int state_id = psci_get_pstate_id(power_state); 62 63 /* Sanity check the requested state id */ 64 switch (state_id) { 65 case PSTATE_ID_CORE_POWERDN: 66 /* 67 * Core powerdown request only for afflvl 0 68 */ 69 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; 70 71 break; 72 73 case PSTATE_ID_CLUSTER_IDLE: 74 case PSTATE_ID_CLUSTER_POWERDN: 75 /* 76 * Cluster powerdown/idle request only for afflvl 1 77 */ 78 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; 79 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 80 81 break; 82 83 case PSTATE_ID_SOC_POWERDN: 84 /* 85 * System powerdown request only for afflvl 2 86 */ 87 for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) 88 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 89 90 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = 91 PLAT_SYS_SUSPEND_STATE_ID; 92 93 break; 94 95 default: 96 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 97 return PSCI_E_INVALID_PARAMS; 98 } 99 100 return PSCI_E_SUCCESS; 101 } 102 103 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 104 { 105 u_register_t mpidr = read_mpidr(); 106 const plat_local_state_t *pwr_domain_state = 107 target_state->pwr_domain_state; 108 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; 109 unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; 110 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; 111 112 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 113 114 assert(stateid_afflvl0 == PLAT_MAX_OFF_STATE); 115 assert(stateid_afflvl1 == PLAT_MAX_OFF_STATE); 116 117 /* suspend the entire soc */ 118 tegra_fc_soc_powerdn(mpidr); 119 120 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) { 121 122 assert(stateid_afflvl0 == PLAT_MAX_OFF_STATE); 123 124 /* Prepare for cluster idle */ 125 tegra_fc_cluster_idle(mpidr); 126 127 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_POWERDN) { 128 129 assert(stateid_afflvl0 == PLAT_MAX_OFF_STATE); 130 131 /* Prepare for cluster powerdn */ 132 tegra_fc_cluster_powerdn(mpidr); 133 134 } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { 135 136 /* Prepare for cpu powerdn */ 137 tegra_fc_cpu_powerdn(mpidr); 138 139 } else { 140 ERROR("%s: Unknown state id\n", __func__); 141 return PSCI_E_NOT_SUPPORTED; 142 } 143 144 return PSCI_E_SUCCESS; 145 } 146 147 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 148 { 149 uint32_t val; 150 151 /* 152 * Check if we are exiting from SOC_POWERDN. 153 */ 154 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 155 PLAT_SYS_SUSPEND_STATE_ID) { 156 157 /* 158 * Enable WRAP to INCR burst type conversions for 159 * incoming requests on the AXI slave ports. 160 */ 161 val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); 162 val &= ~ENABLE_UNSUP_TX_ERRORS; 163 val |= ENABLE_WRAP_TO_INCR_BURSTS; 164 mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); 165 166 /* 167 * Restore Boot and Power Management Processor (BPMP) reset 168 * address and reset it. 169 */ 170 tegra_fc_reset_bpmp(); 171 } 172 173 /* 174 * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's 175 * used for power management and boot purposes. Inform the BPMP that 176 * we have completed the cluster power up. 177 */ 178 tegra_fc_lock_active_cluster(); 179 180 return PSCI_E_SUCCESS; 181 } 182 183 int tegra_soc_pwr_domain_on(u_register_t mpidr) 184 { 185 int cpu = mpidr & MPIDR_CPU_MASK; 186 uint32_t mask = CPU_CORE_RESET_MASK << cpu; 187 188 /* Deassert CPU reset signals */ 189 mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); 190 191 /* Turn on CPU using flow controller or PMC */ 192 if (cpu_powergate_mask[cpu] == 0) { 193 tegra_pmc_cpu_on(cpu); 194 cpu_powergate_mask[cpu] = 1; 195 } else { 196 tegra_fc_cpu_on(cpu); 197 } 198 199 return PSCI_E_SUCCESS; 200 } 201 202 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 203 { 204 tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); 205 return PSCI_E_SUCCESS; 206 } 207 208 int tegra_soc_prepare_system_reset(void) 209 { 210 /* 211 * Set System Clock (SCLK) to POR default so that the clock source 212 * for the PMC APB clock would not be changed due to system reset. 213 */ 214 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, 215 SCLK_BURST_POLICY_DEFAULT); 216 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); 217 218 /* Wait 1 ms to make sure clock source/device logic is stabilized. */ 219 mdelay(1); 220 221 return PSCI_E_SUCCESS; 222 } 223