1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PMU_H__ 32 #define __PMU_H__ 33 34 #include <pmu_regs.h> 35 #include <soc.h> 36 37 /* Allocate sp reginon in pmusram */ 38 #define PSRAM_SP_SIZE 0x80 39 #define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE) 40 41 /***************************************************************************** 42 * Common define for per soc pmu.h 43 *****************************************************************************/ 44 /* The ways of cores power domain contorlling */ 45 enum cores_pm_ctr_mode { 46 core_pwr_pd = 0, 47 core_pwr_wfi = 1, 48 core_pwr_wfi_int = 2 49 }; 50 51 /***************************************************************************** 52 * pmu con,reg 53 *****************************************************************************/ 54 #define PMU_WKUP_CFG(n) ((n) * 4) 55 56 #define PMU_CORE_PM_CON(cpu) (0xc0 + (cpu * 4)) 57 58 /* the shift of bits for cores status */ 59 enum pmu_core_pwrst_shift { 60 clstl_cpu_wfe = 2, 61 clstl_cpu_wfi = 6, 62 clstb_cpu_wfe = 12, 63 clstb_cpu_wfi = 16 64 }; 65 66 #define CKECK_WFE_MSK 0x1 67 #define CKECK_WFI_MSK 0x10 68 #define CKECK_WFEI_MSK 0x11 69 70 enum pmu_powerdomain_id { 71 PD_CPUL0 = 0, 72 PD_CPUL1, 73 PD_CPUL2, 74 PD_CPUL3, 75 PD_CPUB0, 76 PD_CPUB1, 77 PD_SCUL, 78 PD_SCUB, 79 PD_TCPD0, 80 PD_TCPD1, 81 PD_CCI, 82 PD_PERILP, 83 PD_PERIHP, 84 PD_CENTER, 85 PD_VIO, 86 PD_GPU, 87 PD_VCODEC, 88 PD_VDU, 89 PD_RGA, 90 PD_IEP, 91 PD_VO, 92 PD_ISP0 = 22, 93 PD_ISP1, 94 PD_HDCP, 95 PD_GMAC, 96 PD_EMMC, 97 PD_USB3, 98 PD_EDP, 99 PD_GIC, 100 PD_SD, 101 PD_SDIOAUDIO, 102 PD_END 103 }; 104 105 enum powerdomain_state { 106 PMU_POWER_ON = 0, 107 PMU_POWER_OFF, 108 }; 109 110 enum pmu_bus_id { 111 BUS_ID_GPU = 0, 112 BUS_ID_PERILP, 113 BUS_ID_PERIHP, 114 BUS_ID_VCODEC, 115 BUS_ID_VDU, 116 BUS_ID_RGA, 117 BUS_ID_IEP, 118 BUS_ID_VOPB, 119 BUS_ID_VOPL, 120 BUS_ID_ISP0, 121 BUS_ID_ISP1, 122 BUS_ID_HDCP, 123 BUS_ID_USB3, 124 BUS_ID_PERILPM0, 125 BUS_ID_CENTER, 126 BUS_ID_CCIM0, 127 BUS_ID_CCIM1, 128 BUS_ID_VIO, 129 BUS_ID_MSCH0, 130 BUS_ID_MSCH1, 131 BUS_ID_ALIVE, 132 BUS_ID_PMU, 133 BUS_ID_EDP, 134 BUS_ID_GMAC, 135 BUS_ID_EMMC, 136 BUS_ID_CENTER1, 137 BUS_ID_PMUM0, 138 BUS_ID_GIC, 139 BUS_ID_SD, 140 BUS_ID_SDIOAUDIO, 141 }; 142 143 enum pmu_bus_state { 144 BUS_ACTIVE, 145 BUS_IDLE, 146 }; 147 148 /* pmu_cpuapm bit */ 149 enum pmu_cores_pm_by_wfi { 150 core_pm_en = 0, 151 core_pm_int_wakeup_en, 152 core_pm_resv, 153 core_pm_sft_wakeup_en 154 }; 155 156 enum pmu_wkup_cfg0 { 157 PMU_GPIO0A_POSE_WKUP_EN = 0, 158 PMU_GPIO0B_POSE_WKUP_EN = 8, 159 PMU_GPIO0C_POSE_WKUP_EN = 16, 160 PMU_GPIO0D_POSE_WKUP_EN = 24, 161 }; 162 163 enum pmu_wkup_cfg1 { 164 PMU_GPIO0A_NEGEDGE_WKUP_EN = 0, 165 PMU_GPIO0B_NEGEDGE_WKUP_EN = 7, 166 PMU_GPIO0C_NEGEDGE_WKUP_EN = 16, 167 PMU_GPIO0D_NEGEDGE_WKUP_EN = 24, 168 }; 169 170 enum pmu_wkup_cfg2 { 171 PMU_GPIO1A_POSE_WKUP_EN = 0, 172 PMU_GPIO1B_POSE_WKUP_EN = 7, 173 PMU_GPIO1C_POSE_WKUP_EN = 16, 174 PMU_GPIO1D_POSE_WKUP_EN = 24, 175 }; 176 177 enum pmu_wkup_cfg3 { 178 PMU_GPIO1A_NEGEDGE_WKUP_EN = 0, 179 PMU_GPIO1B_NEGEDGE_WKUP_EN = 7, 180 PMU_GPIO1C_NEGEDGE_WKUP_EN = 16, 181 PMU_GPIO1D_NEGEDGE_WKUP_EN = 24, 182 }; 183 184 /* pmu_wkup_cfg4 */ 185 enum pmu_wkup_cfg4 { 186 PMU_CLUSTER_L_WKUP_EN = 0, 187 PMU_CLUSTER_B_WKUP_EN, 188 PMU_GPIO_WKUP_EN, 189 PMU_SDIO_WKUP_EN, 190 191 PMU_SDMMC_WKUP_EN, 192 PMU_TIMER_WKUP_EN = 6, 193 PMU_USBDEV_WKUP_EN, 194 195 PMU_SFT_WKUP_EN, 196 PMU_M0_WDT_WKUP_EN, 197 PMU_TIMEOUT_WKUP_EN, 198 PMU_PWM_WKUP_EN, 199 200 PMU_PCIE_WKUP_EN = 13, 201 }; 202 203 enum pmu_pwrdn_con { 204 PMU_A53_L0_PWRDWN_EN = 0, 205 PMU_A53_L1_PWRDWN_EN, 206 PMU_A53_L2_PWRDWN_EN, 207 PMU_A53_L3_PWRDWN_EN, 208 209 PMU_A72_B0_PWRDWN_EN, 210 PMU_A72_B1_PWRDWN_EN, 211 PMU_SCU_L_PWRDWN_EN, 212 PMU_SCU_B_PWRDWN_EN, 213 214 PMU_TCPD0_PWRDWN_EN, 215 PMU_TCPD1_PWRDWN_EN, 216 PMU_CCI_PWRDWN_EN, 217 PMU_PERILP_PWRDWN_EN, 218 219 PMU_PERIHP_PWRDWN_EN, 220 PMU_CENTER_PWRDWN_EN, 221 PMU_VIO_PWRDWN_EN, 222 PMU_GPU_PWRDWN_EN, 223 224 PMU_VCODEC_PWRDWN_EN, 225 PMU_VDU_PWRDWN_EN, 226 PMU_RGA_PWRDWN_EN, 227 PMU_IEP_PWRDWN_EN, 228 229 PMU_VO_PWRDWN_EN, 230 PMU_ISP0_PWRDWN_EN = 22, 231 PMU_ISP1_PWRDWN_EN, 232 233 PMU_HDCP_PWRDWN_EN, 234 PMU_GMAC_PWRDWN_EN, 235 PMU_EMMC_PWRDWN_EN, 236 PMU_USB3_PWRDWN_EN, 237 238 PMU_EDP_PWRDWN_EN, 239 PMU_GIC_PWRDWN_EN, 240 PMU_SD_PWRDWN_EN, 241 PMU_SDIOAUDIO_PWRDWN_EN, 242 }; 243 244 enum pmu_pwrdn_st { 245 PMU_A53_L0_PWRDWN_ST = 0, 246 PMU_A53_L1_PWRDWN_ST, 247 PMU_A53_L2_PWRDWN_ST, 248 PMU_A53_L3_PWRDWN_ST, 249 250 PMU_A72_B0_PWRDWN_ST, 251 PMU_A72_B1_PWRDWN_ST, 252 PMU_SCU_L_PWRDWN_ST, 253 PMU_SCU_B_PWRDWN_ST, 254 255 PMU_TCPD0_PWRDWN_ST, 256 PMU_TCPD1_PWRDWN_ST, 257 PMU_CCI_PWRDWN_ST, 258 PMU_PERILP_PWRDWN_ST, 259 260 PMU_PERIHP_PWRDWN_ST, 261 PMU_CENTER_PWRDWN_ST, 262 PMU_VIO_PWRDWN_ST, 263 PMU_GPU_PWRDWN_ST, 264 265 PMU_VCODEC_PWRDWN_ST, 266 PMU_VDU_PWRDWN_ST, 267 PMU_RGA_PWRDWN_ST, 268 PMU_IEP_PWRDWN_ST, 269 270 PMU_VO_PWRDWN_ST, 271 PMU_ISP0_PWRDWN_ST = 22, 272 PMU_ISP1_PWRDWN_ST, 273 274 PMU_HDCP_PWRDWN_ST, 275 PMU_GMAC_PWRDWN_ST, 276 PMU_EMMC_PWRDWN_ST, 277 PMU_USB3_PWRDWN_ST, 278 279 PMU_EDP_PWRDWN_ST, 280 PMU_GIC_PWRDWN_ST, 281 PMU_SD_PWRDWN_ST, 282 PMU_SDIOAUDIO_PWRDWN_ST, 283 284 }; 285 286 enum pmu_pll_con { 287 PMU_PLL_PD_CFG = 0, 288 PMU_SFT_PLL_PD = 8, 289 }; 290 291 enum pmu_pwermode_con { 292 PMU_PWR_MODE_EN = 0, 293 PMU_WKUP_RST_EN, 294 PMU_INPUT_CLAMP_EN, 295 PMU_OSC_DIS, 296 297 PMU_ALIVE_USE_LF, 298 PMU_PMU_USE_LF, 299 PMU_POWER_OFF_REQ_CFG, 300 PMU_CHIP_PD_EN, 301 302 PMU_PLL_PD_EN, 303 PMU_CPU0_PD_EN, 304 PMU_L2_FLUSH_EN, 305 PMU_L2_IDLE_EN, 306 307 PMU_SCU_PD_EN, 308 PMU_CCI_PD_EN, 309 PMU_PERILP_PD_EN, 310 PMU_CENTER_PD_EN, 311 312 PMU_SREF0_ENTER_EN, 313 PMU_DDRC0_GATING_EN, 314 PMU_DDRIO0_RET_EN, 315 PMU_DDRIO0_RET_DE_REQ, 316 317 PMU_SREF1_ENTER_EN, 318 PMU_DDRC1_GATING_EN, 319 PMU_DDRIO1_RET_EN, 320 PMU_DDRIO1_RET_DE_REQ, 321 322 PMU_CLK_CENTER_SRC_GATE_EN = 26, 323 PMU_CLK_PERILP_SRC_GATE_EN, 324 325 PMU_CLK_CORE_SRC_GATE_EN, 326 PMU_DDRIO_RET_HW_DE_REQ, 327 PMU_SLP_OUTPUT_CFG, 328 PMU_MAIN_CLUSTER, 329 }; 330 331 enum pmu_sft_con { 332 PMU_WKUP_SFT = 0, 333 PMU_INPUT_CLAMP_CFG, 334 PMU_OSC_DIS_CFG, 335 PMU_PMU_LF_EN_CFG, 336 337 PMU_ALIVE_LF_EN_CFG, 338 PMU_24M_EN_CFG, 339 PMU_DBG_PWRUP_L0_CFG, 340 PMU_WKUP_SFT_M0, 341 342 PMU_DDRCTL0_C_SYSREQ_CFG, 343 PMU_DDR0_IO_RET_CFG, 344 345 PMU_DDRCTL1_C_SYSREQ_CFG = 12, 346 PMU_DDR1_IO_RET_CFG, 347 DBG_PWRUP_B0_CFG = 15, 348 349 DBG_NOPWERDWN_L0_EN, 350 DBG_NOPWERDWN_L1_EN, 351 DBG_NOPWERDWN_L2_EN, 352 DBG_NOPWERDWN_L3_EN, 353 354 DBG_PWRUP_REQ_L_EN = 20, 355 CLUSTER_L_CLK_SRC_GATING_CFG, 356 L2_FLUSH_REQ_CLUSTER_L, 357 ACINACTM_CLUSTER_L_CFG, 358 359 DBG_NO_PWERDWN_B0_EN, 360 DBG_NO_PWERDWN_B1_EN, 361 362 DBG_PWRUP_REQ_B_EN = 28, 363 CLUSTER_B_CLK_SRC_GATING_CFG, 364 L2_FLUSH_REQ_CLUSTER_B, 365 ACINACTM_CLUSTER_B_CFG, 366 }; 367 368 enum pmu_int_con { 369 PMU_PMU_INT_EN = 0, 370 PMU_PWRMD_WKUP_INT_EN, 371 PMU_WKUP_GPIO0_NEG_INT_EN, 372 PMU_WKUP_GPIO0_POS_INT_EN, 373 PMU_WKUP_GPIO1_NEG_INT_EN, 374 PMU_WKUP_GPIO1_POS_INT_EN, 375 }; 376 377 enum pmu_int_st { 378 PMU_PWRMD_WKUP_INT_ST = 1, 379 PMU_WKUP_GPIO0_NEG_INT_ST, 380 PMU_WKUP_GPIO0_POS_INT_ST, 381 PMU_WKUP_GPIO1_NEG_INT_ST, 382 PMU_WKUP_GPIO1_POS_INT_ST, 383 }; 384 385 enum pmu_gpio0_pos_int_con { 386 PMU_GPIO0A_POS_INT_EN = 0, 387 PMU_GPIO0B_POS_INT_EN = 8, 388 PMU_GPIO0C_POS_INT_EN = 16, 389 PMU_GPIO0D_POS_INT_EN = 24, 390 }; 391 392 enum pmu_gpio0_neg_int_con { 393 PMU_GPIO0A_NEG_INT_EN = 0, 394 PMU_GPIO0B_NEG_INT_EN = 8, 395 PMU_GPIO0C_NEG_INT_EN = 16, 396 PMU_GPIO0D_NEG_INT_EN = 24, 397 }; 398 399 enum pmu_gpio1_pos_int_con { 400 PMU_GPIO1A_POS_INT_EN = 0, 401 PMU_GPIO1B_POS_INT_EN = 8, 402 PMU_GPIO1C_POS_INT_EN = 16, 403 PMU_GPIO1D_POS_INT_EN = 24, 404 }; 405 406 enum pmu_gpio1_neg_int_con { 407 PMU_GPIO1A_NEG_INT_EN = 0, 408 PMU_GPIO1B_NEG_INT_EN = 8, 409 PMU_GPIO1C_NEG_INT_EN = 16, 410 PMU_GPIO1D_NEG_INT_EN = 24, 411 }; 412 413 enum pmu_gpio0_pos_int_st { 414 PMU_GPIO0A_POS_INT_ST = 0, 415 PMU_GPIO0B_POS_INT_ST = 8, 416 PMU_GPIO0C_POS_INT_ST = 16, 417 PMU_GPIO0D_POS_INT_ST = 24, 418 }; 419 420 enum pmu_gpio0_neg_int_st { 421 PMU_GPIO0A_NEG_INT_ST = 0, 422 PMU_GPIO0B_NEG_INT_ST = 8, 423 PMU_GPIO0C_NEG_INT_ST = 16, 424 PMU_GPIO0D_NEG_INT_ST = 24, 425 }; 426 427 enum pmu_gpio1_pos_int_st { 428 PMU_GPIO1A_POS_INT_ST = 0, 429 PMU_GPIO1B_POS_INT_ST = 8, 430 PMU_GPIO1C_POS_INT_ST = 16, 431 PMU_GPIO1D_POS_INT_ST = 24, 432 }; 433 434 enum pmu_gpio1_neg_int_st { 435 PMU_GPIO1A_NEG_INT_ST = 0, 436 PMU_GPIO1B_NEG_INT_ST = 8, 437 PMU_GPIO1C_NEG_INT_ST = 16, 438 PMU_GPIO1D_NEG_INT_ST = 24, 439 }; 440 441 /* pmu power down configure register 0x0050 */ 442 enum pmu_pwrdn_inten { 443 PMU_A53_L0_PWR_SWITCH_INT_EN = 0, 444 PMU_A53_L1_PWR_SWITCH_INT_EN, 445 PMU_A53_L2_PWR_SWITCH_INT_EN, 446 PMU_A53_L3_PWR_SWITCH_INT_EN, 447 448 PMU_A72_B0_PWR_SWITCH_INT_EN, 449 PMU_A72_B1_PWR_SWITCH_INT_EN, 450 PMU_SCU_L_PWR_SWITCH_INT_EN, 451 PMU_SCU_B_PWR_SWITCH_INT_EN, 452 453 PMU_TCPD0_PWR_SWITCH_INT_EN, 454 PMU_TCPD1_PWR_SWITCH_INT_EN, 455 PMU_CCI_PWR_SWITCH_INT_EN, 456 PMU_PERILP_PWR_SWITCH_INT_EN, 457 458 PMU_PERIHP_PWR_SWITCH_INT_EN, 459 PMU_CENTER_PWR_SWITCH_INT_EN, 460 PMU_VIO_PWR_SWITCH_INT_EN, 461 PMU_GPU_PWR_SWITCH_INT_EN, 462 463 PMU_VCODEC_PWR_SWITCH_INT_EN, 464 PMU_VDU_PWR_SWITCH_INT_EN, 465 PMU_RGA_PWR_SWITCH_INT_EN, 466 PMU_IEP_PWR_SWITCH_INT_EN, 467 468 PMU_VO_PWR_SWITCH_INT_EN, 469 PMU_ISP0_PWR_SWITCH_INT_EN = 22, 470 PMU_ISP1_PWR_SWITCH_INT_EN, 471 472 PMU_HDCP_PWR_SWITCH_INT_EN, 473 PMU_GMAC_PWR_SWITCH_INT_EN, 474 PMU_EMMC_PWR_SWITCH_INT_EN, 475 PMU_USB3_PWR_SWITCH_INT_EN, 476 477 PMU_EDP_PWR_SWITCH_INT_EN, 478 PMU_GIC_PWR_SWITCH_INT_EN, 479 PMU_SD_PWR_SWITCH_INT_EN, 480 PMU_SDIOAUDIO_PWR_SWITCH_INT_EN, 481 }; 482 483 enum pmu_wkup_status { 484 PMU_WKUP_BY_CLSTER_L_INT = 0, 485 PMU_WKUP_BY_CLSTER_b_INT, 486 PMU_WKUP_BY_GPIO_INT, 487 PMU_WKUP_BY_SDIO_DET, 488 489 PMU_WKUP_BY_SDMMC_DET, 490 PMU_WKUP_BY_TIMER = 6, 491 PMU_WKUP_BY_USBDEV_DET, 492 493 PMU_WKUP_BY_M0_SFT, 494 PMU_WKUP_BY_M0_WDT_INT, 495 PMU_WKUP_BY_TIMEOUT, 496 PMU_WKUP_BY_PWM, 497 498 PMU_WKUP_BY_PCIE = 13, 499 }; 500 501 enum pmu_bus_clr { 502 PMU_CLR_GPU = 0, 503 PMU_CLR_PERILP, 504 PMU_CLR_PERIHP, 505 PMU_CLR_VCODEC, 506 507 PMU_CLR_VDU, 508 PMU_CLR_RGA, 509 PMU_CLR_IEP, 510 PMU_CLR_VOPB, 511 512 PMU_CLR_VOPL, 513 PMU_CLR_ISP0, 514 PMU_CLR_ISP1, 515 PMU_CLR_HDCP, 516 517 PMU_CLR_USB3, 518 PMU_CLR_PERILPM0, 519 PMU_CLR_CENTER, 520 PMU_CLR_CCIM1, 521 522 PMU_CLR_CCIM0, 523 PMU_CLR_VIO, 524 PMU_CLR_MSCH0, 525 PMU_CLR_MSCH1, 526 527 PMU_CLR_ALIVE, 528 PMU_CLR_PMU, 529 PMU_CLR_EDP, 530 PMU_CLR_GMAC, 531 532 PMU_CLR_EMMC, 533 PMU_CLR_CENTER1, 534 PMU_CLR_PMUM0, 535 PMU_CLR_GIC, 536 537 PMU_CLR_SD, 538 PMU_CLR_SDIOAUDIO, 539 }; 540 541 /* PMU bus idle request register */ 542 enum pmu_bus_idle_req { 543 PMU_IDLE_REQ_GPU = 0, 544 PMU_IDLE_REQ_PERILP, 545 PMU_IDLE_REQ_PERIHP, 546 PMU_IDLE_REQ_VCODEC, 547 548 PMU_IDLE_REQ_VDU, 549 PMU_IDLE_REQ_RGA, 550 PMU_IDLE_REQ_IEP, 551 PMU_IDLE_REQ_VOPB, 552 553 PMU_IDLE_REQ_VOPL, 554 PMU_IDLE_REQ_ISP0, 555 PMU_IDLE_REQ_ISP1, 556 PMU_IDLE_REQ_HDCP, 557 558 PMU_IDLE_REQ_USB3, 559 PMU_IDLE_REQ_PERILPM0, 560 PMU_IDLE_REQ_CENTER, 561 PMU_IDLE_REQ_CCIM0, 562 563 PMU_IDLE_REQ_CCIM1, 564 PMU_IDLE_REQ_VIO, 565 PMU_IDLE_REQ_MSCH0, 566 PMU_IDLE_REQ_MSCH1, 567 568 PMU_IDLE_REQ_ALIVE, 569 PMU_IDLE_REQ_PMU, 570 PMU_IDLE_REQ_EDP, 571 PMU_IDLE_REQ_GMAC, 572 573 PMU_IDLE_REQ_EMMC, 574 PMU_IDLE_REQ_CENTER1, 575 PMU_IDLE_REQ_PMUM0, 576 PMU_IDLE_REQ_GIC, 577 578 PMU_IDLE_REQ_SD, 579 PMU_IDLE_REQ_SDIOAUDIO, 580 }; 581 582 /* pmu bus idle status register */ 583 enum pmu_bus_idle_st { 584 PMU_IDLE_ST_GPU = 0, 585 PMU_IDLE_ST_PERILP, 586 PMU_IDLE_ST_PERIHP, 587 PMU_IDLE_ST_VCODEC, 588 589 PMU_IDLE_ST_VDU, 590 PMU_IDLE_ST_RGA, 591 PMU_IDLE_ST_IEP, 592 PMU_IDLE_ST_VOPB, 593 594 PMU_IDLE_ST_VOPL, 595 PMU_IDLE_ST_ISP0, 596 PMU_IDLE_ST_ISP1, 597 PMU_IDLE_ST_HDCP, 598 599 PMU_IDLE_ST_USB3, 600 PMU_IDLE_ST_PERILPM0, 601 PMU_IDLE_ST_CENTER, 602 PMU_IDLE_ST_CCIM0, 603 604 PMU_IDLE_ST_CCIM1, 605 PMU_IDLE_ST_VIO, 606 PMU_IDLE_ST_MSCH0, 607 PMU_IDLE_ST_MSCH1, 608 609 PMU_IDLE_ST_ALIVE, 610 PMU_IDLE_ST_PMU, 611 PMU_IDLE_ST_EDP, 612 PMU_IDLE_ST_GMAC, 613 614 PMU_IDLE_ST_EMMC, 615 PMU_IDLE_ST_CENTER1, 616 PMU_IDLE_ST_PMUM0, 617 PMU_IDLE_ST_GIC, 618 619 PMU_IDLE_ST_SD, 620 PMU_IDLE_ST_SDIOAUDIO, 621 }; 622 623 enum pmu_bus_idle_ack { 624 PMU_IDLE_ACK_GPU = 0, 625 PMU_IDLE_ACK_PERILP, 626 PMU_IDLE_ACK_PERIHP, 627 PMU_IDLE_ACK_VCODEC, 628 629 PMU_IDLE_ACK_VDU, 630 PMU_IDLE_ACK_RGA, 631 PMU_IDLE_ACK_IEP, 632 PMU_IDLE_ACK_VOPB, 633 634 PMU_IDLE_ACK_VOPL, 635 PMU_IDLE_ACK_ISP0, 636 PMU_IDLE_ACK_ISP1, 637 PMU_IDLE_ACK_HDCP, 638 639 PMU_IDLE_ACK_USB3, 640 PMU_IDLE_ACK_PERILPM0, 641 PMU_IDLE_ACK_CENTER, 642 PMU_IDLE_ACK_CCIM0, 643 644 PMU_IDLE_ACK_CCIM1, 645 PMU_IDLE_ACK_VIO, 646 PMU_IDLE_ACK_MSCH0, 647 PMU_IDLE_ACK_MSCH1, 648 649 PMU_IDLE_ACK_ALIVE, 650 PMU_IDLE_ACK_PMU, 651 PMU_IDLE_ACK_EDP, 652 PMU_IDLE_ACK_GMAC, 653 654 PMU_IDLE_ACK_EMMC, 655 PMU_IDLE_ACK_CENTER1, 656 PMU_IDLE_ACK_PMUM0, 657 PMU_IDLE_ACK_GIC, 658 659 PMU_IDLE_ACK_SD, 660 PMU_IDLE_ACK_SDIOAUDIO, 661 }; 662 663 enum pmu_cci500_con { 664 PMU_PREQ_CCI500_CFG_SW = 0, 665 PMU_CLR_PREQ_CCI500_HW, 666 PMU_PSTATE_CCI500_0, 667 PMU_PSTATE_CCI500_1, 668 669 PMU_PSTATE_CCI500_2, 670 PMU_QREQ_CCI500_CFG_SW, 671 PMU_CLR_QREQ_CCI500_HW, 672 PMU_QGATING_CCI500_CFG, 673 674 PMU_PREQ_CCI500_CFG_SW_WMSK = 16, 675 PMU_CLR_PREQ_CCI500_HW_WMSK, 676 PMU_PSTATE_CCI500_0_WMSK, 677 PMU_PSTATE_CCI500_1_WMSK, 678 679 PMU_PSTATE_CCI500_2_WMSK, 680 PMU_QREQ_CCI500_CFG_SW_WMSK, 681 PMU_CLR_QREQ_CCI500_HW_WMSK, 682 PMU_QGATING_CCI500_CFG_WMSK, 683 }; 684 685 enum pmu_adb400_con { 686 PMU_PWRDWN_REQ_CXCS_SW = 0, 687 PMU_PWRDWN_REQ_CORE_L_SW, 688 PMU_PWRDWN_REQ_CORE_L_2GIC_SW, 689 PMU_PWRDWN_REQ_GIC2_CORE_L_SW, 690 691 PMU_PWRDWN_REQ_CORE_B_SW, 692 PMU_PWRDWN_REQ_CORE_B_2GIC_SW, 693 PMU_PWRDWN_REQ_GIC2_CORE_B_SW, 694 695 PMU_CLR_CXCS_HW = 8, 696 PMU_CLR_CORE_L_HW, 697 PMU_CLR_CORE_L_2GIC_HW, 698 PMU_CLR_GIC2_CORE_L_HW, 699 700 PMU_CLR_CORE_B_HW, 701 PMU_CLR_CORE_B_2GIC_HW, 702 PMU_CLR_GIC2_CORE_B_HW, 703 704 PMU_PWRDWN_REQ_CXCS_SW_WMSK = 16, 705 PMU_PWRDWN_REQ_CORE_L_SW_WMSK, 706 PMU_PWRDWN_REQ_CORE_L_2GIC_SW_WMSK, 707 PMU_PWRDWN_REQ_GIC2_CORE_L_SW_WMSK, 708 709 PMU_PWRDWN_REQ_CORE_B_SW_WMSK, 710 PMU_PWRDWN_REQ_CORE_B_2GIC_SW_WMSK, 711 PMU_PWRDWN_REQ_GIC2_CORE_B_SW_WMSK, 712 713 PMU_CLR_CXCS_HW_WMSK = 24, 714 PMU_CLR_CORE_L_HW_WMSK, 715 PMU_CLR_CORE_L_2GIC_HW_WMSK, 716 PMU_CLR_GIC2_CORE_L_HW_WMSK, 717 718 PMU_CLR_CORE_B_HW_WMSK, 719 PMU_CLR_CORE_B_2GIC_HW_WMSK, 720 PMU_CLR_GIC2_CORE_B_HW_WMSK, 721 }; 722 723 enum pmu_adb400_st { 724 PMU_PWRDWN_REQ_CXCS_SW_ST = 0, 725 PMU_PWRDWN_REQ_CORE_L_SW_ST, 726 PMU_PWRDWN_REQ_CORE_L_2GIC_SW_ST, 727 PMU_PWRDWN_REQ_GIC2_CORE_L_SW_ST, 728 729 PMU_PWRDWN_REQ_CORE_B_SW_ST, 730 PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST, 731 PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST, 732 733 PMU_CLR_CXCS_HW_ST = 8, 734 PMU_CLR_CORE_L_HW_ST, 735 PMU_CLR_CORE_L_2GIC_HW_ST, 736 PMU_CLR_GIC2_CORE_L_HW_ST, 737 738 PMU_CLR_CORE_B_HW_ST, 739 PMU_CLR_CORE_B_2GIC_HW_ST, 740 PMU_CLR_GIC2_CORE_B_HW_ST, 741 }; 742 743 enum pmu_pwrdn_con1 { 744 PMU_VD_SCU_L_PWRDN_EN = 0, 745 PMU_VD_SCU_B_PWRDN_EN, 746 PMU_VD_CENTER_PWRDN_EN, 747 }; 748 749 enum pmu_core_pwr_st { 750 L2_FLUSHDONE_CLUSTER_L = 0, 751 STANDBY_BY_WFIL2_CLUSTER_L, 752 753 L2_FLUSHDONE_CLUSTER_B = 10, 754 STANDBY_BY_WFIL2_CLUSTER_B, 755 }; 756 757 /* Specific features required */ 758 #define AP_PWROFF 0x0a 759 760 #define GPIO0A0_SMT_ENABLE BITS_WITH_WMASK(1, 3, 0) 761 #define GPIO1A6_IOMUX BITS_WITH_WMASK(0, 3, 12) 762 763 #define TSADC_INT_PIN 38 764 #define CORES_PM_DISABLE 0x0 765 766 #define PD_CTR_LOOP 500 767 #define CHK_CPU_LOOP 500 768 #define MAX_WAIT_COUNT 1000 769 770 #define GRF_SOC_CON4 0x0e210 771 772 #define PMUGRF_GPIO0A_SMT 0x0120 773 #define PMUGRF_SOC_CON0 0x0180 774 775 #define CCI_FORCE_WAKEUP WMSK_BIT(8) 776 #define EXTERNAL_32K WMSK_BIT(0) 777 778 #define PLL_PD_HW 0xff 779 #define IOMUX_CLK_32K 0x00030002 780 #define NOC_AUTO_ENABLE 0x3fffffff 781 782 #define SAVE_QOS(array, NAME) \ 783 RK3399_CPU_AXI_SAVE_QOS(array, CPU_AXI_##NAME##_QOS_BASE) 784 #define RESTORE_QOS(array, NAME) \ 785 RK3399_CPU_AXI_RESTORE_QOS(array, CPU_AXI_##NAME##_QOS_BASE) 786 787 #define RK3399_CPU_AXI_SAVE_QOS(array, base) do { \ 788 array[0] = mmio_read_32(base + CPU_AXI_QOS_ID_COREID); \ 789 array[1] = mmio_read_32(base + CPU_AXI_QOS_REVISIONID); \ 790 array[2] = mmio_read_32(base + CPU_AXI_QOS_PRIORITY); \ 791 array[3] = mmio_read_32(base + CPU_AXI_QOS_MODE); \ 792 array[4] = mmio_read_32(base + CPU_AXI_QOS_BANDWIDTH); \ 793 array[5] = mmio_read_32(base + CPU_AXI_QOS_SATURATION); \ 794 array[6] = mmio_read_32(base + CPU_AXI_QOS_EXTCONTROL); \ 795 } while (0) 796 797 #define RK3399_CPU_AXI_RESTORE_QOS(array, base) do { \ 798 mmio_write_32(base + CPU_AXI_QOS_ID_COREID, array[0]); \ 799 mmio_write_32(base + CPU_AXI_QOS_REVISIONID, array[1]); \ 800 mmio_write_32(base + CPU_AXI_QOS_PRIORITY, array[2]); \ 801 mmio_write_32(base + CPU_AXI_QOS_MODE, array[3]); \ 802 mmio_write_32(base + CPU_AXI_QOS_BANDWIDTH, array[4]); \ 803 mmio_write_32(base + CPU_AXI_QOS_SATURATION, array[5]); \ 804 mmio_write_32(base + CPU_AXI_QOS_EXTCONTROL, array[6]); \ 805 } while (0) 806 807 struct pmu_slpdata_s { 808 uint32_t cci_m0_qos[CPU_AXI_QOS_NUM_REGS]; 809 uint32_t cci_m1_qos[CPU_AXI_QOS_NUM_REGS]; 810 uint32_t dmac0_qos[CPU_AXI_QOS_NUM_REGS]; 811 uint32_t dmac1_qos[CPU_AXI_QOS_NUM_REGS]; 812 uint32_t dcf_qos[CPU_AXI_QOS_NUM_REGS]; 813 uint32_t crypto0_qos[CPU_AXI_QOS_NUM_REGS]; 814 uint32_t crypto1_qos[CPU_AXI_QOS_NUM_REGS]; 815 uint32_t pmu_cm0_qos[CPU_AXI_QOS_NUM_REGS]; 816 uint32_t peri_cm1_qos[CPU_AXI_QOS_NUM_REGS]; 817 uint32_t gic_qos[CPU_AXI_QOS_NUM_REGS]; 818 uint32_t sdmmc_qos[CPU_AXI_QOS_NUM_REGS]; 819 uint32_t gmac_qos[CPU_AXI_QOS_NUM_REGS]; 820 uint32_t emmc_qos[CPU_AXI_QOS_NUM_REGS]; 821 uint32_t usb_otg0_qos[CPU_AXI_QOS_NUM_REGS]; 822 uint32_t usb_otg1_qos[CPU_AXI_QOS_NUM_REGS]; 823 uint32_t usb_host0_qos[CPU_AXI_QOS_NUM_REGS]; 824 uint32_t usb_host1_qos[CPU_AXI_QOS_NUM_REGS]; 825 uint32_t gpu_qos[CPU_AXI_QOS_NUM_REGS]; 826 uint32_t video_m0_qos[CPU_AXI_QOS_NUM_REGS]; 827 uint32_t video_m1_r_qos[CPU_AXI_QOS_NUM_REGS]; 828 uint32_t video_m1_w_qos[CPU_AXI_QOS_NUM_REGS]; 829 uint32_t rga_r_qos[CPU_AXI_QOS_NUM_REGS]; 830 uint32_t rga_w_qos[CPU_AXI_QOS_NUM_REGS]; 831 uint32_t vop_big_r[CPU_AXI_QOS_NUM_REGS]; 832 uint32_t vop_big_w[CPU_AXI_QOS_NUM_REGS]; 833 uint32_t vop_little[CPU_AXI_QOS_NUM_REGS]; 834 uint32_t iep_qos[CPU_AXI_QOS_NUM_REGS]; 835 uint32_t isp1_m0_qos[CPU_AXI_QOS_NUM_REGS]; 836 uint32_t isp1_m1_qos[CPU_AXI_QOS_NUM_REGS]; 837 uint32_t isp0_m0_qos[CPU_AXI_QOS_NUM_REGS]; 838 uint32_t isp0_m1_qos[CPU_AXI_QOS_NUM_REGS]; 839 uint32_t hdcp_qos[CPU_AXI_QOS_NUM_REGS]; 840 uint32_t perihp_nsp_qos[CPU_AXI_QOS_NUM_REGS]; 841 uint32_t perilp_nsp_qos[CPU_AXI_QOS_NUM_REGS]; 842 uint32_t perilpslv_nsp_qos[CPU_AXI_QOS_NUM_REGS]; 843 uint32_t sdio_qos[CPU_AXI_QOS_NUM_REGS]; 844 }; 845 846 extern uint32_t clst_warmboot_data[PLATFORM_CLUSTER_COUNT]; 847 848 extern void sram_func_set_ddrctl_pll(uint32_t pll_src); 849 850 #endif /* __PMU_H__ */ 851