1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <string.h> 32 #include <stdint.h> 33 #include <dram.h> 34 #include "dram_spec_timing.h" 35 36 static const uint8_t ddr3_cl_cwl[][7] = { 37 /* 38 * speed 0~330 331 ~ 400 401 ~ 533 534~666 667~800 801~933 934~1066 39 * tCK>3 2.5~3 1.875~2.5 1.5~1.875 1.25~1.5 1.07~1.25 0.938~1.07 40 * cl<<4, cwl cl<<4, cwl cl<<4, cwl 41 */ 42 /* DDR3_800D (5-5-5) */ 43 {((5 << 4) | 5), ((5 << 4) | 5), 0, 0, 0, 0, 0}, 44 /* DDR3_800E (6-6-6) */ 45 {((5 << 4) | 5), ((6 << 4) | 5), 0, 0, 0, 0, 0}, 46 /* DDR3_1066E (6-6-6) */ 47 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), 0, 0, 0, 0}, 48 /* DDR3_1066F (7-7-7) */ 49 {((5 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), 0, 0, 0, 0}, 50 /* DDR3_1066G (8-8-8) */ 51 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), 0, 0, 0, 0}, 52 /* DDR3_1333F (7-7-7) */ 53 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 54 0, 0, 0}, 55 /* DDR3_1333G (8-8-8) */ 56 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((8 << 4) | 7), 57 0, 0, 0}, 58 /* DDR3_1333H (9-9-9) */ 59 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((9 << 4) | 7), 60 0, 0, 0}, 61 /* DDR3_1333J (10-10-10) */ 62 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 63 0, 0, 0}, 64 /* DDR3_1600G (8-8-8) */ 65 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 66 ((8 << 4) | 8), 0, 0}, 67 /* DDR3_1600H (9-9-9) */ 68 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 69 ((9 << 4) | 8), 0, 0}, 70 /* DDR3_1600J (10-10-10) */ 71 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 72 ((10 << 4) | 8), 0, 0}, 73 /* DDR3_1600K (11-11-11) */ 74 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 75 ((11 << 4) | 8), 0, 0}, 76 /* DDR3_1866J (10-10-10) */ 77 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 78 ((9 << 4) | 8), ((11 << 4) | 9), 0}, 79 /* DDR3_1866K (11-11-11) */ 80 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((8 << 4) | 7), 81 ((10 << 4) | 8), ((11 << 4) | 9), 0}, 82 /* DDR3_1866L (12-12-12) */ 83 {((6 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 84 ((11 << 4) | 8), ((12 << 4) | 9), 0}, 85 /* DDR3_1866M (13-13-13) */ 86 {((6 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 87 ((11 << 4) | 8), ((13 << 4) | 9), 0}, 88 /* DDR3_2133K (11-11-11) */ 89 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 90 ((9 << 4) | 8), ((10 << 4) | 9), ((11 << 4) | 10)}, 91 /* DDR3_2133L (12-12-12) */ 92 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 93 ((9 << 4) | 8), ((11 << 4) | 9), ((12 << 4) | 10)}, 94 /* DDR3_2133M (13-13-13) */ 95 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 96 ((10 << 4) | 8), ((12 << 4) | 9), ((13 << 4) | 10)}, 97 /* DDR3_2133N (14-14-14) */ 98 {((6 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 99 ((11 << 4) | 8), ((13 << 4) | 9), ((14 << 4) | 10)}, 100 /* DDR3_DEFAULT */ 101 {((6 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 102 ((11 << 4) | 8), ((13 << 4) | 9), ((14 << 4) | 10)} 103 }; 104 105 static const uint16_t ddr3_trc_tfaw[] = { 106 /* tRC tFAW */ 107 ((50 << 8) | 50), /* DDR3_800D (5-5-5) */ 108 ((53 << 8) | 50), /* DDR3_800E (6-6-6) */ 109 110 ((49 << 8) | 50), /* DDR3_1066E (6-6-6) */ 111 ((51 << 8) | 50), /* DDR3_1066F (7-7-7) */ 112 ((53 << 8) | 50), /* DDR3_1066G (8-8-8) */ 113 114 ((47 << 8) | 45), /* DDR3_1333F (7-7-7) */ 115 ((48 << 8) | 45), /* DDR3_1333G (8-8-8) */ 116 ((50 << 8) | 45), /* DDR3_1333H (9-9-9) */ 117 ((51 << 8) | 45), /* DDR3_1333J (10-10-10) */ 118 119 ((45 << 8) | 40), /* DDR3_1600G (8-8-8) */ 120 ((47 << 8) | 40), /* DDR3_1600H (9-9-9)*/ 121 ((48 << 8) | 40), /* DDR3_1600J (10-10-10) */ 122 ((49 << 8) | 40), /* DDR3_1600K (11-11-11) */ 123 124 ((45 << 8) | 35), /* DDR3_1866J (10-10-10) */ 125 ((46 << 8) | 35), /* DDR3_1866K (11-11-11) */ 126 ((47 << 8) | 35), /* DDR3_1866L (12-12-12) */ 127 ((48 << 8) | 35), /* DDR3_1866M (13-13-13) */ 128 129 ((44 << 8) | 35), /* DDR3_2133K (11-11-11) */ 130 ((45 << 8) | 35), /* DDR3_2133L (12-12-12) */ 131 ((46 << 8) | 35), /* DDR3_2133M (13-13-13) */ 132 ((47 << 8) | 35), /* DDR3_2133N (14-14-14) */ 133 134 ((53 << 8) | 50) /* DDR3_DEFAULT */ 135 }; 136 137 static uint32_t get_max_speed_rate(struct timing_related_config *timing_config) 138 { 139 if (timing_config->ch_cnt > 1) 140 return max(timing_config->dram_info[0].speed_rate, 141 timing_config->dram_info[1].speed_rate); 142 else 143 return timing_config->dram_info[0].speed_rate; 144 } 145 146 static uint32_t 147 get_max_die_capability(struct timing_related_config *timing_config) 148 { 149 uint32_t die_cap = 0; 150 uint32_t cs, ch; 151 152 for (ch = 0; ch < timing_config->ch_cnt; ch++) { 153 for (cs = 0; cs < timing_config->dram_info[ch].cs_cnt; cs++) { 154 die_cap = max(die_cap, 155 timing_config-> 156 dram_info[ch].per_die_capability[cs]); 157 } 158 } 159 return die_cap; 160 } 161 162 /* tRSTL, 100ns */ 163 #define DDR3_TRSTL (100) 164 /* trsth, 500us */ 165 #define DDR3_TRSTH (500000) 166 /* trefi, 7.8us */ 167 #define DDR3_TREFI_7_8_US (7800) 168 /* tWR, 15ns */ 169 #define DDR3_TWR (15) 170 /* tRTP, max(4 tCK,7.5ns) */ 171 #define DDR3_TRTP (7) 172 /* tRRD = max(4nCK, 10ns) */ 173 #define DDR3_TRRD (10) 174 /* tCK */ 175 #define DDR3_TCCD (4) 176 /*tWTR, max(4 tCK,7.5ns)*/ 177 #define DDR3_TWTR (7) 178 /* tCK */ 179 #define DDR3_TRTW (0) 180 /* tRAS, 37.5ns(400MHz) 37.5ns(533MHz) */ 181 #define DDR3_TRAS (37) 182 /* ns */ 183 #define DDR3_TRFC_512MBIT (90) 184 /* ns */ 185 #define DDR3_TRFC_1GBIT (110) 186 /* ns */ 187 #define DDR3_TRFC_2GBIT (160) 188 /* ns */ 189 #define DDR3_TRFC_4GBIT (300) 190 /* ns */ 191 #define DDR3_TRFC_8GBIT (350) 192 193 /*pd and sr*/ 194 #define DDR3_TXP (7) /* tXP, max(3 tCK, 7.5ns)( < 933MHz) */ 195 #define DDR3_TXPDLL (24) /* tXPDLL, max(10 tCK, 24ns) */ 196 #define DDR3_TDLLK (512) /* tXSR, tDLLK=512 tCK */ 197 #define DDR3_TCKE_400MHZ (7) /* tCKE, max(3 tCK,7.5ns)(400MHz) */ 198 #define DDR3_TCKE_533MHZ (6) /* tCKE, max(3 tCK,5.625ns)(533MHz) */ 199 #define DDR3_TCKSRE (10) /* tCKSRX, max(5 tCK, 10ns) */ 200 201 /*mode register timing*/ 202 #define DDR3_TMOD (15) /* tMOD, max(12 tCK,15ns) */ 203 #define DDR3_TMRD (4) /* tMRD, 4 tCK */ 204 205 /* ZQ */ 206 #define DDR3_TZQINIT (640) /* tZQinit, max(512 tCK, 640ns) */ 207 #define DDR3_TZQCS (80) /* tZQCS, max(64 tCK, 80ns) */ 208 #define DDR3_TZQOPER (320) /* tZQoper, max(256 tCK, 320ns) */ 209 210 /* Write leveling */ 211 #define DDR3_TWLMRD (40) /* tCK */ 212 #define DDR3_TWLO (9) /* max 7.5ns */ 213 #define DDR3_TWLDQSEN (25) /* tCK */ 214 215 /* 216 * Description: depend on input parameter "timing_config", 217 * and calculate all ddr3 218 * spec timing to "pdram_timing" 219 * parameters: 220 * input: timing_config 221 * output: pdram_timing 222 */ 223 static void ddr3_get_parameter(struct timing_related_config *timing_config, 224 struct dram_timing_t *pdram_timing) 225 { 226 uint32_t nmhz = timing_config->freq; 227 uint32_t ddr_speed_bin = get_max_speed_rate(timing_config); 228 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 229 uint32_t tmp; 230 231 memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); 232 pdram_timing->mhz = nmhz; 233 pdram_timing->al = 0; 234 pdram_timing->bl = timing_config->bl; 235 if (nmhz <= 330) 236 tmp = 0; 237 else if (nmhz <= 400) 238 tmp = 1; 239 else if (nmhz <= 533) 240 tmp = 2; 241 else if (nmhz <= 666) 242 tmp = 3; 243 else if (nmhz <= 800) 244 tmp = 4; 245 else if (nmhz <= 933) 246 tmp = 5; 247 else 248 tmp = 6; 249 250 /* when dll bypss cl = cwl = 6 */ 251 if (nmhz < 300) { 252 pdram_timing->cl = 6; 253 pdram_timing->cwl = 6; 254 } else { 255 pdram_timing->cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4) & 0xf; 256 pdram_timing->cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf; 257 } 258 259 switch (timing_config->dramds) { 260 case 40: 261 tmp = DDR3_DS_40; 262 break; 263 case 34: 264 default: 265 tmp = DDR3_DS_34; 266 break; 267 } 268 269 switch (timing_config->dramodt) { 270 case 60: 271 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_60; 272 break; 273 case 40: 274 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_40; 275 break; 276 case 120: 277 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_120; 278 break; 279 case 0: 280 default: 281 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS; 282 break; 283 } 284 285 pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl); 286 pdram_timing->mr[3] = 0; 287 288 pdram_timing->trstl = ((DDR3_TRSTL * nmhz + 999) / 1000); 289 pdram_timing->trsth = ((DDR3_TRSTH * nmhz + 999) / 1000); 290 /* tREFI, average periodic refresh interval, 7.8us */ 291 pdram_timing->trefi = ((DDR3_TREFI_7_8_US * nmhz + 999) / 1000); 292 /* base timing */ 293 pdram_timing->trcd = pdram_timing->cl; 294 pdram_timing->trp = pdram_timing->cl; 295 pdram_timing->trppb = pdram_timing->cl; 296 tmp = ((DDR3_TWR * nmhz + 999) / 1000); 297 pdram_timing->twr = tmp; 298 pdram_timing->tdal = tmp + pdram_timing->trp; 299 if (tmp < 9) { 300 tmp = tmp - 4; 301 } else { 302 tmp += (tmp & 0x1) ? 1 : 0; 303 tmp = tmp >> 1; 304 } 305 if (pdram_timing->bl == 4) 306 pdram_timing->mr[0] = DDR3_BC4 307 | DDR3_CL(pdram_timing->cl) 308 | DDR3_WR(tmp); 309 else 310 pdram_timing->mr[0] = DDR3_BL8 311 | DDR3_CL(pdram_timing->cl) 312 | DDR3_WR(tmp); 313 tmp = ((DDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 314 pdram_timing->trtp = max(4, tmp); 315 pdram_timing->trc = 316 (((ddr3_trc_tfaw[ddr_speed_bin] >> 8) * nmhz + 999) / 1000); 317 tmp = ((DDR3_TRRD * nmhz + 999) / 1000); 318 pdram_timing->trrd = max(4, tmp); 319 pdram_timing->tccd = DDR3_TCCD; 320 tmp = ((DDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000); 321 pdram_timing->twtr = max(4, tmp); 322 pdram_timing->trtw = DDR3_TRTW; 323 pdram_timing->tras_max = 9 * pdram_timing->trefi; 324 pdram_timing->tras_min = ((DDR3_TRAS * nmhz + (nmhz >> 1) + 999) 325 / 1000); 326 pdram_timing->tfaw = 327 (((ddr3_trc_tfaw[ddr_speed_bin] & 0x0ff) * nmhz + 999) 328 / 1000); 329 /* tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb) */ 330 if (ddr_capability_per_die <= 0x4000000) 331 tmp = DDR3_TRFC_512MBIT; 332 else if (ddr_capability_per_die <= 0x8000000) 333 tmp = DDR3_TRFC_1GBIT; 334 else if (ddr_capability_per_die <= 0x10000000) 335 tmp = DDR3_TRFC_2GBIT; 336 else if (ddr_capability_per_die <= 0x20000000) 337 tmp = DDR3_TRFC_4GBIT; 338 else 339 tmp = DDR3_TRFC_8GBIT; 340 pdram_timing->trfc = (tmp * nmhz + 999) / 1000; 341 pdram_timing->txsnr = max(5, (((tmp + 10) * nmhz + 999) / 1000)); 342 pdram_timing->tdqsck_max = 0; 343 /*pd and sr*/ 344 pdram_timing->txsr = DDR3_TDLLK; 345 tmp = ((DDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 346 pdram_timing->txp = max(3, tmp); 347 tmp = ((DDR3_TXPDLL * nmhz + 999) / 1000); 348 pdram_timing->txpdll = max(10, tmp); 349 pdram_timing->tdllk = DDR3_TDLLK; 350 if (nmhz >= 533) 351 tmp = ((DDR3_TCKE_533MHZ * nmhz + 999) / 1000); 352 else 353 tmp = ((DDR3_TCKE_400MHZ * nmhz + (nmhz >> 1) + 999) / 1000); 354 pdram_timing->tcke = max(3, tmp); 355 pdram_timing->tckesr = (pdram_timing->tcke + 1); 356 tmp = ((DDR3_TCKSRE * nmhz + 999) / 1000); 357 pdram_timing->tcksre = max(5, tmp); 358 pdram_timing->tcksrx = max(5, tmp); 359 /*mode register timing*/ 360 tmp = ((DDR3_TMOD * nmhz + 999) / 1000); 361 pdram_timing->tmod = max(12, tmp); 362 pdram_timing->tmrd = DDR3_TMRD; 363 pdram_timing->tmrr = 0; 364 /*ODT*/ 365 pdram_timing->todton = pdram_timing->cwl - 2; 366 /*ZQ*/ 367 tmp = ((DDR3_TZQINIT * nmhz + 999) / 1000); 368 pdram_timing->tzqinit = max(512, tmp); 369 tmp = ((DDR3_TZQCS * nmhz + 999) / 1000); 370 pdram_timing->tzqcs = max(64, tmp); 371 tmp = ((DDR3_TZQOPER * nmhz + 999) / 1000); 372 pdram_timing->tzqoper = max(256, tmp); 373 /* write leveling */ 374 pdram_timing->twlmrd = DDR3_TWLMRD; 375 pdram_timing->twldqsen = DDR3_TWLDQSEN; 376 pdram_timing->twlo = ((DDR3_TWLO * nmhz + (nmhz >> 1) + 999) / 1000); 377 } 378 379 #define LPDDR2_TINIT1 (100) /* ns */ 380 #define LPDDR2_TINIT2 (5) /* tCK */ 381 #define LPDDR2_TINIT3 (200000) /* 200us */ 382 #define LPDDR2_TINIT4 (1000) /* 1us */ 383 #define LPDDR2_TINIT5 (10000) /* 10us */ 384 #define LPDDR2_TRSTL (0) /* tCK */ 385 #define LPDDR2_TRSTH (500000) /* 500us */ 386 #define LPDDR2_TREFI_3_9_US (3900) /* 3.9us */ 387 #define LPDDR2_TREFI_7_8_US (7800) /* 7.8us */ 388 389 /* base timing */ 390 #define LPDDR2_TRCD (24) /* tRCD,15ns(Fast)18ns(Typ)24ns(Slow) */ 391 #define LPDDR2_TRP_PB (18) /* tRPpb,15ns(Fast)18ns(Typ)24ns(Slow) */ 392 #define LPDDR2_TRP_AB_8_BANK (21) /* tRPab,18ns(Fast)21ns(Typ)27ns(Slow) */ 393 #define LPDDR2_TWR (15) /* tWR, max(3tCK,15ns) */ 394 #define LPDDR2_TRTP (7) /* tRTP, max(2tCK, 7.5ns) */ 395 #define LPDDR2_TRRD (10) /* tRRD, max(2tCK,10ns) */ 396 #define LPDDR2_TCCD (2) /* tCK */ 397 #define LPDDR2_TWTR_GREAT_200MHZ (7) /* ns */ 398 #define LPDDR2_TWTR_LITTLE_200MHZ (10) /* ns */ 399 #define LPDDR2_TRTW (0) /* tCK */ 400 #define LPDDR2_TRAS_MAX (70000) /* 70us */ 401 #define LPDDR2_TRAS (42) /* tRAS, max(3tCK,42ns) */ 402 #define LPDDR2_TFAW_GREAT_200MHZ (50) /* max(8tCK,50ns) */ 403 #define LPDDR2_TFAW_LITTLE_200MHZ (60) /* max(8tCK,60ns) */ 404 #define LPDDR2_TRFC_8GBIT (210) /* ns */ 405 #define LPDDR2_TRFC_4GBIT (130) /* ns */ 406 #define LPDDR2_TDQSCK_MIN (2) /* tDQSCKmin, 2.5ns */ 407 #define LPDDR2_TDQSCK_MAX (5) /* tDQSCKmax, 5.5ns */ 408 409 /*pd and sr*/ 410 #define LPDDR2_TXP (7) /* tXP, max(2tCK,7.5ns) */ 411 #define LPDDR2_TXPDLL (0) 412 #define LPDDR2_TDLLK (0) /* tCK */ 413 #define LPDDR2_TCKE (3) /* tCK */ 414 #define LPDDR2_TCKESR (15) /* tCKESR, max(3tCK,15ns) */ 415 #define LPDDR2_TCKSRE (1) /* tCK */ 416 #define LPDDR2_TCKSRX (2) /* tCK */ 417 418 /*mode register timing*/ 419 #define LPDDR2_TMOD (0) 420 #define LPDDR2_TMRD (5) /* tMRD, (=tMRW), 5 tCK */ 421 #define LPDDR2_TMRR (2) /* tCK */ 422 423 /*ZQ*/ 424 #define LPDDR2_TZQINIT (1000) /* ns */ 425 #define LPDDR2_TZQCS (90) /* tZQCS, max(6tCK,90ns) */ 426 #define LPDDR2_TZQCL (360) /* tZQCL, max(6tCK,360ns) */ 427 #define LPDDR2_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 428 429 /* 430 * Description: depend on input parameter "timing_config", 431 * and calculate all lpddr2 432 * spec timing to "pdram_timing" 433 * parameters: 434 * input: timing_config 435 * output: pdram_timing 436 */ 437 static void lpddr2_get_parameter(struct timing_related_config *timing_config, 438 struct dram_timing_t *pdram_timing) 439 { 440 uint32_t nmhz = timing_config->freq; 441 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 442 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp; 443 444 memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); 445 pdram_timing->mhz = nmhz; 446 pdram_timing->al = 0; 447 pdram_timing->bl = timing_config->bl; 448 449 /* 1066 933 800 667 533 400 333 450 * RL, 8 7 6 5 4 3 3 451 * WL, 4 4 3 2 2 1 1 452 */ 453 if (nmhz <= 266) { 454 pdram_timing->cl = 4; 455 pdram_timing->cwl = 2; 456 pdram_timing->mr[2] = LPDDR2_RL4_WL2; 457 } else if (nmhz <= 333) { 458 pdram_timing->cl = 5; 459 pdram_timing->cwl = 2; 460 pdram_timing->mr[2] = LPDDR2_RL5_WL2; 461 } else if (nmhz <= 400) { 462 pdram_timing->cl = 6; 463 pdram_timing->cwl = 3; 464 pdram_timing->mr[2] = LPDDR2_RL6_WL3; 465 } else if (nmhz <= 466) { 466 pdram_timing->cl = 7; 467 pdram_timing->cwl = 4; 468 pdram_timing->mr[2] = LPDDR2_RL7_WL4; 469 } else { 470 pdram_timing->cl = 8; 471 pdram_timing->cwl = 4; 472 pdram_timing->mr[2] = LPDDR2_RL8_WL4; 473 } 474 switch (timing_config->dramds) { 475 case 120: 476 pdram_timing->mr[3] = LPDDR2_DS_120; 477 break; 478 case 80: 479 pdram_timing->mr[3] = LPDDR2_DS_80; 480 break; 481 case 60: 482 pdram_timing->mr[3] = LPDDR2_DS_60; 483 break; 484 case 48: 485 pdram_timing->mr[3] = LPDDR2_DS_48; 486 break; 487 case 40: 488 pdram_timing->mr[3] = LPDDR2_DS_40; 489 break; 490 case 34: 491 default: 492 pdram_timing->mr[3] = LPDDR2_DS_34; 493 break; 494 } 495 pdram_timing->mr[0] = 0; 496 497 pdram_timing->tinit1 = (LPDDR2_TINIT1 * nmhz + 999) / 1000; 498 pdram_timing->tinit2 = LPDDR2_TINIT2; 499 pdram_timing->tinit3 = (LPDDR2_TINIT3 * nmhz + 999) / 1000; 500 pdram_timing->tinit4 = (LPDDR2_TINIT4 * nmhz + 999) / 1000; 501 pdram_timing->tinit5 = (LPDDR2_TINIT5 * nmhz + 999) / 1000; 502 pdram_timing->trstl = LPDDR2_TRSTL; 503 pdram_timing->trsth = (LPDDR2_TRSTH * nmhz + 999) / 1000; 504 /* 505 * tREFI, average periodic refresh interval, 506 * 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb) 507 */ 508 if (ddr_capability_per_die >= 0x10000000) 509 pdram_timing->trefi = (LPDDR2_TREFI_3_9_US * nmhz + 999) 510 / 1000; 511 else 512 pdram_timing->trefi = (LPDDR2_TREFI_7_8_US * nmhz + 999) 513 / 1000; 514 /* base timing */ 515 tmp = ((LPDDR2_TRCD * nmhz + 999) / 1000); 516 pdram_timing->trcd = max(3, tmp); 517 /* 518 * tRPpb, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow), 519 */ 520 trppb_tmp = ((LPDDR2_TRP_PB * nmhz + 999) / 1000); 521 trppb_tmp = max(3, trppb_tmp); 522 pdram_timing->trppb = trppb_tmp; 523 /* 524 * tRPab, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 525 * 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow)) 526 */ 527 trp_tmp = ((LPDDR2_TRP_AB_8_BANK * nmhz + 999) / 1000); 528 trp_tmp = max(3, trp_tmp); 529 pdram_timing->trp = trp_tmp; 530 twr_tmp = ((LPDDR2_TWR * nmhz + 999) / 1000); 531 twr_tmp = max(3, twr_tmp); 532 pdram_timing->twr = twr_tmp; 533 bl_tmp = (pdram_timing->bl == 16) ? LPDDR2_BL16 : 534 ((pdram_timing->bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4); 535 pdram_timing->mr[1] = bl_tmp | LPDDR2_N_WR(twr_tmp); 536 tmp = ((LPDDR2_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 537 pdram_timing->trtp = max(2, tmp); 538 tras_tmp = ((LPDDR2_TRAS * nmhz + 999) / 1000); 539 tras_tmp = max(3, tras_tmp); 540 pdram_timing->tras_min = tras_tmp; 541 pdram_timing->tras_max = ((LPDDR2_TRAS_MAX * nmhz + 999) / 1000); 542 pdram_timing->trc = (tras_tmp + trp_tmp); 543 tmp = ((LPDDR2_TRRD * nmhz + 999) / 1000); 544 pdram_timing->trrd = max(2, tmp); 545 pdram_timing->tccd = LPDDR2_TCCD; 546 /* tWTR, max(2tCK, 7.5ns(533-266MHz) 10ns(200-166MHz)) */ 547 if (nmhz > 200) 548 tmp = ((LPDDR2_TWTR_GREAT_200MHZ * nmhz + (nmhz >> 1) + 549 999) / 1000); 550 else 551 tmp = ((LPDDR2_TWTR_LITTLE_200MHZ * nmhz + 999) / 1000); 552 pdram_timing->twtr = max(2, tmp); 553 pdram_timing->trtw = LPDDR2_TRTW; 554 if (nmhz <= 200) 555 pdram_timing->tfaw = (LPDDR2_TFAW_LITTLE_200MHZ * nmhz + 999) 556 / 1000; 557 else 558 pdram_timing->tfaw = (LPDDR2_TFAW_GREAT_200MHZ * nmhz + 999) 559 / 1000; 560 /* tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb) */ 561 if (ddr_capability_per_die >= 0x40000000) { 562 pdram_timing->trfc = 563 (LPDDR2_TRFC_8GBIT * nmhz + 999) / 1000; 564 tmp = (((LPDDR2_TRFC_8GBIT + 10) * nmhz + 999) / 1000); 565 } else { 566 pdram_timing->trfc = 567 (LPDDR2_TRFC_4GBIT * nmhz + 999) / 1000; 568 tmp = (((LPDDR2_TRFC_4GBIT + 10) * nmhz + 999) / 1000); 569 } 570 if (tmp < 2) 571 tmp = 2; 572 pdram_timing->txsr = tmp; 573 pdram_timing->txsnr = tmp; 574 /* tdqsck use rounded down */ 575 pdram_timing->tdqsck = ((LPDDR2_TDQSCK_MIN * nmhz + (nmhz >> 1)) 576 / 1000); 577 pdram_timing->tdqsck_max = 578 ((LPDDR2_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999) 579 / 1000); 580 /* pd and sr */ 581 tmp = ((LPDDR2_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 582 pdram_timing->txp = max(2, tmp); 583 pdram_timing->txpdll = LPDDR2_TXPDLL; 584 pdram_timing->tdllk = LPDDR2_TDLLK; 585 pdram_timing->tcke = LPDDR2_TCKE; 586 tmp = ((LPDDR2_TCKESR * nmhz + 999) / 1000); 587 pdram_timing->tckesr = max(3, tmp); 588 pdram_timing->tcksre = LPDDR2_TCKSRE; 589 pdram_timing->tcksrx = LPDDR2_TCKSRX; 590 /* mode register timing */ 591 pdram_timing->tmod = LPDDR2_TMOD; 592 pdram_timing->tmrd = LPDDR2_TMRD; 593 pdram_timing->tmrr = LPDDR2_TMRR; 594 /* ZQ */ 595 pdram_timing->tzqinit = (LPDDR2_TZQINIT * nmhz + 999) / 1000; 596 tmp = ((LPDDR2_TZQCS * nmhz + 999) / 1000); 597 pdram_timing->tzqcs = max(6, tmp); 598 tmp = ((LPDDR2_TZQCL * nmhz + 999) / 1000); 599 pdram_timing->tzqoper = max(6, tmp); 600 tmp = ((LPDDR2_TZQRESET * nmhz + 999) / 1000); 601 pdram_timing->tzqreset = max(3, tmp); 602 } 603 604 #define LPDDR3_TINIT1 (100) /* ns */ 605 #define LPDDR3_TINIT2 (5) /* tCK */ 606 #define LPDDR3_TINIT3 (200000) /* 200us */ 607 #define LPDDR3_TINIT4 (1000) /* 1us */ 608 #define LPDDR3_TINIT5 (10000) /* 10us */ 609 #define LPDDR3_TRSTL (0) 610 #define LPDDR3_TRSTH (0) /* 500us */ 611 #define LPDDR3_TREFI_3_9_US (3900) /* 3.9us */ 612 613 /* base timging */ 614 #define LPDDR3_TRCD (18) /* tRCD,15ns(Fast)18ns(Typ)24ns(Slow) */ 615 #define LPDDR3_TRP_PB (18) /* tRPpb, 15ns(Fast) 18ns(Typ) 24ns(Slow) */ 616 #define LPDDR3_TRP_AB (21) /* tRPab, 18ns(Fast) 21ns(Typ) 27ns(Slow) */ 617 #define LPDDR3_TWR (15) /* tWR, max(4tCK,15ns) */ 618 #define LPDDR3_TRTP (7) /* tRTP, max(4tCK, 7.5ns) */ 619 #define LPDDR3_TRRD (10) /* tRRD, max(2tCK,10ns) */ 620 #define LPDDR3_TCCD (4) /* tCK */ 621 #define LPDDR3_TWTR (7) /* tWTR, max(4tCK, 7.5ns) */ 622 #define LPDDR3_TRTW (0) /* tCK register min valid value */ 623 #define LPDDR3_TRAS_MAX (70000) /* 70us */ 624 #define LPDDR3_TRAS (42) /* tRAS, max(3tCK,42ns) */ 625 #define LPDDR3_TFAW (50) /* tFAW,max(8tCK, 50ns) */ 626 #define LPDDR3_TRFC_8GBIT (210) /* tRFC, 130ns(4Gb) 210ns(>4Gb) */ 627 #define LPDDR3_TRFC_4GBIT (130) /* ns */ 628 #define LPDDR3_TDQSCK_MIN (2) /* tDQSCKmin,2.5ns */ 629 #define LPDDR3_TDQSCK_MAX (5) /* tDQSCKmax,5.5ns */ 630 631 /* pd and sr */ 632 #define LPDDR3_TXP (7) /* tXP, max(3tCK,7.5ns) */ 633 #define LPDDR3_TXPDLL (0) 634 #define LPDDR3_TCKE (7) /* tCKE, (max 7.5ns,3 tCK) */ 635 #define LPDDR3_TCKESR (15) /* tCKESR, max(3tCK,15ns) */ 636 #define LPDDR3_TCKSRE (2) /* tCKSRE=tCPDED, 2 tCK */ 637 #define LPDDR3_TCKSRX (2) /* tCKSRX, 2 tCK */ 638 639 /* mode register timing */ 640 #define LPDDR3_TMOD (0) 641 #define LPDDR3_TMRD (14) /* tMRD, (=tMRW), max(14ns, 10 tCK) */ 642 #define LPDDR3_TMRR (4) /* tMRR, 4 tCK */ 643 #define LPDDR3_TMRRI LPDDR3_TRCD 644 645 /* ODT */ 646 #define LPDDR3_TODTON (3) /* 3.5ns */ 647 648 /* ZQ */ 649 #define LPDDR3_TZQINIT (1000) /* 1us */ 650 #define LPDDR3_TZQCS (90) /* tZQCS, 90ns */ 651 #define LPDDR3_TZQCL (360) /* 360ns */ 652 #define LPDDR3_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 653 /* write leveling */ 654 #define LPDDR3_TWLMRD (40) /* ns */ 655 #define LPDDR3_TWLO (20) /* ns */ 656 #define LPDDR3_TWLDQSEN (25) /* ns */ 657 /* CA training */ 658 #define LPDDR3_TCACKEL (10) /* tCK */ 659 #define LPDDR3_TCAENT (10) /* tCK */ 660 #define LPDDR3_TCAMRD (20) /* tCK */ 661 #define LPDDR3_TCACKEH (10) /* tCK */ 662 #define LPDDR3_TCAEXT (10) /* tCK */ 663 #define LPDDR3_TADR (20) /* ns */ 664 #define LPDDR3_TMRZ (3) /* ns */ 665 666 /* 667 * Description: depend on input parameter "timing_config", 668 * and calculate all lpddr3 669 * spec timing to "pdram_timing" 670 * parameters: 671 * input: timing_config 672 * output: pdram_timing 673 */ 674 static void lpddr3_get_parameter(struct timing_related_config *timing_config, 675 struct dram_timing_t *pdram_timing) 676 { 677 uint32_t nmhz = timing_config->freq; 678 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 679 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp; 680 681 memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); 682 pdram_timing->mhz = nmhz; 683 pdram_timing->al = 0; 684 pdram_timing->bl = timing_config->bl; 685 686 /* 687 * Only support Write Latency Set A here 688 * 1066 933 800 733 667 600 533 400 166 689 * RL, 16 14 12 11 10 9 8 6 3 690 * WL, 8 8 6 6 6 5 4 3 1 691 */ 692 if (nmhz <= 400) { 693 pdram_timing->cl = 6; 694 pdram_timing->cwl = 3; 695 pdram_timing->mr[2] = LPDDR3_RL6_WL3; 696 } else if (nmhz <= 533) { 697 pdram_timing->cl = 8; 698 pdram_timing->cwl = 4; 699 pdram_timing->mr[2] = LPDDR3_RL8_WL4; 700 } else if (nmhz <= 600) { 701 pdram_timing->cl = 9; 702 pdram_timing->cwl = 5; 703 pdram_timing->mr[2] = LPDDR3_RL9_WL5; 704 } else if (nmhz <= 667) { 705 pdram_timing->cl = 10; 706 pdram_timing->cwl = 6; 707 pdram_timing->mr[2] = LPDDR3_RL10_WL6; 708 } else if (nmhz <= 733) { 709 pdram_timing->cl = 11; 710 pdram_timing->cwl = 6; 711 pdram_timing->mr[2] = LPDDR3_RL11_WL6; 712 } else if (nmhz <= 800) { 713 pdram_timing->cl = 12; 714 pdram_timing->cwl = 6; 715 pdram_timing->mr[2] = LPDDR3_RL12_WL6; 716 } else if (nmhz <= 933) { 717 pdram_timing->cl = 14; 718 pdram_timing->cwl = 8; 719 pdram_timing->mr[2] = LPDDR3_RL14_WL8; 720 } else { 721 pdram_timing->cl = 16; 722 pdram_timing->cwl = 8; 723 pdram_timing->mr[2] = LPDDR3_RL16_WL8; 724 } 725 switch (timing_config->dramds) { 726 case 80: 727 pdram_timing->mr[3] = LPDDR3_DS_80; 728 break; 729 case 60: 730 pdram_timing->mr[3] = LPDDR3_DS_60; 731 break; 732 case 48: 733 pdram_timing->mr[3] = LPDDR3_DS_48; 734 break; 735 case 40: 736 pdram_timing->mr[3] = LPDDR3_DS_40; 737 break; 738 case 3440: 739 pdram_timing->mr[3] = LPDDR3_DS_34D_40U; 740 break; 741 case 4048: 742 pdram_timing->mr[3] = LPDDR3_DS_40D_48U; 743 break; 744 case 3448: 745 pdram_timing->mr[3] = LPDDR3_DS_34D_48U; 746 break; 747 case 34: 748 default: 749 pdram_timing->mr[3] = LPDDR3_DS_34; 750 break; 751 } 752 pdram_timing->mr[0] = 0; 753 switch (timing_config->dramodt) { 754 case 60: 755 pdram_timing->mr11 = LPDDR3_ODT_60; 756 break; 757 case 120: 758 pdram_timing->mr11 = LPDDR3_ODT_120; 759 break; 760 case 240: 761 default: 762 pdram_timing->mr11 = LPDDR3_ODT_240; 763 break; 764 } 765 766 pdram_timing->tinit1 = (LPDDR3_TINIT1 * nmhz + 999) / 1000; 767 pdram_timing->tinit2 = LPDDR3_TINIT2; 768 pdram_timing->tinit3 = (LPDDR3_TINIT3 * nmhz + 999) / 1000; 769 pdram_timing->tinit4 = (LPDDR3_TINIT4 * nmhz + 999) / 1000; 770 pdram_timing->tinit5 = (LPDDR3_TINIT5 * nmhz + 999) / 1000; 771 pdram_timing->trstl = LPDDR3_TRSTL; 772 pdram_timing->trsth = (LPDDR3_TRSTH * nmhz + 999) / 1000; 773 /* tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb) */ 774 pdram_timing->trefi = (LPDDR3_TREFI_3_9_US * nmhz + 999) / 1000; 775 /* base timing */ 776 tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000); 777 pdram_timing->trcd = max(3, tmp); 778 trppb_tmp = ((LPDDR3_TRP_PB * nmhz + 999) / 1000); 779 trppb_tmp = max(3, trppb_tmp); 780 pdram_timing->trppb = trppb_tmp; 781 trp_tmp = ((LPDDR3_TRP_AB * nmhz + 999) / 1000); 782 trp_tmp = max(3, trp_tmp); 783 pdram_timing->trp = trp_tmp; 784 twr_tmp = ((LPDDR3_TWR * nmhz + 999) / 1000); 785 twr_tmp = max(4, twr_tmp); 786 pdram_timing->twr = twr_tmp; 787 if (twr_tmp <= 6) 788 twr_tmp = 6; 789 else if (twr_tmp <= 8) 790 twr_tmp = 8; 791 else if (twr_tmp <= 12) 792 twr_tmp = twr_tmp; 793 else if (twr_tmp <= 14) 794 twr_tmp = 14; 795 else 796 twr_tmp = 16; 797 if (twr_tmp > 9) 798 pdram_timing->mr[2] |= (1 << 4); /*enable nWR > 9*/ 799 twr_tmp = (twr_tmp > 9) ? (twr_tmp - 10) : (twr_tmp - 2); 800 bl_tmp = LPDDR3_BL8; 801 pdram_timing->mr[1] = bl_tmp | LPDDR3_N_WR(twr_tmp); 802 tmp = ((LPDDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 803 pdram_timing->trtp = max(4, tmp); 804 tras_tmp = ((LPDDR3_TRAS * nmhz + 999) / 1000); 805 tras_tmp = max(3, tras_tmp); 806 pdram_timing->tras_min = tras_tmp; 807 pdram_timing->trc = (tras_tmp + trp_tmp); 808 tmp = ((LPDDR3_TRRD * nmhz + 999) / 1000); 809 pdram_timing->trrd = max(2, tmp); 810 pdram_timing->tccd = LPDDR3_TCCD; 811 tmp = ((LPDDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000); 812 pdram_timing->twtr = max(4, tmp); 813 pdram_timing->trtw = ((LPDDR3_TRTW * nmhz + 999) / 1000); 814 pdram_timing->tras_max = ((LPDDR3_TRAS_MAX * nmhz + 999) / 1000); 815 tmp = (LPDDR3_TFAW * nmhz + 999) / 1000; 816 pdram_timing->tfaw = max(8, tmp); 817 if (ddr_capability_per_die > 0x20000000) { 818 pdram_timing->trfc = 819 (LPDDR3_TRFC_8GBIT * nmhz + 999) / 1000; 820 tmp = (((LPDDR3_TRFC_8GBIT + 10) * nmhz + 999) / 1000); 821 } else { 822 pdram_timing->trfc = 823 (LPDDR3_TRFC_4GBIT * nmhz + 999) / 1000; 824 tmp = (((LPDDR3_TRFC_4GBIT + 10) * nmhz + 999) / 1000); 825 } 826 pdram_timing->txsr = max(2, tmp); 827 pdram_timing->txsnr = max(2, tmp); 828 /* tdqsck use rounded down */ 829 pdram_timing->tdqsck = 830 ((LPDDR3_TDQSCK_MIN * nmhz + (nmhz >> 1)) 831 / 1000); 832 pdram_timing->tdqsck_max = 833 ((LPDDR3_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999) 834 / 1000); 835 /*pd and sr*/ 836 tmp = ((LPDDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 837 pdram_timing->txp = max(3, tmp); 838 pdram_timing->txpdll = LPDDR3_TXPDLL; 839 tmp = ((LPDDR3_TCKE * nmhz + (nmhz >> 1) + 999) / 1000); 840 pdram_timing->tcke = max(3, tmp); 841 tmp = ((LPDDR3_TCKESR * nmhz + 999) / 1000); 842 pdram_timing->tckesr = max(3, tmp); 843 pdram_timing->tcksre = LPDDR3_TCKSRE; 844 pdram_timing->tcksrx = LPDDR3_TCKSRX; 845 /*mode register timing*/ 846 pdram_timing->tmod = LPDDR3_TMOD; 847 tmp = ((LPDDR3_TMRD * nmhz + 999) / 1000); 848 pdram_timing->tmrd = max(10, tmp); 849 pdram_timing->tmrr = LPDDR3_TMRR; 850 tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000); 851 pdram_timing->tmrri = max(3, tmp); 852 /* ODT */ 853 pdram_timing->todton = (LPDDR3_TODTON * nmhz + (nmhz >> 1) + 999) 854 / 1000; 855 /* ZQ */ 856 pdram_timing->tzqinit = (LPDDR3_TZQINIT * nmhz + 999) / 1000; 857 pdram_timing->tzqcs = 858 ((LPDDR3_TZQCS * nmhz + 999) / 1000); 859 pdram_timing->tzqoper = 860 ((LPDDR3_TZQCL * nmhz + 999) / 1000); 861 tmp = ((LPDDR3_TZQRESET * nmhz + 999) / 1000); 862 pdram_timing->tzqreset = max(3, tmp); 863 /* write leveling */ 864 pdram_timing->twlmrd = (LPDDR3_TWLMRD * nmhz + 999) / 1000; 865 pdram_timing->twlo = (LPDDR3_TWLO * nmhz + 999) / 1000; 866 pdram_timing->twldqsen = (LPDDR3_TWLDQSEN * nmhz + 999) / 1000; 867 /* CA training */ 868 pdram_timing->tcackel = LPDDR3_TCACKEL; 869 pdram_timing->tcaent = LPDDR3_TCAENT; 870 pdram_timing->tcamrd = LPDDR3_TCAMRD; 871 pdram_timing->tcackeh = LPDDR3_TCACKEH; 872 pdram_timing->tcaext = LPDDR3_TCAEXT; 873 pdram_timing->tadr = (LPDDR3_TADR * nmhz + 999) / 1000; 874 pdram_timing->tmrz = (LPDDR3_TMRZ * nmhz + 999) / 1000; 875 pdram_timing->tcacd = pdram_timing->tadr + 2; 876 } 877 878 #define LPDDR4_TINIT1 (200000) /* 200us */ 879 #define LPDDR4_TINIT2 (10) /* 10ns */ 880 #define LPDDR4_TINIT3 (2000000) /* 2ms */ 881 #define LPDDR4_TINIT4 (5) /* tCK */ 882 #define LPDDR4_TINIT5 (2000) /* 2us */ 883 #define LPDDR4_TRSTL LPDDR4_TINIT1 884 #define LPDDR4_TRSTH LPDDR4_TINIT3 885 #define LPDDR4_TREFI_3_9_US (3900) /* 3.9us */ 886 887 /* base timging */ 888 #define LPDDR4_TRCD (18) /* tRCD, max(18ns,4tCK) */ 889 #define LPDDR4_TRP_PB (18) /* tRPpb, max(18ns, 4tCK) */ 890 #define LPDDR4_TRP_AB (21) /* tRPab, max(21ns, 4tCK) */ 891 #define LPDDR4_TRRD (10) /* tRRD, max(4tCK,10ns) */ 892 #define LPDDR4_TCCD_BL16 (8) /* tCK */ 893 #define LPDDR4_TCCD_BL32 (16) /* tCK */ 894 #define LPDDR4_TWTR (10) /* tWTR, max(8tCK, 10ns) */ 895 #define LPDDR4_TRTW (0) /* tCK register min valid value */ 896 #define LPDDR4_TRAS_MAX (70000) /* 70us */ 897 #define LPDDR4_TRAS (42) /* tRAS, max(3tCK,42ns) */ 898 #define LPDDR4_TFAW (40) /* tFAW,min 40ns) */ 899 #define LPDDR4_TRFC_12GBIT (280) /* tRFC, 280ns(>=12Gb) */ 900 #define LPDDR4_TRFC_6GBIT (180) /* 6Gb/8Gb 180ns */ 901 #define LPDDR4_TRFC_4GBIT (130) /* 4Gb 130ns */ 902 #define LPDDR4_TDQSCK_MIN (1) /* tDQSCKmin,1.5ns */ 903 #define LPDDR4_TDQSCK_MAX (3) /* tDQSCKmax,3.5ns */ 904 #define LPDDR4_TPPD (4) /* tCK */ 905 906 /* pd and sr */ 907 #define LPDDR4_TXP (7) /* tXP, max(5tCK,7.5ns) */ 908 #define LPDDR4_TCKE (7) /* tCKE, max(7.5ns,4 tCK) */ 909 #define LPDDR4_TESCKE (1) /* tESCKE, max(1.75ns, 3tCK) */ 910 #define LPDDR4_TSR (15) /* tSR, max(15ns, 3tCK) */ 911 #define LPDDR4_TCMDCKE (1) /* max(1.75ns, 3tCK) */ 912 #define LPDDR4_TCSCKE (1) /* 1.75ns */ 913 #define LPDDR4_TCKELCS (5) /* max(5ns, 5tCK) */ 914 #define LPDDR4_TCSCKEH (1) /* 1.75ns */ 915 #define LPDDR4_TCKEHCS (7) /* max(7.5ns, 5tCK) */ 916 #define LPDDR4_TMRWCKEL (14) /* max(14ns, 10tCK) */ 917 #define LPDDR4_TCKELCMD (7) /* max(7.5ns, 3tCK) */ 918 #define LPDDR4_TCKEHCMD (7) /* max(7.5ns, 3tCK) */ 919 #define LPDDR4_TCKELPD (7) /* max(7.5ns, 3tCK) */ 920 #define LPDDR4_TCKCKEL (7) /* max(7.5ns, 3tCK) */ 921 922 /* mode register timing */ 923 #define LPDDR4_TMRD (14) /* tMRD, (=tMRW), max(14ns, 10 tCK) */ 924 #define LPDDR4_TMRR (8) /* tMRR, 8 tCK */ 925 926 /* ODT */ 927 #define LPDDR4_TODTON (3) /* 3.5ns */ 928 929 /* ZQ */ 930 #define LPDDR4_TZQCAL (1000) /* 1us */ 931 #define LPDDR4_TZQLAT (30) /* tZQLAT, max(30ns,8tCK) */ 932 #define LPDDR4_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 933 #define LPDDR4_TZQCKE (1) /* tZQCKE, max(1.75ns, 3tCK) */ 934 935 /* write leveling */ 936 #define LPDDR4_TWLMRD (40) /* tCK */ 937 #define LPDDR4_TWLO (20) /* ns */ 938 #define LPDDR4_TWLDQSEN (20) /* tCK */ 939 940 /* CA training */ 941 #define LPDDR4_TCAENT (250) /* ns */ 942 #define LPDDR4_TADR (20) /* ns */ 943 #define LPDDR4_TMRZ (1) /* 1.5ns */ 944 #define LPDDR4_TVREF_LONG (250) /* ns */ 945 #define LPDDR4_TVREF_SHORT (100) /* ns */ 946 947 /* VRCG */ 948 #define LPDDR4_TVRCG_ENABLE (200) /* ns */ 949 #define LPDDR4_TVRCG_DISABLE (100) /* ns */ 950 951 /* FSP */ 952 #define LPDDR4_TFC_LONG (250) /* ns */ 953 #define LPDDR4_TCKFSPE (7) /* max(7.5ns, 4tCK) */ 954 #define LPDDR4_TCKFSPX (7) /* max(7.5ns, 4tCK) */ 955 956 /* 957 * Description: depend on input parameter "timing_config", 958 * and calculate all lpddr4 959 * spec timing to "pdram_timing" 960 * parameters: 961 * input: timing_config 962 * output: pdram_timing 963 */ 964 static void lpddr4_get_parameter(struct timing_related_config *timing_config, 965 struct dram_timing_t *pdram_timing) 966 { 967 uint32_t nmhz = timing_config->freq; 968 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 969 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp; 970 971 memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); 972 pdram_timing->mhz = nmhz; 973 pdram_timing->al = 0; 974 pdram_timing->bl = timing_config->bl; 975 976 /* 977 * Only support Write Latency Set A here 978 * 2133 1866 1600 1333 1066 800 533 266 979 * RL, 36 32 28 24 20 14 10 6 980 * WL, 18 16 14 12 10 8 6 4 981 * nWR, 40 34 30 24 20 16 10 6 982 * nRTP,16 14 12 10 8 8 8 8 983 */ 984 tmp = (timing_config->bl == 32) ? 1 : 0; 985 986 /* 987 * we always use WR preamble = 2tCK 988 * RD preamble = Static 989 */ 990 tmp |= (1 << 2); 991 if (nmhz <= 266) { 992 pdram_timing->cl = 6; 993 pdram_timing->cwl = 4; 994 pdram_timing->twr = 6; 995 pdram_timing->trtp = 8; 996 pdram_timing->mr[2] = LPDDR4_RL6_NRTP8 | LPDDR4_A_WL4; 997 } else if (nmhz <= 533) { 998 if (timing_config->rdbi) { 999 pdram_timing->cl = 12; 1000 pdram_timing->mr[2] = LPDDR4_RL12_NRTP8 | LPDDR4_A_WL6; 1001 } else { 1002 pdram_timing->cl = 10; 1003 pdram_timing->mr[2] = LPDDR4_RL10_NRTP8 | LPDDR4_A_WL6; 1004 } 1005 pdram_timing->cwl = 6; 1006 pdram_timing->twr = 10; 1007 pdram_timing->trtp = 8; 1008 tmp |= (1 << 4); 1009 } else if (nmhz <= 800) { 1010 if (timing_config->rdbi) { 1011 pdram_timing->cl = 16; 1012 pdram_timing->mr[2] = LPDDR4_RL16_NRTP8 | LPDDR4_A_WL8; 1013 } else { 1014 pdram_timing->cl = 14; 1015 pdram_timing->mr[2] = LPDDR4_RL14_NRTP8 | LPDDR4_A_WL8; 1016 } 1017 pdram_timing->cwl = 8; 1018 pdram_timing->twr = 16; 1019 pdram_timing->trtp = 8; 1020 tmp |= (2 << 4); 1021 } else if (nmhz <= 1066) { 1022 if (timing_config->rdbi) { 1023 pdram_timing->cl = 22; 1024 pdram_timing->mr[2] = LPDDR4_RL22_NRTP8 | LPDDR4_A_WL10; 1025 } else { 1026 pdram_timing->cl = 20; 1027 pdram_timing->mr[2] = LPDDR4_RL20_NRTP8 | LPDDR4_A_WL10; 1028 } 1029 pdram_timing->cwl = 10; 1030 pdram_timing->twr = 20; 1031 pdram_timing->trtp = 8; 1032 tmp |= (3 << 4); 1033 } else if (nmhz <= 1333) { 1034 if (timing_config->rdbi) { 1035 pdram_timing->cl = 28; 1036 pdram_timing->mr[2] = LPDDR4_RL28_NRTP10 | 1037 LPDDR4_A_WL12; 1038 } else { 1039 pdram_timing->cl = 24; 1040 pdram_timing->mr[2] = LPDDR4_RL24_NRTP10 | 1041 LPDDR4_A_WL12; 1042 } 1043 pdram_timing->cwl = 12; 1044 pdram_timing->twr = 24; 1045 pdram_timing->trtp = 10; 1046 tmp |= (4 << 4); 1047 } else if (nmhz <= 1600) { 1048 if (timing_config->rdbi) { 1049 pdram_timing->cl = 32; 1050 pdram_timing->mr[2] = LPDDR4_RL32_NRTP12 | 1051 LPDDR4_A_WL14; 1052 } else { 1053 pdram_timing->cl = 28; 1054 pdram_timing->mr[2] = LPDDR4_RL28_NRTP12 | 1055 LPDDR4_A_WL14; 1056 } 1057 pdram_timing->cwl = 14; 1058 pdram_timing->twr = 30; 1059 pdram_timing->trtp = 12; 1060 tmp |= (5 << 4); 1061 } else if (nmhz <= 1866) { 1062 if (timing_config->rdbi) { 1063 pdram_timing->cl = 36; 1064 pdram_timing->mr[2] = LPDDR4_RL36_NRTP14 | 1065 LPDDR4_A_WL16; 1066 } else { 1067 pdram_timing->cl = 32; 1068 pdram_timing->mr[2] = LPDDR4_RL32_NRTP14 | 1069 LPDDR4_A_WL16; 1070 } 1071 pdram_timing->cwl = 16; 1072 pdram_timing->twr = 34; 1073 pdram_timing->trtp = 14; 1074 tmp |= (6 << 4); 1075 } else { 1076 if (timing_config->rdbi) { 1077 pdram_timing->cl = 40; 1078 pdram_timing->mr[2] = LPDDR4_RL40_NRTP16 | 1079 LPDDR4_A_WL18; 1080 } else { 1081 pdram_timing->cl = 36; 1082 pdram_timing->mr[2] = LPDDR4_RL36_NRTP16 | 1083 LPDDR4_A_WL18; 1084 } 1085 pdram_timing->cwl = 18; 1086 pdram_timing->twr = 40; 1087 pdram_timing->trtp = 16; 1088 tmp |= (7 << 4); 1089 } 1090 pdram_timing->mr[1] = tmp; 1091 tmp = (timing_config->rdbi ? LPDDR4_DBI_RD_EN : 0) | 1092 (timing_config->wdbi ? LPDDR4_DBI_WR_EN : 0); 1093 switch (timing_config->dramds) { 1094 case 240: 1095 pdram_timing->mr[3] = LPDDR4_PDDS_240 | tmp; 1096 break; 1097 case 120: 1098 pdram_timing->mr[3] = LPDDR4_PDDS_120 | tmp; 1099 break; 1100 case 80: 1101 pdram_timing->mr[3] = LPDDR4_PDDS_80 | tmp; 1102 break; 1103 case 60: 1104 pdram_timing->mr[3] = LPDDR4_PDDS_60 | tmp; 1105 break; 1106 case 48: 1107 pdram_timing->mr[3] = LPDDR4_PDDS_48 | tmp; 1108 break; 1109 case 40: 1110 default: 1111 pdram_timing->mr[3] = LPDDR4_PDDS_40 | tmp; 1112 break; 1113 } 1114 pdram_timing->mr[0] = 0; 1115 switch (timing_config->dramodt) { 1116 case 240: 1117 tmp = LPDDR4_DQODT_240; 1118 break; 1119 case 120: 1120 tmp = LPDDR4_DQODT_120; 1121 break; 1122 case 80: 1123 tmp = LPDDR4_DQODT_80; 1124 break; 1125 case 60: 1126 tmp = LPDDR4_DQODT_60; 1127 break; 1128 case 48: 1129 tmp = LPDDR4_DQODT_48; 1130 break; 1131 case 40: 1132 default: 1133 tmp = LPDDR4_DQODT_40; 1134 break; 1135 } 1136 switch (timing_config->caodt) { 1137 case 240: 1138 pdram_timing->mr11 = LPDDR4_CAODT_240 | tmp; 1139 break; 1140 case 120: 1141 pdram_timing->mr11 = LPDDR4_CAODT_120 | tmp; 1142 break; 1143 case 80: 1144 pdram_timing->mr11 = LPDDR4_CAODT_80 | tmp; 1145 break; 1146 case 60: 1147 pdram_timing->mr11 = LPDDR4_CAODT_60 | tmp; 1148 break; 1149 case 48: 1150 pdram_timing->mr11 = LPDDR4_CAODT_48 | tmp; 1151 break; 1152 case 40: 1153 default: 1154 pdram_timing->mr11 = LPDDR4_CAODT_40 | tmp; 1155 break; 1156 } 1157 1158 pdram_timing->tinit1 = (LPDDR4_TINIT1 * nmhz + 999) / 1000; 1159 pdram_timing->tinit2 = (LPDDR4_TINIT2 * nmhz + 999) / 1000; 1160 pdram_timing->tinit3 = (LPDDR4_TINIT3 * nmhz + 999) / 1000; 1161 pdram_timing->tinit4 = (LPDDR4_TINIT4 * nmhz + 999) / 1000; 1162 pdram_timing->tinit5 = (LPDDR4_TINIT5 * nmhz + 999) / 1000; 1163 pdram_timing->trstl = (LPDDR4_TRSTL * nmhz + 999) / 1000; 1164 pdram_timing->trsth = (LPDDR4_TRSTH * nmhz + 999) / 1000; 1165 /* tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb) */ 1166 pdram_timing->trefi = (LPDDR4_TREFI_3_9_US * nmhz + 999) / 1000; 1167 /* base timing */ 1168 tmp = ((LPDDR4_TRCD * nmhz + 999) / 1000); 1169 pdram_timing->trcd = max(4, tmp); 1170 trppb_tmp = ((LPDDR4_TRP_PB * nmhz + 999) / 1000); 1171 trppb_tmp = max(4, trppb_tmp); 1172 pdram_timing->trppb = trppb_tmp; 1173 trp_tmp = ((LPDDR4_TRP_AB * nmhz + 999) / 1000); 1174 trp_tmp = max(4, trp_tmp); 1175 pdram_timing->trp = trp_tmp; 1176 tras_tmp = ((LPDDR4_TRAS * nmhz + 999) / 1000); 1177 tras_tmp = max(3, tras_tmp); 1178 pdram_timing->tras_min = tras_tmp; 1179 pdram_timing->trc = (tras_tmp + trp_tmp); 1180 tmp = ((LPDDR4_TRRD * nmhz + 999) / 1000); 1181 pdram_timing->trrd = max(4, tmp); 1182 if (timing_config->bl == 32) 1183 pdram_timing->tccd = LPDDR4_TCCD_BL16; 1184 else 1185 pdram_timing->tccd = LPDDR4_TCCD_BL32; 1186 pdram_timing->tccdmw = 4 * pdram_timing->tccd; 1187 tmp = ((LPDDR4_TWTR * nmhz + 999) / 1000); 1188 pdram_timing->twtr = max(8, tmp); 1189 pdram_timing->trtw = ((LPDDR4_TRTW * nmhz + 999) / 1000); 1190 pdram_timing->tras_max = ((LPDDR4_TRAS_MAX * nmhz + 999) / 1000); 1191 pdram_timing->tfaw = (LPDDR4_TFAW * nmhz + 999) / 1000; 1192 if (ddr_capability_per_die > 0x60000000) { 1193 /* >= 12Gb */ 1194 pdram_timing->trfc = 1195 (LPDDR4_TRFC_12GBIT * nmhz + 999) / 1000; 1196 tmp = (((LPDDR4_TRFC_12GBIT + 7) * nmhz + (nmhz >> 1) + 1197 999) / 1000); 1198 } else if (ddr_capability_per_die > 0x30000000) { 1199 pdram_timing->trfc = 1200 (LPDDR4_TRFC_6GBIT * nmhz + 999) / 1000; 1201 tmp = (((LPDDR4_TRFC_6GBIT + 7) * nmhz + (nmhz >> 1) + 1202 999) / 1000); 1203 } else { 1204 pdram_timing->trfc = 1205 (LPDDR4_TRFC_4GBIT * nmhz + 999) / 1000; 1206 tmp = (((LPDDR4_TRFC_4GBIT + 7) * nmhz + (nmhz >> 1) + 1207 999) / 1000); 1208 } 1209 pdram_timing->txsr = max(2, tmp); 1210 pdram_timing->txsnr = max(2, tmp); 1211 /* tdqsck use rounded down */ 1212 pdram_timing->tdqsck = ((LPDDR4_TDQSCK_MIN * nmhz + 1213 (nmhz >> 1)) / 1000); 1214 pdram_timing->tdqsck_max = ((LPDDR4_TDQSCK_MAX * nmhz + 1215 (nmhz >> 1) + 999) / 1000); 1216 pdram_timing->tppd = LPDDR4_TPPD; 1217 /* pd and sr */ 1218 tmp = ((LPDDR4_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 1219 pdram_timing->txp = max(5, tmp); 1220 tmp = ((LPDDR4_TCKE * nmhz + (nmhz >> 1) + 999) / 1000); 1221 pdram_timing->tcke = max(4, tmp); 1222 tmp = ((LPDDR4_TESCKE * nmhz + 1223 ((nmhz * 3) / 4) + 1224 999) / 1000); 1225 pdram_timing->tescke = max(3, tmp); 1226 tmp = ((LPDDR4_TSR * nmhz + 999) / 1000); 1227 pdram_timing->tsr = max(3, tmp); 1228 tmp = ((LPDDR4_TCMDCKE * nmhz + 1229 ((nmhz * 3) / 4) + 1230 999) / 1000); 1231 pdram_timing->tcmdcke = max(3, tmp); 1232 pdram_timing->tcscke = ((LPDDR4_TCSCKE * nmhz + 1233 ((nmhz * 3) / 4) + 1234 999) / 1000); 1235 tmp = ((LPDDR4_TCKELCS * nmhz + 999) / 1000); 1236 pdram_timing->tckelcs = max(5, tmp); 1237 pdram_timing->tcsckeh = ((LPDDR4_TCSCKEH * nmhz + 1238 ((nmhz * 3) / 4) + 1239 999) / 1000); 1240 tmp = ((LPDDR4_TCKEHCS * nmhz + 1241 (nmhz >> 1) + 999) / 1000); 1242 pdram_timing->tckehcs = max(5, tmp); 1243 tmp = ((LPDDR4_TMRWCKEL * nmhz + 999) / 1000); 1244 pdram_timing->tmrwckel = max(10, tmp); 1245 tmp = ((LPDDR4_TCKELCMD * nmhz + (nmhz >> 1) + 1246 999) / 1000); 1247 pdram_timing->tckelcmd = max(3, tmp); 1248 tmp = ((LPDDR4_TCKEHCMD * nmhz + (nmhz >> 1) + 1249 999) / 1000); 1250 pdram_timing->tckehcmd = max(3, tmp); 1251 tmp = ((LPDDR4_TCKELPD * nmhz + (nmhz >> 1) + 1252 999) / 1000); 1253 pdram_timing->tckelpd = max(3, tmp); 1254 tmp = ((LPDDR4_TCKCKEL * nmhz + (nmhz >> 1) + 1255 999) / 1000); 1256 pdram_timing->tckckel = max(3, tmp); 1257 /* mode register timing */ 1258 tmp = ((LPDDR4_TMRD * nmhz + 999) / 1000); 1259 pdram_timing->tmrd = max(10, tmp); 1260 pdram_timing->tmrr = LPDDR4_TMRR; 1261 pdram_timing->tmrri = pdram_timing->trcd + 3; 1262 /* ODT */ 1263 pdram_timing->todton = (LPDDR4_TODTON * nmhz + (nmhz >> 1) + 999) 1264 / 1000; 1265 /* ZQ */ 1266 pdram_timing->tzqcal = (LPDDR4_TZQCAL * nmhz + 999) / 1000; 1267 tmp = ((LPDDR4_TZQLAT * nmhz + 999) / 1000); 1268 pdram_timing->tzqlat = max(8, tmp); 1269 tmp = ((LPDDR4_TZQRESET * nmhz + 999) / 1000); 1270 pdram_timing->tzqreset = max(3, tmp); 1271 tmp = ((LPDDR4_TZQCKE * nmhz + 1272 ((nmhz * 3) / 4) + 1273 999) / 1000); 1274 pdram_timing->tzqcke = max(3, tmp); 1275 /* write leveling */ 1276 pdram_timing->twlmrd = LPDDR4_TWLMRD; 1277 pdram_timing->twlo = (LPDDR4_TWLO * nmhz + 999) / 1000; 1278 pdram_timing->twldqsen = LPDDR4_TWLDQSEN; 1279 /* CA training */ 1280 pdram_timing->tcaent = (LPDDR4_TCAENT * nmhz + 999) / 1000; 1281 pdram_timing->tadr = (LPDDR4_TADR * nmhz + 999) / 1000; 1282 pdram_timing->tmrz = (LPDDR4_TMRZ * nmhz + (nmhz >> 1) + 999) / 1000; 1283 pdram_timing->tvref_long = (LPDDR4_TVREF_LONG * nmhz + 999) / 1000; 1284 pdram_timing->tvref_short = (LPDDR4_TVREF_SHORT * nmhz + 999) / 1000; 1285 /* VRCG */ 1286 pdram_timing->tvrcg_enable = (LPDDR4_TVRCG_ENABLE * nmhz + 1287 999) / 1000; 1288 pdram_timing->tvrcg_disable = (LPDDR4_TVRCG_DISABLE * nmhz + 1289 999) / 1000; 1290 /* FSP */ 1291 pdram_timing->tfc_long = (LPDDR4_TFC_LONG * nmhz + 999) / 1000; 1292 tmp = (LPDDR4_TCKFSPE * nmhz + (nmhz >> 1) + 999) / 1000; 1293 pdram_timing->tckfspe = max(4, tmp); 1294 tmp = (LPDDR4_TCKFSPX * nmhz + (nmhz >> 1) + 999) / 1000; 1295 pdram_timing->tckfspx = max(4, tmp); 1296 } 1297 1298 /* 1299 * Description: depend on input parameter "timing_config", 1300 * and calculate correspond "dram_type" 1301 * spec timing to "pdram_timing" 1302 * parameters: 1303 * input: timing_config 1304 * output: pdram_timing 1305 * NOTE: MR ODT is set, need to disable by controller 1306 */ 1307 void dram_get_parameter(struct timing_related_config *timing_config, 1308 struct dram_timing_t *pdram_timing) 1309 { 1310 switch (timing_config->dram_type) { 1311 case DDR3: 1312 ddr3_get_parameter(timing_config, pdram_timing); 1313 break; 1314 case LPDDR2: 1315 lpddr2_get_parameter(timing_config, pdram_timing); 1316 break; 1317 case LPDDR3: 1318 lpddr3_get_parameter(timing_config, pdram_timing); 1319 break; 1320 case LPDDR4: 1321 lpddr4_get_parameter(timing_config, pdram_timing); 1322 break; 1323 } 1324 } 1325