1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bl_common.h> 34 #include <context.h> 35 #include <context_mgmt.h> 36 #include <debug.h> 37 #include <memctrl.h> 38 #include <mmio.h> 39 #include <platform.h> 40 #include <platform_def.h> 41 #include <pmc.h> 42 #include <psci.h> 43 #include <tegra_def.h> 44 #include <tegra_private.h> 45 46 extern uint64_t tegra_bl31_phys_base; 47 extern uint64_t tegra_sec_entry_point; 48 49 /* 50 * The following platform setup functions are weakly defined. They 51 * provide typical implementations that will be overridden by a SoC. 52 */ 53 #pragma weak tegra_soc_pwr_domain_suspend 54 #pragma weak tegra_soc_pwr_domain_on 55 #pragma weak tegra_soc_pwr_domain_off 56 #pragma weak tegra_soc_pwr_domain_on_finish 57 #pragma weak tegra_soc_pwr_domain_power_down_wfi 58 #pragma weak tegra_soc_prepare_system_reset 59 #pragma weak tegra_soc_prepare_system_off 60 #pragma weak tegra_soc_get_target_pwr_state 61 62 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 63 { 64 return PSCI_E_NOT_SUPPORTED; 65 } 66 67 int tegra_soc_pwr_domain_on(u_register_t mpidr) 68 { 69 return PSCI_E_SUCCESS; 70 } 71 72 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 73 { 74 return PSCI_E_SUCCESS; 75 } 76 77 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 78 { 79 return PSCI_E_SUCCESS; 80 } 81 82 int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) 83 { 84 return PSCI_E_SUCCESS; 85 } 86 87 int tegra_soc_prepare_system_reset(void) 88 { 89 return PSCI_E_SUCCESS; 90 } 91 92 __dead2 void tegra_soc_prepare_system_off(void) 93 { 94 ERROR("Tegra System Off: operation not handled.\n"); 95 panic(); 96 } 97 98 plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, 99 const plat_local_state_t *states, 100 unsigned int ncpu) 101 { 102 plat_local_state_t target = PLAT_MAX_RET_STATE, temp; 103 104 assert(ncpu); 105 106 do { 107 temp = *states++; 108 if ((temp > target) && (temp != PLAT_MAX_OFF_STATE)) 109 target = temp; 110 } while (--ncpu); 111 112 return target; 113 } 114 115 /******************************************************************************* 116 * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND` 117 * call to get the `power_state` parameter. This allows the platform to encode 118 * the appropriate State-ID field within the `power_state` parameter which can 119 * be utilized in `pwr_domain_suspend()` to suspend to system affinity level. 120 ******************************************************************************/ 121 void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state) 122 { 123 /* all affinities use system suspend state id */ 124 for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) 125 req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN; 126 } 127 128 /******************************************************************************* 129 * Handler called when an affinity instance is about to enter standby. 130 ******************************************************************************/ 131 void tegra_cpu_standby(plat_local_state_t cpu_state) 132 { 133 /* 134 * Enter standby state 135 * dsb is good practice before using wfi to enter low power states 136 */ 137 dsb(); 138 wfi(); 139 } 140 141 /******************************************************************************* 142 * Handler called when an affinity instance is about to be turned on. The 143 * level and mpidr determine the affinity instance. 144 ******************************************************************************/ 145 int tegra_pwr_domain_on(u_register_t mpidr) 146 { 147 return tegra_soc_pwr_domain_on(mpidr); 148 } 149 150 /******************************************************************************* 151 * Handler called when a power domain is about to be turned off. The 152 * target_state encodes the power state that each level should transition to. 153 ******************************************************************************/ 154 void tegra_pwr_domain_off(const psci_power_state_t *target_state) 155 { 156 tegra_soc_pwr_domain_off(target_state); 157 } 158 159 /******************************************************************************* 160 * Handler called when a power domain is about to be suspended. The 161 * target_state encodes the power state that each level should transition to. 162 ******************************************************************************/ 163 void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) 164 { 165 tegra_soc_pwr_domain_suspend(target_state); 166 167 /* disable GICC */ 168 tegra_gic_cpuif_deactivate(); 169 } 170 171 /******************************************************************************* 172 * Handler called at the end of the power domain suspend sequence. The 173 * target_state encodes the power state that each level should transition to. 174 ******************************************************************************/ 175 __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t 176 *target_state) 177 { 178 /* call the chip's power down handler */ 179 tegra_soc_pwr_domain_power_down_wfi(target_state); 180 181 /* enter power down state */ 182 wfi(); 183 184 /* we can never reach here */ 185 ERROR("%s: operation not handled.\n", __func__); 186 panic(); 187 } 188 189 /******************************************************************************* 190 * Handler called when a power domain has just been powered on after 191 * being turned off earlier. The target_state encodes the low power state that 192 * each level has woken up from. 193 ******************************************************************************/ 194 void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) 195 { 196 plat_params_from_bl2_t *plat_params; 197 198 /* 199 * Initialize the GIC cpu and distributor interfaces 200 */ 201 plat_gic_setup(); 202 203 /* 204 * Check if we are exiting from deep sleep. 205 */ 206 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 207 PSTATE_ID_SOC_POWERDN) { 208 209 /* 210 * Restore Memory Controller settings as it loses state 211 * during system suspend. 212 */ 213 tegra_memctrl_restore_settings(); 214 215 /* 216 * Security configuration to allow DRAM/device access. 217 */ 218 plat_params = bl31_get_plat_params(); 219 tegra_memctrl_tzdram_setup(plat_params->tzdram_base, 220 plat_params->tzdram_size); 221 222 /* 223 * Set up the TZRAM memory aperture to allow only secure world 224 * access 225 */ 226 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 227 } 228 229 /* 230 * Reset hardware settings. 231 */ 232 tegra_soc_pwr_domain_on_finish(target_state); 233 } 234 235 /******************************************************************************* 236 * Handler called when a power domain has just been powered on after 237 * having been suspended earlier. The target_state encodes the low power state 238 * that each level has woken up from. 239 ******************************************************************************/ 240 void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 241 { 242 tegra_pwr_domain_on_finish(target_state); 243 } 244 245 /******************************************************************************* 246 * Handler called when the system wants to be powered off 247 ******************************************************************************/ 248 __dead2 void tegra_system_off(void) 249 { 250 INFO("Powering down system...\n"); 251 252 tegra_soc_prepare_system_off(); 253 } 254 255 /******************************************************************************* 256 * Handler called when the system wants to be restarted. 257 ******************************************************************************/ 258 __dead2 void tegra_system_reset(void) 259 { 260 INFO("Restarting system...\n"); 261 262 /* per-SoC system reset handler */ 263 tegra_soc_prepare_system_reset(); 264 265 /* 266 * Program the PMC in order to restart the system. 267 */ 268 tegra_pmc_system_reset(); 269 } 270 271 /******************************************************************************* 272 * Handler called to check the validity of the power state parameter. 273 ******************************************************************************/ 274 int32_t tegra_validate_power_state(unsigned int power_state, 275 psci_power_state_t *req_state) 276 { 277 assert(req_state); 278 279 return tegra_soc_validate_power_state(power_state, req_state); 280 } 281 282 /******************************************************************************* 283 * Platform handler called to check the validity of the non secure entrypoint. 284 ******************************************************************************/ 285 int tegra_validate_ns_entrypoint(uintptr_t entrypoint) 286 { 287 /* 288 * Check if the non secure entrypoint lies within the non 289 * secure DRAM. 290 */ 291 if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END)) 292 return PSCI_E_SUCCESS; 293 294 return PSCI_E_INVALID_ADDRESS; 295 } 296 297 /******************************************************************************* 298 * Export the platform handlers to enable psci to invoke them 299 ******************************************************************************/ 300 static const plat_psci_ops_t tegra_plat_psci_ops = { 301 .cpu_standby = tegra_cpu_standby, 302 .pwr_domain_on = tegra_pwr_domain_on, 303 .pwr_domain_off = tegra_pwr_domain_off, 304 .pwr_domain_suspend = tegra_pwr_domain_suspend, 305 .pwr_domain_on_finish = tegra_pwr_domain_on_finish, 306 .pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish, 307 .pwr_domain_pwr_down_wfi = tegra_pwr_domain_power_down_wfi, 308 .system_off = tegra_system_off, 309 .system_reset = tegra_system_reset, 310 .validate_power_state = tegra_validate_power_state, 311 .validate_ns_entrypoint = tegra_validate_ns_entrypoint, 312 .get_sys_suspend_power_state = tegra_get_sys_suspend_power_state, 313 }; 314 315 /******************************************************************************* 316 * Export the platform specific power ops and initialize Power Controller 317 ******************************************************************************/ 318 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 319 const plat_psci_ops_t **psci_ops) 320 { 321 psci_power_state_t target_state = { { PSCI_LOCAL_STATE_RUN } }; 322 323 /* 324 * Flush entrypoint variable to PoC since it will be 325 * accessed after a reset with the caches turned off. 326 */ 327 tegra_sec_entry_point = sec_entrypoint; 328 flush_dcache_range((uint64_t)&tegra_sec_entry_point, sizeof(uint64_t)); 329 330 /* 331 * Reset hardware settings. 332 */ 333 tegra_soc_pwr_domain_on_finish(&target_state); 334 335 /* 336 * Initialize PSCI ops struct 337 */ 338 *psci_ops = &tegra_plat_psci_ops; 339 340 return 0; 341 } 342 343 /******************************************************************************* 344 * Platform handler to calculate the proper target power level at the 345 * specified affinity level 346 ******************************************************************************/ 347 plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, 348 const plat_local_state_t *states, 349 unsigned int ncpu) 350 { 351 return tegra_soc_get_target_pwr_state(lvl, states, ncpu); 352 } 353