1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl31.h> 35 #include <bl_common.h> 36 #include <console.h> 37 #include <cortex_a57.h> 38 #include <cortex_a53.h> 39 #include <debug.h> 40 #include <denver.h> 41 #include <errno.h> 42 #include <memctrl.h> 43 #include <mmio.h> 44 #include <platform.h> 45 #include <platform_def.h> 46 #include <stddef.h> 47 #include <string.h> 48 #include <tegra_def.h> 49 #include <tegra_private.h> 50 51 extern void zeromem16(void *mem, unsigned int length); 52 53 /******************************************************************************* 54 * Declarations of linker defined symbols which will help us find the layout 55 * of trusted SRAM 56 ******************************************************************************/ 57 extern unsigned long __RO_START__; 58 extern unsigned long __RO_END__; 59 extern unsigned long __BL31_END__; 60 61 extern uint64_t tegra_bl31_phys_base; 62 extern uint64_t tegra_console_base; 63 64 /* 65 * The next 3 constants identify the extents of the code, RO data region and the 66 * limit of the BL3-1 image. These addresses are used by the MMU setup code and 67 * therefore they must be page-aligned. It is the responsibility of the linker 68 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 69 * refer to page-aligned addresses. 70 */ 71 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 72 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 73 #define BL31_END (unsigned long)(&__BL31_END__) 74 75 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 76 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 77 .tzdram_size = (uint64_t)TZDRAM_SIZE 78 }; 79 80 /******************************************************************************* 81 * This variable holds the non-secure image entry address 82 ******************************************************************************/ 83 extern uint64_t ns_image_entrypoint; 84 85 /******************************************************************************* 86 * The following platform setup functions are weakly defined. They 87 * provide typical implementations that will be overridden by a SoC. 88 ******************************************************************************/ 89 #pragma weak plat_early_platform_setup 90 #pragma weak plat_get_bl31_params 91 #pragma weak plat_get_bl31_plat_params 92 93 void plat_early_platform_setup(void) 94 { 95 ; /* do nothing */ 96 } 97 98 bl31_params_t *plat_get_bl31_params(void) 99 { 100 return NULL; 101 } 102 103 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 104 { 105 return NULL; 106 } 107 108 /******************************************************************************* 109 * Return a pointer to the 'entry_point_info' structure of the next image for 110 * security state specified. BL33 corresponds to the non-secure image type 111 * while BL32 corresponds to the secure image type. 112 ******************************************************************************/ 113 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 114 { 115 if (type == NON_SECURE) 116 return &bl33_image_ep_info; 117 118 /* return BL32 entry point info if it is valid */ 119 if (type == SECURE && bl32_image_ep_info.pc) 120 return &bl32_image_ep_info; 121 122 return NULL; 123 } 124 125 /******************************************************************************* 126 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 127 * passes this platform specific information. 128 ******************************************************************************/ 129 plat_params_from_bl2_t *bl31_get_plat_params(void) 130 { 131 return &plat_bl31_params_from_bl2; 132 } 133 134 /******************************************************************************* 135 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 136 * info. 137 ******************************************************************************/ 138 void bl31_early_platform_setup(bl31_params_t *from_bl2, 139 void *plat_params_from_bl2) 140 { 141 plat_params_from_bl2_t *plat_params = 142 (plat_params_from_bl2_t *)plat_params_from_bl2; 143 #if DEBUG 144 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 145 #endif 146 image_info_t bl32_img_info = { {0} }; 147 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end; 148 149 /* 150 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 151 * there's no argument to relay from a previous bootloader. Platforms 152 * might use custom ways to get arguments, so provide handlers which 153 * they can override. 154 */ 155 if (from_bl2 == NULL) 156 from_bl2 = plat_get_bl31_params(); 157 if (plat_params == NULL) 158 plat_params = plat_get_bl31_plat_params(); 159 160 /* 161 * Copy BL3-3, BL3-2 entry point information. 162 * They are stored in Secure RAM, in BL2's address space. 163 */ 164 assert(from_bl2); 165 assert(from_bl2->bl33_ep_info); 166 bl33_image_ep_info = *from_bl2->bl33_ep_info; 167 168 if (from_bl2->bl32_ep_info) 169 bl32_image_ep_info = *from_bl2->bl32_ep_info; 170 171 /* 172 * Parse platform specific parameters - TZDRAM aperture base and size 173 */ 174 assert(plat_params); 175 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; 176 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 177 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; 178 179 /* 180 * It is very important that we run either from TZDRAM or TZSRAM base. 181 * Add an explicit check here. 182 */ 183 if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) && 184 (TEGRA_TZRAM_BASE != BL31_BASE)) 185 panic(); 186 187 /* 188 * Get the base address of the UART controller to be used for the 189 * console 190 */ 191 assert(plat_params->uart_id); 192 tegra_console_base = plat_get_console_from_id(plat_params->uart_id); 193 194 /* 195 * Configure the UART port to be used as the console 196 */ 197 assert(tegra_console_base); 198 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, 199 TEGRA_CONSOLE_BAUDRATE); 200 201 /* Initialise crash console */ 202 plat_crash_console_init(); 203 204 /* 205 * Do initial security configuration to allow DRAM/device access. 206 */ 207 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, 208 plat_bl31_params_from_bl2.tzdram_size); 209 210 /* 211 * The previous bootloader might not have placed the BL32 image 212 * inside the TZDRAM. We check the BL32 image info to find out 213 * the base/PC values and relocate the image if necessary. 214 */ 215 if (from_bl2->bl32_image_info) { 216 217 bl32_img_info = *from_bl2->bl32_image_info; 218 219 /* Relocate BL32 if it resides outside of the TZDRAM */ 220 tzdram_start = plat_bl31_params_from_bl2.tzdram_base; 221 tzdram_end = plat_bl31_params_from_bl2.tzdram_base + 222 plat_bl31_params_from_bl2.tzdram_size; 223 bl32_start = bl32_img_info.image_base; 224 bl32_end = bl32_img_info.image_base + bl32_img_info.image_size; 225 226 assert(tzdram_end > tzdram_start); 227 assert(bl32_end > bl32_start); 228 assert(bl32_image_ep_info.pc > tzdram_start); 229 assert(bl32_image_ep_info.pc < tzdram_end); 230 231 /* relocate BL32 */ 232 if (bl32_start >= tzdram_end || bl32_end <= tzdram_start) { 233 234 INFO("Relocate BL32 to TZDRAM\n"); 235 236 memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc, 237 (void *)(uintptr_t)bl32_start, 238 bl32_img_info.image_size); 239 240 /* clean up non-secure intermediate buffer */ 241 zeromem16((void *)(uintptr_t)bl32_start, 242 bl32_img_info.image_size); 243 } 244 } 245 246 /* Early platform setup for Tegra SoCs */ 247 plat_early_platform_setup(); 248 249 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ? 250 "Denver" : "ARM", read_mpidr()); 251 } 252 253 /******************************************************************************* 254 * Initialize the gic, configure the SCR. 255 ******************************************************************************/ 256 void bl31_platform_setup(void) 257 { 258 uint32_t tmp_reg; 259 260 /* Initialize the gic cpu and distributor interfaces */ 261 plat_gic_setup(); 262 263 /* 264 * Initialize delay timer 265 */ 266 tegra_delay_timer_init(); 267 268 /* 269 * Setup secondary CPU POR infrastructure. 270 */ 271 plat_secondary_setup(); 272 273 /* 274 * Initial Memory Controller configuration. 275 */ 276 tegra_memctrl_setup(); 277 278 /* 279 * Set up the TZRAM memory aperture to allow only secure world 280 * access 281 */ 282 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 283 284 /* Set the next EL to be AArch64 */ 285 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; 286 write_scr(tmp_reg); 287 288 INFO("BL3-1: Tegra platform setup complete\n"); 289 } 290 291 /******************************************************************************* 292 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit 293 ******************************************************************************/ 294 void bl31_plat_runtime_setup(void) 295 { 296 /* Initialize the runtime console */ 297 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, 298 TEGRA_CONSOLE_BAUDRATE); 299 } 300 301 /******************************************************************************* 302 * Perform the very early platform specific architectural setup here. At the 303 * moment this only intializes the mmu in a quick and dirty way. 304 ******************************************************************************/ 305 void bl31_plat_arch_setup(void) 306 { 307 unsigned long bl31_base_pa = tegra_bl31_phys_base; 308 unsigned long total_base = bl31_base_pa; 309 unsigned long total_size = BL32_BASE - BL31_RO_BASE; 310 unsigned long ro_start = bl31_base_pa; 311 unsigned long ro_size = BL31_RO_LIMIT - BL31_RO_BASE; 312 const mmap_region_t *plat_mmio_map = NULL; 313 #if USE_COHERENT_MEM 314 unsigned long coh_start, coh_size; 315 #endif 316 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 317 318 /* add memory regions */ 319 mmap_add_region(total_base, total_base, 320 total_size, 321 MT_MEMORY | MT_RW | MT_SECURE); 322 mmap_add_region(ro_start, ro_start, 323 ro_size, 324 MT_MEMORY | MT_RO | MT_SECURE); 325 326 /* map TZDRAM used by BL31 as coherent memory */ 327 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { 328 mmap_add_region(params_from_bl2->tzdram_base, 329 params_from_bl2->tzdram_base, 330 BL31_SIZE, 331 MT_DEVICE | MT_RW | MT_SECURE); 332 } 333 334 #if USE_COHERENT_MEM 335 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); 336 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; 337 338 mmap_add_region(coh_start, coh_start, 339 coh_size, 340 MT_DEVICE | MT_RW | MT_SECURE); 341 #endif 342 343 /* add MMIO space */ 344 plat_mmio_map = plat_get_mmio_map(); 345 if (plat_mmio_map) 346 mmap_add(plat_mmio_map); 347 else 348 WARN("MMIO map not available\n"); 349 350 /* set up translation tables */ 351 init_xlat_tables(); 352 353 /* enable the MMU */ 354 enable_mmu_el3(0); 355 356 INFO("BL3-1: Tegra: MMU enabled\n"); 357 } 358 359 /******************************************************************************* 360 * Check if the given NS DRAM range is valid 361 ******************************************************************************/ 362 int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 363 { 364 uint64_t end = base + size_in_bytes - 1; 365 366 /* 367 * Check if the NS DRAM address is valid 368 */ 369 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END) || 370 (base >= end)) { 371 ERROR("NS address is out-of-bounds!\n"); 372 return -EFAULT; 373 } 374 375 /* 376 * TZDRAM aperture contains the BL31 and BL32 images, so we need 377 * to check if the NS DRAM range overlaps the TZDRAM aperture. 378 */ 379 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) { 380 ERROR("NS address overlaps TZDRAM!\n"); 381 return -ENOTSUP; 382 } 383 384 /* valid NS address */ 385 return 0; 386 } 387