1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 18 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <arch.h> 28#include <asm_macros.S> 29#include <platform_def.h> 30#include <pmu_regs.h> 31 32 .globl clst_warmboot_data 33 34 .macro sram_func _name 35 .cfi_sections .debug_frame 36 .section .sram.text, "ax" 37 .type \_name, %function 38 .func \_name 39 .cfi_startproc 40 \_name: 41 .endm 42 43#define CRU_CLKSEL_CON6 0x118 44 45#define DDRCTL0_C_SYSREQ_CFG 0x0100 46#define DDRCTL1_C_SYSREQ_CFG 0x1000 47 48#define DDRC0_SREF_DONE_EXT 0x01 49#define DDRC1_SREF_DONE_EXT 0x04 50 51#define PLL_MODE_SHIFT (0x8) 52#define PLL_NORMAL_MODE ((0x3 << (PLL_MODE_SHIFT + 16)) | \ 53 (0x1 << PLL_MODE_SHIFT)) 54#define MPIDR_CLST_L_BITS 0x0 55 /* 56 * For different socs, if we want to speed up warmboot, 57 * we need to config some regs here. 58 * If scu was suspend, we must resume related clk 59 * from slow (24M) mode to normal mode first. 60 * X0: MPIDR_EL1 & MPIDR_CLUSTER_MASK 61 */ 62.macro func_rockchip_clst_warmboot 63 adr x4, clst_warmboot_data 64 lsr x5, x0, #6 65 ldr w3, [x4, x5] 66 str wzr, [x4, x5] 67 cmp w3, #PMU_CLST_RET 68 b.ne clst_warmboot_end 69 ldr w6, =(PLL_NORMAL_MODE) 70 /* 71 * core_l offset is CRU_BASE + 0xc, 72 * core_b offset is CRU_BASE + 0x2c 73 */ 74 ldr x7, =(CRU_BASE + 0xc) 75 lsr x2, x0, #3 76 str w6, [x7, x2] 77clst_warmboot_end: 78.endm 79 80.macro rockchip_clst_warmboot_data 81clst_warmboot_data: 82 .rept PLATFORM_CLUSTER_COUNT 83 .word 0 84 .endr 85.endm 86 87 /* ----------------------------------------------- 88 * void sram_func_set_ddrctl_pll(uint32_t pll_src) 89 * Function to switch the PLL source for ddrctrl 90 * In: x0 - The PLL of the clk_ddrc clock source 91 * out: None 92 * Clobber list : x0 - x3, x5, x8 - x10 93 * ----------------------------------------------- 94 */ 95 96 .globl sram_func_set_ddrctl_pll 97 98sram_func sram_func_set_ddrctl_pll 99 /* backup parameter */ 100 mov x8, x0 101 102 /* disable the MMU at EL3 */ 103 mrs x9, sctlr_el3 104 bic x10, x9, #(SCTLR_M_BIT) 105 msr sctlr_el3, x10 106 isb 107 dsb sy 108 109 /* enable ddrctl0_1 idle request */ 110 mov x5, PMU_BASE 111 ldr w0, [x5, #PMU_SFT_CON] 112 orr w0, w0, #DDRCTL0_C_SYSREQ_CFG 113 orr w0, w0, #DDRCTL1_C_SYSREQ_CFG 114 str w0, [x5, #PMU_SFT_CON] 115 116check_ddrc0_1_sref_enter: 117 ldr w1, [x5, #PMU_DDR_SREF_ST] 118 and w2, w1, #DDRC0_SREF_DONE_EXT 119 and w3, w1, #DDRC1_SREF_DONE_EXT 120 orr w2, w2, w3 121 cmp w2, #(DDRC0_SREF_DONE_EXT | DDRC1_SREF_DONE_EXT) 122 b.eq check_ddrc0_1_sref_enter 123 124 /* 125 * select a PLL for ddrctrl: 126 * x0 = 0: ALPLL 127 * x0 = 1: ABPLL 128 * x0 = 2: DPLL 129 * x0 = 3: GPLLL 130 */ 131 mov x5, CRU_BASE 132 lsl w0, w8, #4 133 orr w0, w0, #0x00300000 134 str w0, [x5, #CRU_CLKSEL_CON6] 135 136 /* disable ddrctl0_1 idle request */ 137 mov x5, PMU_BASE 138 ldr w0, [x5, #PMU_SFT_CON] 139 bic w0, w0, #DDRCTL0_C_SYSREQ_CFG 140 bic w0, w0, #DDRCTL1_C_SYSREQ_CFG 141 str w0, [x5, #PMU_SFT_CON] 142 143check_ddrc0_1_sref_exit: 144 ldr w1, [x5, #PMU_DDR_SREF_ST] 145 and w2, w1, #DDRC0_SREF_DONE_EXT 146 and w3, w1, #DDRC1_SREF_DONE_EXT 147 orr w2, w2, w3 148 cmp w2, #0x0 149 b.eq check_ddrc0_1_sref_exit 150 151 /* reenable the MMU at EL3 */ 152 msr sctlr_el3, x9 153 isb 154 dsb sy 155 156 ret 157endfunc sram_func_set_ddrctl_pll 158